JPH06245025A - Image sensor, multichip type image sensor and signal processing circuit - Google Patents

Abstract

PURPOSE:To quicken signal reading by alternately outputting the signals of odd/even picture elements of a sensor chip with the timing of deviating them by half a period only in respective output stable periods from the sensor chip and synthesizing them on a substrate outside the chip. CONSTITUTION:This circuit is provided with plural disposed picture elements, a sensor chip provided with a first output line 11 outputting a signal from the odd picture element among the plural picture elements, a second output line 12 outputting a signal from the even picture element among the plural picture elements and a means 14 outputting a signal from the plural picture elements alternately to the first and second output lines with the timing of deviating the odd and picture elements each other by half a period; and a means synthesizing signals from the first and second signal lines 11 and 12 outside the sensor chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor of a document reading device mainly used in facsimiles, copying machines and the like.

The present invention relates to a signal processing circuit for receiving an output signal of an image sensor and outputting a signal for printing on paper or the like.

[0003]

2. Description of the Related Art (Conventional example of image sensor) Conventionally, as a document reading apparatus, a contact type multi-chip image sensor using, for example, a short-focus image forming element array is known. 7 to 13 show an example of such a document reading apparatus, and FIG. 7 is a perspective view showing the appearance of the document reading apparatus.
Is a sectional view taken along the line AA ', FIG. 9 is a perspective view of a substrate on which a sensor chip is mounted, FIG. 10 is a sectional view taken along the line BB', FIG. 11 is a perspective view of a substrate on which an LED is mounted, and FIG. FIG. 13 is a perspective view showing the outer appearance of a facsimile machine using the apparatus.
Is a sectional view taken along the line CC ′.

As shown in FIGS. 7 and 8, a transparent glass plate 201 which is in contact with the document surface is attached to the upper surface of the casing 200, and L
The substrate 210 on which the EDs 211 are arranged is provided in the housing 200 at a predetermined angle so that the emitted light 212 of the LED 211 is reflected by the original surface in contact with the upper surface of the transparent glass plate 201, and the reflection of the transparent glass plate 201 is performed. An optical system 209 that allows light 213 to pass therethrough, and a substrate 50 corresponding to the optical system 209.
A plurality of line sensors 1 provided above are provided in a housing 200. And, for the above optical system, for example, a trade name "SELHOC lens array" (manufactured by Nippon Sheet Glass Co., Ltd.)
The short-focus imaging element array described above is adopted.

As shown in FIGS. 9 and 10, the line sensor 1 is covered with a protective film 206 on the substrate 50 to protect the wiring portion 208, and the substrate 50 is covered with a casing 200.
It is supported by a bottom plate 205 which is engaged with a rubber plate 207. As shown in FIG. 7, end plates 203 are attached to both ends of the casing 200 with screws 204. Further, the housing 200 is provided with a connector 202 for inputting / outputting an external power source such as a facsimile main body and a control signal.
Is provided.

As shown in FIGS. 12 and 13, such a contact type multi-chip image sensor 110 is arranged, for example, at a document reading position of a facsimile through a fixing metal fitting 109. Here, a document insertion opening 103 is provided at the front edge of the facsimile main body 100.
A slit 105 is formed in parallel with the guide stage 104, and a guide piece 106 that determines the insertion position of the original is slidably attached to the slit 105. In addition, a keyboard panel 101 and an operation message display unit 1 are provided on the front upper surface of the facsimile main body 100.
07 is arranged, and the document outlet 102 is provided after that. The original 118 inserted from the original insertion port 103 reaches the feeding roller 108 via the separating piece 117, passes between the platen roller 116 and the image sensor 110, and is ejected to the original taking-out port 102. A roll-shaped recording paper 114 is housed in the rear part of the facsimile main body 100, and its end is taken out to the outside via a platen roller 115. The recording head 111 is located at the position of the platen roller 115. The information is recorded by. 112 in the figure
Is a system control board for the facsimile.
Reference numeral 13 is a power supply unit.

FIG. 14 is an equivalent circuit diagram showing an example of a circuit configuration in the chip of the line sensor 1. In the figure, reference numeral 2 denotes a sensor of a bipolar transistor structure (hereinafter referred to as a bipolar sensor) which forms a pixel of the line sensor 1, accumulates electric charges corresponding to incident light to the pixel in a base region, and outputs a signal to an emitter. 3) is a constant voltage source for resetting the base voltage of the bipolar sensor 2,
Reference numeral 4 denotes a PMO for controlling the timing of resetting the base voltage of the bipolar sensor 2 to the voltage of the constant voltage source 3.
S transistor, 5 is a constant voltage source for resetting the emitter voltage of the bipolar sensor 2, 6 is an nMOS transistor for controlling the timing of resetting the emitter voltage of the bipolar sensor 2 to the voltage of the constant voltage source, 7 Is a transfer capacitor for temporarily holding the signal output to the emitter of the bipolar sensor 2, 8 is a constant voltage source for resetting the voltage of the transfer capacitor 7, and 9 is a constant voltage source for the voltage of the transfer capacitor 7. An nMOS transistor for controlling the timing of resetting to the voltage of 8, 11 and 12 are output lines for outputting signals of odd pixels and even pixels from the transfer capacitor 7, and 13 is a signal temporarily held in the transfer capacitor 7. NMOS transistor for controlling the timing of outputting the signal to the output lines 11 and 12, and 14 to the gate of the nMOS transistor 13. Outputs the following pulse, the shift register for sequentially outputting the temporarily stored signal to the transfer capacitor 7 on the output line 11, 12, 15 and 16 each output line 1
NMOS transistors for selecting the signals output to 1 and 12, 19 are constant voltage sources for resetting the output lines 11 and 12, and 17 and 18 are output lines 11 and 12 to the voltage of the constant voltage source 19, respectively. An nMOS transistor for controlling the reset timing, 20 is a buffer amplifier for outputting the signal selected by the nMOS transistors 15 and 16, 21 is a constant voltage source for resetting the input of the buffer amplifier 20, 22 Is an nMOS transistor for controlling the timing of resetting the input of the buffer amplifier 20 to the voltage of the constant voltage source 21, 23
Is a capacitance for sampling and holding the output of the buffer amplifier 20, and 24 is nM for controlling the timing of sampling and holding the output of the buffer amplifier 20.
OS transistor, 25 is a capacitance for clamping the sampled and held signal, 26 is a constant voltage source for clamping, 27 is an nMOS transistor for controlling the timing of clamping to the voltage of the constant voltage source 26, and 28 is a clamp. A buffer amplifier for outputting the generated signal, and 29 is an nMOS transistor for selecting a chip.

FIG. 15 shows the structure of the substrate 50.
Reference numeral 0 is a common output line obtained by synthesizing the output of each chip via the nMOS transistor 29 for chip selection provided in each chip.

The signal read operation of the image sensor having the above-mentioned structure will be described with reference to the equivalent circuit diagram of FIG. 14 and the timing chart of FIG.

First, the voltage of the transfer capacitor 7 is reset to the voltage of the constant power source 8 by setting the pulse φ _CR to the high level. Next, the pulse φ _T becomes High level, and the signal of each pixel output to the emitter of the bipolar sensor 2 is transferred to the transfer capacitor 7. Next, the pulse φ _BR goes to the Low level, and then the pulse φ _ER goes to the High level, whereby the base and the emitter of the bipolar sensor 2 are reset to the voltages of the constant voltage sources 3 and 5, respectively, and the bipolar sensor 2 Enters the accumulation state.

The signal temporarily held in the transfer capacitor 7 is read out to the output lines 11 and 12 alternately by the output pulses SR1 to SR8 of the shift register 14 so that the odd and even pixels are alternately read out. 12 are alternately reset. Further, the pulse φ _SH and the pulse φ _R are alternately set to the high level, so that the signal becomes the pulse φ _R.
Becomes a signal clamped during the period of High level.

To select each chip, the pulse φ _SW1 is first set to Hi.
The first chip is selected when the gh level is reached,
While the signals of all the pixels of the first chip are output, the output of only the first chip is output to the common output line 30, and when the output of the first chip is completed, the chip outputs of the second chip and the subsequent chips are output one chip at a time. It is output to the common output line 30.

In this way, document reading is performed by the multichip type image sensor composed of a plurality of chips.

(Conventional Example of Signal Processing Circuit) Conventionally, in order to convert an output signal of an image sensor into binary data for printing an image on paper on a facsimile, for example,
Signal processing was performed by a signal processing circuit as shown in the block diagram of FIG.

In FIG. 17, reference numeral 41 denotes an image sensor which irradiates a document with light and photoelectrically converts reflected light from the document to output an electric signal corresponding to the document. Reference numeral 42 denotes an analog output signal of the image sensor 41. Digitally converted, 6bi
An analog-digital conversion circuit that outputs a digital signal of t, 43 is an edge emphasis circuit that detects an edge of an image from the output of the A / D conversion circuit 42, and emphasizes the edge, 44 is an output signal of the edge emphasis circuit 43 A brightness-density conversion circuit for brightness-density conversion, 45 is a binarization circuit for binarizing the output signal of the brightness-density conversion circuit 44, and 46 is shading for inputting to the + side reference voltage of the A / D conversion circuit 42. Shading memory for holding data, and 47 is a line memory for temporarily holding data required for edge detection and binarization.

In the signal processing circuit having the above structure, first,
The image sensor 41 reads white provided on the device, A / D-converts it by the A / D conversion circuit 42, and then stores it in the shading memory 46.

Next, the original is read line by line, the white output read in advance for each pixel is read from the shading memory 46, and is used as a reference voltage on the + side of the A / D conversion circuit 42. Sensor 4
Input a constant voltage source that is approximately equal to the black output of 1. As described above, the output signal of each pixel is subjected to the standardized A / D conversion between the black output and the white output which is different between the pixels, and the shading caused by the light amount variation of the light source can be corrected.

Next, shading correction is performed to obtain 6 bitA.
The output of the A / D conversion circuit 42, which has been D / D converted, is input to the line memory 47, the edge of the image is detected by the edge emphasis circuit 43 from the read data of the preceding and following lines, and the edge of the original data is emphasized. The output thus produced is input to the luminance-density conversion circuit 44. The brightness-density conversion circuit 44 converts the sensor output signal (luminance signal) into a density signal and outputs it according to the γ table shown in FIG. Further, in the binarization circuit 45, the density signal is used in the line memory 47,
Pseudo gradation image processing such as dither method or error diffusion method is performed and binary data is output.

[0019]

However, in the conventional example of the above multi-chip type image sensor, the odd pixel,
Since the signal output of an even pixel is output to the same output terminal in the sensor chip, the reset time of the output line and the output rise time are included in the signal read time per pixel, which impedes the speeding up of signal read. Was there.

Further, in the conventional example of the above signal processing circuit, 6
Since the sensor output that has become a bit digital signal is converted into a density signal by the γ table in the brightness-density conversion circuit, the gradation of the density signal becomes discontinuous in the high density area of the document, and the number of gradations is reduced. .

Therefore, when the sensor output signal has a noise of more than one gradation, if a variation of two gradations is expected in the digital signal, the density signal has a maximum of 10 as shown in FIG.
Since there are variations in gradation and they appear in printed images, improvement has been desired.

[0022]

An image sensor according to the present invention comprises a plurality of arranged pixels, a first output line to which signals from odd-numbered pixels of the plurality of pixels are output, and the plurality of pixels. The second output line to which the signal from the even pixel is output, and the plurality of the second output line to the first output line and the second output line alternately at the timings of the odd pixel and the even pixel shifted by a half cycle. And a means for outputting a signal from the pixel, and a means for synthesizing a signal from the first output line and a signal from the second output line outside the sensor chip. It is characterized by having.

The multi-chip type image sensor of the present invention is formed by arranging a plurality of sensor chips in the image sensor of the present invention.

The signal processing circuit of the present invention reads image information by an image sensor, obtains an electric signal corresponding to the image information from the image sensor, performs analog-digital conversion on the electric signal, and converts the electric signal into a digital signal. According to a predetermined γ table, in the signal processing circuit for converting the density signal of the print image, the number of bits of the digital signal converted by the γ table is made larger than the number of bits of the density signal after conversion. To do.

[0025]

According to the image sensor and the multi-chip type image sensor of the present invention, the signals of the odd-numbered pixel and the even-numbered pixel are read out by shifting the phase by a half cycle, and output to separate output terminals inside the sensor chip, and the signals outside the sensor chip are output. The signals of odd pixels and even pixels are combined on the same output line, and the rise time of the signal and the reset time of the output line are excluded from the signal read time of the entire image sensor to speed up signal read. .

Further, in the signal processing circuit of the present invention, the number of bits of the luminance signal is made larger than the number of bits of the density signal in the luminance-density conversion, thereby reducing the gradation skip of the density signal and variation in the sensor output. And the density variation in the printed image are equalized.

[0027]

Embodiments of the present invention will be described in detail below with reference to the drawings. (Embodiment of Image Sensor of the Present Invention) As an embodiment of the image sensor of the present invention, a multi-chip type image sensor will be taken up, but the present invention can be applied to one sensor chip, in particular, a multi-chip type image sensor. It is not limited to.

FIG. 1 is an equivalent circuit diagram showing an example of a circuit configuration in a chip of a line sensor 1 embodying the present invention, and FIG. 2 is a diagram showing a substrate on which a plurality of line sensors are mounted. The same components as those in FIGS. 14 and 15 are designated by the same reference numerals and the description thereof will be omitted.

In FIGS. 1 and 2, 20 and 31 are output buffer amplifiers (not shown in FIG. 1) for outputting signals of odd-numbered pixels and even-numbered pixels, and 23 and 32 are output buffer amplifiers 20. , 31 are capacitors for sampling and holding the output, 24 and 33 are nMOS transistors for controlling sampling and holding timings, 25 and 34 are capacitors for clamping signals,
Reference numerals 26 and 35 denote constant voltage sources that supply a clamp voltage (note that the constant voltage sources are not shown in FIG. 1 and are shown as the constant voltage source 26 in common) 20.
7 and 36 are n for controlling the timing of clamping
MOS transistors 28, 37 are output buffer amplifiers, and 29, 38 are nMOS transistors for selecting an odd pixel and an even pixel when selecting a sensor chip to output to the common output line 30.

The signal reading operation of such a multi-chip type image sensor will be described with reference to the timing chart of FIG. The operation until the signal of each pixel is transferred to the transfer capacitor 7 is the same as the conventional example described with reference to FIG.

The pixel signals temporarily held in the transfer capacitor 7 are read out to the output line 11 by the pulses SR1 to SR8 from the shift register 14 and the output line 1 by the even pixels.
2 is read. First, the pulse SR1 is High
Then, the signal of the first pixel is read out to the output line 11, the pulse SR2 becomes High level at a timing delayed by a half cycle before the end, and the signal of the second pixel is read out to the output line 12. Further, the pulse SR1 is delayed by a half cycle before the signal reading of the second pixel is completed.
Goes to Low level, reading of the first pixel is completed,
After the output line 11 is reset by the pulse φ _R1 , the pulse SR3 becomes High level, and the signal of the third pixel is read out to the output line 11. The signal reading of the second pixel is completed at a timing delayed by a half cycle before the signal reading of the third pixel is completed, the output line 12 is reset by the pulse φ _R2 , and then the pulse SR4 becomes High level. The signals of 4 pixels are read out to the output line 12.

Thereafter, the signals of odd-numbered pixels are read out to the output line 11 and the signals of even-numbered pixels are read out to the output line 12 at a timing shifted by a half cycle.

The signal of the odd pixel output to the output line 11 is clamped to the voltage of the constant voltage source 26 by the pulse φ _S1 and the pulse φ _R1 via the amplifier 20, and the pulse φ via the output buffer / amplifier 28. _{When odd1} is High level,
It is output to the common output line 30.

Similarly, the signal of the even pixel output to the output line 12 is clamped to the voltage of the constant voltage source 35 by the pulse φ _S2 and the pulse φ _R2 via the amplifier 31, and is output via the output buffer amplifier 37. When the pulse φ _even1 is at the high level, it is output to the common output line 30.

The pulse φ _odd1 and the pulse φ _even1 respectively become High level after the signals output to the output lines 11 and 12 have sufficiently risen, and become Low level before being reset by the pulse φ _R1 and pulse φ _R2. Therefore, the signals that are sampled and held and clamped are output to the common output line 30. The pulse φ _odd1 and the pulse φ _even1 are alternately set to High level while the signal reading of the first chip is being performed, and become Low level when the signal reading of the first chip is completed. Second
The chip signal is read, the selection pulse φ _odd2 and the pulse φ _{even2 of} the second chip are alternately set to the high level, and the signals of the third and subsequent chips are sequentially read out.

The offset of the buffer amplifier after clamping, which causes a step difference between chips in the output of the multi-chip type image sensor, appears in the offset difference between the output buffer amplifiers 28 and 37 in the chip even between odd-numbered and even-numbered pixels. , Because it is clamped in the chip, amplifier 2
If the gains of 0 and 31 are given and amplification is not performed outside the chip, the final output of the image sensor will be within a level that causes no problem. (Embodiment of Signal Processing Circuit of the Present Invention) FIG. 4 is a block diagram of a signal processing circuit according to an embodiment of the present invention. The same components as those in FIG. 17 are designated by the same reference numerals.

In the figure, reference numeral 41 denotes a document which is irradiated with light,
An image sensor 42 'for photoelectrically converting the reflected light from the document and outputting an electric signal corresponding to the document, and the image sensor 4'.
An analog-to-digital conversion circuit that performs analog-to-digital conversion on the output signal of 1 and outputs an 8-bit digital signal,
Reference numeral 43 denotes an edge enhancement circuit that detects an edge of an image from the output of the A / D conversion circuit 42 'and enhances the edge, and 44' outputs the output signal (8 bits) of the edge enhancement circuit 43 to 6 bits.
Luminance-density conversion circuit for converting to a density signal of 45, a binarization circuit for binarizing the output signal of the brightness-density conversion circuit 44, and 46 for inputting to the + side reference voltage of the A / D conversion circuit 42. A shading memory for holding the shading data, and a line memory 47 for temporarily holding the data necessary for edge detection and binarization.

In the signal processing circuit having the above-described structure, the image sensor 41 first reads white in order to obtain shading correction data, converts it into an 8-bit digital signal by the A / D conversion circuit 42 ', and inputs it to the shading memory 46. .

Next, the image sensor 41 reads the original and inputs the shading data obtained in advance as a reference voltage on the + side of the A / D conversion circuit 42 'for each pixel. A voltage of a constant voltage source that is almost equal to the black output of the image sensor 41 is input to the negative reference voltage, and 8b is standardized between the black output and the white output of each pixel.
The A / D conversion circuit 42 'outputs the it digital signal.

Shading correction is performed in this way,
The sensor output signal that has become a digital signal is edge-enhanced by the edge emphasizing circuit 43, and then the brightness-density conversion circuit 4
4 ', and the .gamma. Conversion shown in FIG. 5 is performed to obtain a density signal.

Here, the gradation of the density signal is exactly the same as that of the conventional example shown in FIG. The gradation of the sensor output signal is 256 gradations in total in this embodiment.
40 gradations corresponding to 10 gradations of 8 (total 64 gradations)
Up to 56 gradations are shown.

Therefore, in the γ table shown in FIG. 5, for the gradation represented by ◯ for every four gradations, the corresponding values for all 64 gradations are used as they are. The density signal value of the gradation represented by x, which does not have a value corresponding to all 64 gradations, is a value which interpolates between the gradations represented by ◯.

Now, assuming that the sensor output variation is a little over one gradation out of all 64 gradations and five gradations out of all 256 gradations, the variation of the density signal of the image to be printed is shown by using the γ table of FIG. It becomes like 6. Here, the gradation of the sensor output signal of FIG. 6 is 256 gradations in total, and 40 gradations corresponds to 10 gradations of 64 gradations in total. Therefore, comparing 10 gradations of the sensor output signal in FIG. 19 with 40 gradations of the sensor output in FIG. 6, it can be seen that the density signal variation is improved by about 3 gradations.

As described above, the density signal variation can be reduced, and when the sensor output variation is less than or equal to one of the total 64 gray levels, a more significant difference appears.

[0045]

As described above, according to the image sensor or the multi-chip type image sensor of the present invention, the signals of the odd and even pixels of the sensor chip are alternately arranged at a timing shifted by a half cycle, and the signals from the sensor chip are changed. By outputting only the output stable period and synthesizing on the substrate outside the chip, it is possible to speed up the signal reading.

Further, according to the signal processing circuit of the present invention, when the sensor output signal is converted into the density signal of the print image, the number of bits of the sensor output signal is larger than the number of bits of the density signal γ.
By converting using the table, the S / N ratio of the image sensor output can be reflected in the printed image to the maximum extent.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing an example of a circuit configuration in a chip of a line sensor 1 embodying the present invention.

FIG. 2 is a diagram showing a substrate on which a plurality of line sensors are mounted.

FIG. 3 is a timing chart showing a signal read operation of the above embodiment.

FIG. 4 is a block diagram of a signal processing circuit according to an embodiment of the present invention.

FIG. 5 is a diagram showing a γ table for performing γ conversion.

FIG. 6 is a characteristic diagram showing a variation of an image density signal with respect to a sensor output signal.

FIG. 7 is a perspective view showing an appearance of a document reading device.

8 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 9 is a perspective view of a substrate on which a sensor chip is mounted.

10 is a sectional view taken along line BB ′ of FIG.

FIG. 11 is a perspective view of a substrate on which an LED is mounted.

FIG. 12 is a perspective view showing the outer appearance of a facsimile machine using a document reading device.

13 is a cross-sectional view taken along the line CC ′ of FIG.

FIG. 14 is a diagram showing an example of an equivalent circuit in the chip of the line sensor 1.

FIG. 15 is a diagram showing a configuration of a substrate 50.

FIG. 16 is a timing chart showing a signal reading operation of the image sensor.

FIG. 17 is a block diagram showing a conventional signal processing circuit.

FIG. 18 is a diagram showing a γ table for performing conventional γ conversion.

FIG. 19 is a characteristic diagram showing variations in the image density signal with respect to the sensor output signal.

[Explanation of symbols]

 2 Bipolar type sensor 3 Constant voltage source 4 PMOS transistor 5 Constant voltage source 6 nMOS transistor 7 Transfer capacitance 8 Constant voltage source 9 nMOS transistor 11 Odd pixel output line 12 Even pixel output line 13 nMOS transistor 14 Shift register 17 nMOS transistor 18 nMOS transistor 19 constant voltage source 20,31 buffer amplifier 23,32 sample and hold capacitance 24,33 nMOS transistor 25,34 clamp capacitance 26,35 constant voltage source 27,36 nMOS transistor 28,37 buffer -Amplifier 29,38 nMOS transistor 41 Image sensor 42 'Analog-digital conversion circuit 43 Edge enhancement circuit 44' Luminance-density conversion circuit 45 Binarization circuit 46 Shading- Mori 47 line memory

Claims (3)

[Claims] 1. A plurality of arrayed pixels, a first output line from which signals from odd-numbered pixels of the plurality of pixels are output, and a signal from even-numbered pixels of the plurality of pixels are output. A second output line, and means for alternately outputting signals from the plurality of pixels to the first output line and the second output line at timings that the odd pixel and the even pixel are shifted from each other by a half cycle. An image sensor comprising: a sensor chip provided; and means for synthesizing a signal from the first output line and a signal from the second output line outside the sensor chip. 2. A multi-chip type image sensor configured by arranging a plurality of the sensor chips according to claim 1. 3. The image information is read by an image sensor, an electric signal corresponding to the image information is obtained from the image sensor, the electric signal is analog-digital converted, and the converted digital signal is subjected to a predetermined γ table. In the signal processing circuit for converting the density signal of the print image, the number of bits of the digital signal converted by the γ table is made larger than the number of bits of the density signal after conversion.