JPH06244690A - Detection switch - Google Patents

Abstract

PURPOSE:To reduce the possibility of output abnormality caused by any fault in the output transistor of an output circuit and to predict the fault in a detection switch. CONSTITUTION:This switch is provided with an output circuit 12 for electrifying a load to be connected to an output end by the output of a switch main circuit 11. In the output circuit 12, a transistor Q3 for output use and a transistor Q4 to be operated simultaneously with the former transistor are parallelly provided. When the current drive of the transistor Q3 is abnormal, the load is electrified by the transistor Q4. When an output cable is disconnected, no load current flows but voltages Va, Vb and Vc are made different from the normal period of time. Therefore, the fault state can be detected by a fault diagnostic cirucit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch such as a photoelectric switch or a proximity switch, and more particularly to a detection switch characterized by a failure diagnosis function of its output circuit.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of a conventional proximity switch. In the figure, a power supply circuit 2 is connected to a power supply terminal 1a via a diode D3 to supply power to each block in the proximity switch. In the proximity switch, an oscillation circuit 3 that oscillates at a constant frequency, a detection circuit 4 that detects the oscillation output thereof, and a signal processing circuit 5 that determines the proximity of an object based on a decrease in the detection output are provided.
The output of the signal processing circuit 5 is output to the outside from the terminal 1c via the output circuit 6. As shown, the output circuit 6 has an output transistor Q1 to which the output of the signal processing circuit 5 is given to the base and whose emitter is connected to the terminal 1b.
The collector of the transistor Q1 is a diode D1 and a resistor R
1 to the power supply terminal 1a. A Zener diode D2 for absorbing surge is connected between the collector and the emitter of the transistor Q1, and the collector is connected to the output terminal 1c via the resistor R2. The power supply terminal 1a is connected to the power supply circuit 2 via the diode D3.

[0003]

The output circuit 6 as described above is provided.
In the conventional detection switch having the above, the surge can be absorbed by inserting a capacitor in the power supply terminal 1a, but the output terminal 1c is switched, and therefore the Zener diode D2 needs to absorb the surge. Therefore, when a large surge voltage is applied to the output circuit, it cannot be absorbed by the Zener diode ZD, and the output transistor Q1 is destroyed. When the output transistor Q1 is destroyed, the output terminal is closed as in the case where the object is detected even if the object is not detected.

The present invention has been made in view of such conventional problems, and makes it possible to generate a normal output even when the output transistor is deteriorated and to predict a failure. The purpose is to

[0005]

According to a first aspect of the present invention, there is provided a switch main circuit which is connected to a pair of power supply terminals and outputs a switch signal, and between a power supply terminal and an output terminal based on an output from the switch main circuit. An output circuit for controlling energization to a load of the switch, wherein the output circuit has a base to which an output from the switch main circuit is input, and a collector connected to a signal terminal via a resistor. , And the output from the switch main circuit is input to the base,
And a second transistor whose collector is connected to the collector of the first transistor via a diode.

According to the invention of claim 2 of the present application, the first and second transistors are respectively connected to the emitter resistors, and the input voltage applied to the bases of the first and second transistors and the first transistor An emitter voltage and an emitter voltage of the second transistor are respectively input, and a failure diagnosis circuit that outputs a failure diagnosis signal when they are not at the same logic level is featured.

[0007]

According to the present invention having such a feature, the first and second transistors are opened and closed almost simultaneously based on the output from the switch main circuit, and the current is supplied to the load. Then, even if the first transistor cannot drive the current or the saturation voltage between the collector and the emitter of the first transistor becomes high, the power is supplied to the load by the second transistor. When the second transistor is short-circuited or the output cable is short-circuited, the emitter voltage of the first transistor becomes high level. When these abnormalities occur, the base voltage and the emitter voltage of the first and second transistors are different from those in the normal state, and therefore the failure diagnosis circuit performs the failure diagnosis.

[0008]

1 is a circuit diagram showing a configuration of an output circuit portion of a detection switch according to an embodiment of the present invention. In this figure, each block from the power supply circuit 2 to the signal processing circuit 5 is the same as the conventional example, and is shown as a switch main circuit 11. The output of the switch main circuit 11 is given to the transistor Q2 of the output circuit 12. The emitter of the transistor Q2 is grounded, and the collector is connected to the input terminal of the power supply circuit 2 via the resistor R3. Diode D at terminal 1a
4 is connected to the anode, and the cathode end is connected to the resistor R3 and the power supply circuit 2 in the switch main circuit 11. Now, the base of the first transistor Q3 is connected to the collector of the transistor Q2 via the resistor R4. The emitter of the transistor Q3 is connected to the terminal 1b via the resistor R5, and the collector is connected to the terminal 1a via the resistor R6. A Zener diode D5 for absorbing surge is connected between the collector of the transistor Q3 and the terminal 1b. The collector of the transistor Q2 is connected to the second transistor Q4 via the integrating circuit of the resistor R7 and the capacitor C1.
Connected to the base of. A resistor R5 is connected between the emitter of the transistor Q4 and the terminal 1b, and its collector is connected to the collector of the transistor Q3 via a Zener diode D6. Also, the collector of the transistor Q3 is a resistor R
It is connected to the output terminal 1c through 8. The transistor Q3 is a switching transistor for opening and closing the output, and the transistor Q4 operates at substantially the same time as it, and opens and closes the output together with the transistor Q4.

Next, the operation of this embodiment will be described with reference to FIG. First, the operation during normal operation will be described. (1) When the emitter potential Va of the transistor Q2 becomes L level due to the output from the switch main circuit 11, the transistor Q3 does not operate. At this time, if the emitter potentials of the transistors Q3 and Q4 are Vb and Vc, respectively, the transistors Q3 and Q4 are in the off state, and
Vc also becomes L level. (2) When the output circuit 12 is in the normal state and the voltage Va is at the H level, the transistor Q3 is turned on and the voltage Vb becomes the H level. The transistor Q4 also turns on a little later than this, and Vc becomes H level.

Now, the operation when the collector voltage Va of the transistor Q2 of the output circuit is H level and is abnormal will be described. (3) In the abnormal state where the output transistor Q3 cannot drive current, the voltage Vb becomes L level. At this time, since the load current flows through the Zener diode D6, the transistor Q4, and the resistor R8, the voltage Vc becomes H level. Therefore, the output can be opened and closed despite the failure of the output transistor Q3.

(4) The output transistor Q3 can drive current, but when V _CE3 becomes high, V _CE3
By setting> V _CE4 + V _D6 + V _R8 , a load current flows through the Zener diode D6, the transistor Q4 and the resistor R8. Also in this case, Vb becomes L level and Vc becomes H level.

(5) When the output transistor Q3 is short-circuited and destroyed, the voltage Vb also becomes the H level when the voltage Va is at the H level. At this time, the load current does not flow through the transistor Q4 and Vc becomes L level.

(6) When the output cable connected to the terminal 1c is broken, both Vb and Vc become L level even if the voltage Va becomes H level. This is summarized as shown in FIG. Therefore, the abnormal state can be diagnosed based on the logical states of Va, Vb and Vc.

FIG. 3 is a block diagram showing the overall structure of a detection switch including such a failure diagnosis circuit 13. In this figure, each block from the power supply circuit 2 to the signal processing circuit 5 is the same as that of the conventional example, and the configuration of the output circuit 12 is the same as that of the first embodiment shown in FIG. In this embodiment, a failure diagnosis circuit 13 to which the voltages Va, Vb, Vc in the output circuit 12 are input is provided. The failure diagnosis circuit 13 is a circuit that outputs a failure diagnosis signal in the cases of (3) to (6) in FIG. 2, and is an OR circuit that receives an inverted signal of Va, Vb, and Vc, and an output of the OR circuit, for example. An AND circuit that takes the logical product of V and Va determines that none of the three inputs have the same logic level, and obtains a failure diagnostic signal. Then, the failure indicator lamp 14 is turned on according to the failure diagnosis output of the failure diagnosis circuit 13. In this way, the transistor Q2 in the output circuit is turned off and the voltage Va
When H is at the H level, a failure diagnosis signal can be output in the case of any of the failures in FIGS. 2 (3) to (6).
Further, even when the output transistor Q3 fails and the current cannot be driven, the second transistor Q4 can play an auxiliary role of the output transistor.

Although the zener diode D6 is connected between the collectors of the transistor Q4 and the transistor Q3 in this embodiment, a diode D7 may be used instead of the zener diode as shown in FIG.

[0016]

As described in detail above, according to the present invention, the load current can be supplied by the second transistor even when the output transistor is short-circuited, and the possibility of malfunction is reduced. be able to. Further, in the invention of claim 2 of the present application, since the state in which the output transistor is broken or the state in which the residual voltage is increased before the output transistor is broken can be diagnosed as a failure state, failure prediction can be performed. can get.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an output circuit of a detection switch according to an embodiment of the present invention.

FIG. 2 is a diagram showing normal and abnormal states of a transistor of this embodiment and changes in output of each part.

FIG. 3 is a block diagram showing an overall configuration of a detection switch according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of an output circuit according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional detection switch.

[Explanation of symbols]

 11 switch main circuit 12 output circuit 13 failure diagnosis circuit 14 failure indicator light Q1 to Q4 transistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Motoshi Tomoshi 10 No. 10 Hanazono Doudocho, Ukyo-ku, Kyoto City, Kyoto Prefecture Omron Co., Ltd. OMRON Corporation

Claims (2)

[Claims] 1. A switch main circuit which is connected to a pair of power supply terminals and outputs a switch signal; and an output circuit which controls energization of a load between a power supply terminal and an output terminal based on an output from the switch main circuit. In the detection switch having: the output circuit, the output from the switch main circuit is input to the base, the collector is connected to a signal terminal via a resistor, and the output from the switch main circuit A second transistor which is input to the base and whose collector is connected to the collector of the first transistor via a diode. 2. The first and second transistors are respectively connected to emitter resistors, and the input voltage applied to the bases of the first and second transistors, the emitter voltage of the first transistor, and the Second
2. The detection switch according to claim 1, further comprising a failure diagnosis circuit which outputs a failure diagnosis signal when the emitter voltages of the respective transistors are input to each other and they are not at the same logic level.