JPH06244374A - Matrix type ferroelectric memory - Google Patents

Abstract

PURPOSE: To enable very large-scale integration, without deteriorating residual polarization by composing a semiconductor element of a pnp type lateral transistor(TR) and an npn type longitudinal TR and connecting the base part of one TR to the collector part of the other. CONSTITUTION: On a p-type Si substrate 31, an n-well region 32, p<+> -diffusion layers 34 and 35, an n<+> -emitter region 36 are formed to constitute a semiconductor element in two-terminal switch structure consisting of a longitudinal npn TR and a lateral pnp TR. To a field oxide film 32 on the surface of the substrate 31, a ferroelectric capacitor constituted of a base substrate 39, a ferroelectric thin film 40, and an upper electrode 41 is connected across a protection film 38, in series with the semiconductor element. Further, the upper electrode 41 and an emitter region 36 are connected by a 3rd lead-out electrode 45. Thus, a ferroelectric capacitor is formed on the protection film 38 of SiO2 , so that the capacitor becomes extremely stable and a very large-scale integration can be actualized, without deterioration in residual polarization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type ferroelectric memory, and more particularly to an improvement of a matrix type ferroelectric memory using a two-terminal switch.

[0002]

2. Description of the Related Art Conventionally, it is generally known that a ferroelectric material has a hysteresis characteristic, and data can be recorded by utilizing this characteristic. FIG. 24 is a hysteresis characteristic diagram, in which the horizontal axis represents the electric field (or voltage) E and the vertical axis represents the polarization amount P. In FIG. 1, two polarization states A when the voltage is 0,
By corresponding digital signals "1" and "0" to each C, it can be used as a memory. Now, assume that a "1" signal is stored in this ferroelectric substance and the state of polarization A is present. At this time, when a positive read pulse E _r is applied, the polarization shifts from A to B and returns to C. At this time, the amount of charge generated from the ferroelectric substance and flowing into the read circuit is Q _CB -Q _AB = Q _SW . If there is a C state having a "0" signal, Q _AB = Q _BA , and the total is "0". by this,
Can be used as memory. An attempt to utilize such characteristics as a memory is disclosed in Japanese Patent Application Laid-Open No. 55-126905.
The method disclosed herein is described in "Polar Dielectrics and
thin applications "J. C. Burfootand George
W. Detailed in Tayler.

In an attempt to construct a memory by combining a ferroelectric thin film having such characteristics as an extremely thin film (for example, about 100 nm to 400 nm) on a Si wafer and combining it with a transistor for selecting a memory cell, For example, J. F. Scott, and C.I. A. P. Araujo "Sci
ence “246” p1400 (1989). Further, in Japanese Patent Laid-Open No. 1-158691, “1” is stored in the ferroelectric film in the form of remanent polarization in a pair of the ferroelectric film and the passcade transistor. A method for comparing and reading "/ 0" information is disclosed in Japanese Patent Laid-Open No. 1-278063.
It has been proposed to use a ferroelectric substance having a relaxation effect in the M-type memory cell. On the other hand, Japanese Laid-Open Patent Publication No. 2-177077 makes a half-selection by configuring one memory cell with ferroelectric capacitors connected to four driver circuits and using elements with nonlinear threshold characteristics of a diode before and after the capacitor. It takes a configuration to avoid the situation.

In such a state, we have already disclosed in JP-A-2-
As shown in JP-A-154388 and JP-A-2-154389, a nondestructive driving method for a ferroelectric thin film having a matrix structure is proposed. As shown in FIG. 25, this has a simple matrix structure, the upper electrode 1 forms a stripe as an X-line, the lower electrode 2 forms a stripe as a Y-line, and a ferroelectric thin film sandwiched between them. Area 3 is used as a memory cell. In this case, the hysteresis characteristic of the present ferroelectric substance is re-set at a write voltage of 1/2 × V _W or V _W × 1/3 as shown in FIGS. 26 (A) and (B).
There is no change in manent polarization (spontaneous polarization), and it is necessary to have P _S at V _W during writing and reading. However, the problem is that the actual hysteresis is
Like from A to E _C, there is a gradual change. The most important thing is the so-called “Lack of true E _C ”, that is, on Hysteresis, as shown in FIG. 1, E _C (coercive electric field) or V _C (= E _c · d (thickness)) (coercive voltage) ) Exists, but the pulse is less than this V _c

Disturbance pulsing a very large number of pulses
When given as es (disturbance pulse), the remanent polarization P _r deteriorates as shown in FIG. That is, first, the polarization is written in the direction of the angle by the write pulse, and then the disturbance pulse is applied a plurality of times at the pulse train column voltage V _C / k of V _C or less (where k is a given scaling factor).

After that, the remaining charge is measured by using a read pulse. If the remanent polarization does not deteriorate below the coercive voltage V _C , a plurality of disturbances below V _C may occur.
It should not deteriorate even with nce pulses.

[0007]

However, as is clear from the evaluation results of FIG. 26, P _r deteriorates immediately at V _c and also deteriorates at V _C / 3 several hundreds of times. On the other hand, V _c / 5
But it is slightly deteriorated. This is a fatal defect such as information destruction of non-selected cells. In order to solve this problem, a memory cell of the same type using a diode or the like as a two-terminal switch has been proposed. For example, the above-mentioned JP-A-2-154388 and JP-A-2-154389 are available.

The present invention has been made in consideration of such circumstances, and an object thereof is to provide a matrix type ferroelectric memory capable of ultra-high integration without deterioration of remanent polarization.

[0009]

The present inventor has found the problems of the prior art by simulation and evaluation of an actual device. 28A and 28B are simulation methods for observing the effect of the two-terminal switch. This simulation method is described in T.W. Mihara and others “Proceedings o
f Internationalization Symposium of Integrated Fer
roelectrics p (1992). Considering two types of two-terminal switches, FIG. 29 (A) shows a type in which the current changes from I _{min to} I _max with the threshold voltage (Vth).
29 (B) is a type in which the current changes from C _{min to} C _max with Vth. The simulation result is far from the ideal hysteresis characteristic of FIG. 27, as shown in the serial model of FIG. 29 (D). The results of connecting the two-terminal switch with a Zener diode and a ferroelectric thin film as a PZT thin film in series are shown in FIGS. 30 (A) and 30 (B). It shows the characteristics as simulated. Here, the cause is that I _max or C _max of the two-terminal switch is insufficient.

2P before and after E _C (or V _C ) in ferroelectrics
The charge of _r deteriorates all at once. That is, I _sw = 2 (P _r / Δ
t) · A _f = 2P _r A _f / C _L · R _L. here,
2P _r is twice the remanent polarization, A _f is the area, C _L is the charge capacity, and R _L is the charge resistance. The value of this I _sw is C _L · R _C
Is small and is several ns, I _sw is as large as several kiloamperes per cm. That is, when I _{max of the} two-terminal switch is less than this, the voltage of the ferroelectric thin film is slowly improved and the hysteresis does not change sufficiently quickly.

Therefore, the present inventor decided to use a pnpn two-terminal switch. The basic idea is already disclosed in Japanese Patent Application Laid-Open No. 2-154389 filed by the present applicant, but it is a mere conceptual diagram, and its effect producing method, effective producing method, and device structure have been clarified. There wasn't.

An object of the present invention is to provide a pnpn type two-terminal switch which is more optimal and characteristically compatible with the new two-terminal switch of the present inventor. 1 (A) to (C)
Shows a conceptual diagram of the present invention. 1A is a hysteresis characteristic of a ferroelectric thin film, FIG. 1B is an IV characteristic of a pnpn two-terminal switch, and FIG. 1C is a Q characteristic of a two-terminal switch.
Each shows -V hysteresis characteristic. Further, P _r represents remanent polarization, and V _C represents coercive electric field. I-V characteristic is OF up to V _th
In the F state, the resistance of the two-terminal switch is lowered at the same time when it is turned on thereafter, from V _sat to V _th (V _th −
The absolute value of V _sat ) works as a dead zone and there is no problem such as “Lack of true E _c ” during this period. That is, no information destruction of the non-selected cells or the semi-selected cells (only X or Y is selected) is eliminated in this dead area.

Now, the method and device structure for reducing the pnpn type two-terminal switch is the present invention. Figure 3
(A) shows an equivalent circuit of this device. Equivalently, p
This is a combination of the base of the np type bipolar transistor 11 and the npn type bipolar transistor 12, and one transistor is connected to the collector of the other.
When a voltage is applied (+ on the X line and − on the Y line), one of the transistors has a CE reverse breakdown voltage, so that no current flows. However, if it exceeds the breakdown voltage, the breakdown voltage _{= BV CEO + V BE (I} B) However, BV _CEO: breakdown voltage between the collector and emitter of npn transistors, V _BE: forward voltage between the base and emitter of the pnp transistor , Most of them are BV _CEO (npn type transistor), but when it exceeds this, 1 / β times of the emitter current of the npn type transistor flows from the base, and this α times (α amplification factor of the pnp type transistor) is greater than I _E. Flowing. However, β shows a current amplification factor. That is, β (npn type transistor) × β (pnp type transistor) = 1

When the operating point is determined by the saturation condition of the condition (1), it is turned on. A current (I) -voltage (V) curve is shown in FIG. FIG. 4 is an actual structural diagram. However,
Reference numeral 13 is a p-type Si substrate, 14 is an n-well region surrounded by a field oxide film 15, and 16 and 17 are p ^+. Type diffusion layer, 18 is a dielectric capacitance, W _B is p ⁺ The distance between the mold diffusion layers 16 and 17 is shown. in this case,

Vth ⁺ Is approximately equal to BV _CEO (npn type transistor), and Vth ⁻ Is approximately equal to BV _ECO (pnp type transistor), and when V _C is approximately equal to 1.0 V when actually combined with a memory as shown in FIG. 5, FE (dielectric capacitance) +2 terminal switch = 3.0
It is desirable to turn on at V. In addition, 19 in FIG. 5 is 2
Indicates a terminal switch. That is, BV _CEO (npn) is approximately B
It must be equal to V _ECO and 2.0V. Therefore, the lateral (horizontal) transistor is selected as the pnp transistor of the two-terminal switch in the pnpn, and the vertical (vertical) transistor type is selected as the npn transistor. Now, this is the BV _CEO (pnp-type transistor), in the case of pnp type transistor determines the concentration and base width W _B of the n-well region. Therefore, the surface concentration of the n-well region is 1 ×
10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ and W _B are preferably 0.5 to ³ μm. Next, regarding BV _CEO (npn), similarly, the concentration and width of the base region of the vertical npn-transistor are determined. Therefore, the base concentration is 1 × 10 ¹⁸ cm ^-3 to 1 ×
10 ²⁰ cm ^-3, W _B is 300nm~1000nm is desirable.

That is, according to the present invention, the p-type base substrate, the n-type first semiconductor layer formed in the element region of the base substrate, and the surface of the first semiconductor layer are formed separately from each other. A semiconductor element including a semiconductor type two-terminal switch having a p-type second semiconductor layer and an n-type third semiconductor layer formed on the surface of the second semiconductor layer, and an insulating film on the underlying substrate. A matrix type ferroelectric memory comprising a ferroelectric capacitor having a base electrode, a ferroelectric thin film, and an upper electrode, the ferroelectric capacitor being formed via Is pnp
Type horizontal transistor and an npn vertical transistor, the base portion of the horizontal transistor is common with the collector portion of the vertical transistor, and the collector portion of the horizontal transistor is common with the base portion of the vertical transistor. It is a matrix type ferroelectric memory characterized in that

In the present invention, DC magnetron sputtering is generally used as a method for forming the base electrode, and RF is used.
-Sputtering or EB-vapor deposition may be used. The thickness of the base electrode is preferably in the range of 50 nm to 500 nm. Between the protective film and the base electrode, a base layer such as T
A layer made of i, Ta, TiW, TiN, W, Cr, Ni may be used.

In the present invention, the ferroelectric thin film is usually formed after depositing the base electrode on the entire surface, because this is better in uniformity and characteristics. As the method of forming the ferroelectric thin film, in addition to spin-on coating by a sol-gel method, spin-on from a metal organic solution, CVD method such as MOCVD, LSCVD (liquid source CVD), chemical vapor deposition (Chemical Vapor Dep
gas phase, RF-sputtering or CI
Physical methods such as B (Cluster Ion Beam) can be mentioned. Any material may be used as the material of the ferroelectric thin film as long as it has ferroelectric characteristics, but the polarization amount, coercive electric field, Fatigue
Not all materials can be used in terms of (fatigue breakdown), data-refection, memory characteristics, and MOS-process compatibility. Therefore, as a material that can be actually used, for example, PZT, its doping or loaded (partially substituted), Bi-based ferroelectric compound, B
An i-layered prevskite material is used. Since sufficient characteristics cannot be obtained by simply forming the ferroelectric thin film, it is preferable to use it after polycrystallizing after heat treatment at 500 to 900 ° C. in RTP (rapid thermal processing) or a heat treatment furnace.

In the present invention, it is conceivable that the upper or lower electrode of the ferroelectric capacitor and the emitter of either one of the two-terminal switches are connected by an external electrode. In this case, the material of the external electrode is, for example, an Al alloy. (Eg A
1Si, AlCuSi) and barrier metal (eg Ti,
Ta, TiW, TiW) combination, Pt and barrier metal (eg Ti, Ta, TiW, TiW) combination,
Pt and barrier metal (eg Ti, Ta, TiW, Ti
Examples of the combination include W) and those obtained by siliciding the Si surface (for example, PtSi, PdSi, MoSi, WSi).

In the present invention, a protective film may be formed on the substrate including the field oxide film. In this case, the material of the protective film is, for example, PSG or phosphorus in accordance with a normal semiconductor process. SiO _2, BPSG, boron and phosphorus-containing _{SiO 2, Si 3 N 4,} SiO 2, TE
OS-SiO ₂ or the like is used, but spin-coated SiO ₂ (SOG or OCD) may be used.

[0021]

According to the present invention, the semiconductor element is composed of a pnp-type lateral transistor and an npn-type vertical transistor, and the base portion of the lateral transistor is shared with the collector portion of the vertical transistor. By making the collector part of the lateral transistor common with the base part of the vertical transistor, ultra-high integration can be realized without deterioration of remanent polarization.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.
It Example 1 Reference is made to FIG. 31 in the figure is p-type Si
The board is shown. The surface of the substrate 31 is formed by the LOCOS method.
The field oxide film 32 is formed. This feel
In the island region of the substrate 31 surrounded by the oxide film 32, an n-type wafer is formed.
Area 33 is formed. Here, in the n-well region 33
Concentration is 10¹⁶-10¹⁸cm^-3And the depth is 0.5-2 μm
Is. In the n well region 33, p⁺ Type diffusion layers 34, 35
Are formed separately from each other. Where p⁺ Mold half
The surface concentration of the conductor layers 34 and 35 is 10¹⁸-10¹⁹cm^-3And the depth
Is 0.3 to 0.5 μm. One p⁺ Type semiconductor layer 34
Has n⁺ A mold emitter region 36 is formed. here
Then, the emitter region 36 is formed of, for example, As as a dopant.
Is formed with a depth of 0.1 to 0.4 μm,
Area density is 10¹⁹-10^{twenty one}cm^-3Is. The field acid
In the region of the substrate 31 below the oxide film 32, p⁺ Type channel stopper
A region 37 is formed.

A protective film 38 is formed on the field oxide film 32 including the island region of the substrate 31, and the p ⁺ Type diffusion layer 34,
n ⁺ The protective films 38 corresponding to the mold emitter regions 36 are opened. PSG was used as the material of the protective film 38. A base electrode 39, a ferroelectric thin film 40, and an upper electrode 41 are respectively formed on a part of the protective film 38 with an adhesive layer (not shown) therebetween to form a ferroelectric capacitor. PZT was used as the material of the ferroelectric thin film 40. This PZT has a polarization amount of about 30 μC / cm ² , Coercive electric field is about 50
KV / cm, dielectric constant 500-1000, fatigue fracture 200
10 ⁹ at an electric field of KV / cm The polarization amount is halved with each turn. Also, B
If i-layered prevskite material is used, the polarization amount is about 10 μC / cm ² , Coercive electric field is about 40KV / cm, dielectric constant is 2
0 to 400, fatigue failure is 10 ^{12 in} an electric field of 200 KV / cm
There is no change up to the time. The data retention is 10 years or more after leaving it at 100 ° C. The ferroelectric thin film 40
The upper electrode 41 is shorter than the base electrode 39. Where n ⁺ Type emitter region 36, p ⁺ A vertical npn transistor is constituted by the type diffusion layer (base) 35 and the n well region 33, and the p + type diffusion layer (emitter) 34, the n well region (base) 33 and the p + type diffusion layer (collector) 35. A lateral pnp transistor is configured.

The upper electrode 41, the base electrode 39 and the protective film 38
A passivation film 42 is formed on the top. Here, as the material of the passivation film 42, for example, SOG, PSG, BPSG, P-CVD film (plasma-
CVD film), Si ₃ N ₄ , and Al ₂ O ₃ . P ⁺ Type diffusion layer 34, n ⁺ Type emitter region 36, base electrode 39
And the passivation film corresponding to the upper electrode 41, respectively.
42 is opened, and p ^{+ is} added to this opened portion. The first extraction electrode 43 connected to the mold diffusion layer 34, the second extraction electrode 43 connected to the base electrode 39
An extraction electrode 44 and a third extraction electrode 45 connected to the upper electrode 41 are formed. Here, the third extraction electrode 45 is
Characteristics of ferroelectric thin film 40 and p used as electrode of 2-terminal switch
⁺ Type diffusion layer 34, n ⁺ It is necessary to simultaneously fill the ohmic contacts of the die emitter region 36, and the material of the extraction electrode 45 is an Al alloy (for example, AlSi, AlCuS).
i) was used.

An outline of the method of manufacturing the ferroelectric memory of FIG. 6 is as follows. (1) First, after forming the field oxide film 32 on the surface of the p-type Si substrate 31 by the LOCOS method, the n well region 33 is formed in the element region surrounded by the field oxide film 32,
P ^{+ in} other areas A mold channel stopper region 37 is formed. Then, p ⁺ is formed on the surface of the n-well region 33 by a well-known technique. The type semiconductor layers 34 and 35 are formed separately from each other. Furthermore, p ⁺ N ^{+ on} the surface of the semiconductor layer 35 A mold emitter region 36 is formed.

(2) Next, a protective film made of SiO _{2 on} the entire surface
Form 38. Subsequently, after forming a base electrode material, a ferroelectric thin film material, and an upper electrode material (not shown), RIE (Reacting) is performed using ordinary photolithography.
Ion Etching) or an ion mill is used to form a ferroelectric capacitor composed of a base electrode 39, a ferroelectric thin film 40 made of PZT and an upper electrode 41 on a part of the protective film 38. Here, the deposition of the base electrode material layer is D
C-magnetron sputtering is used. Further, in forming the ferroelectric thin film 40, spin-on coating by a sol-gel method is used.

(3) Next, after forming the passivation film 42 on the entire surface, the p ⁺ Type semiconductor layer 34, n ⁺ The passivation film 42 and the protective film 32 corresponding to the mold emitter region 36 are selectively opened, and the upper electrode 41 and the lower electrode 39 are formed.
And a first extraction electrode 43, a second extraction electrode 44, and a third extraction electrode 44 are formed in these openings to form a semiconductor device having a two-terminal switch structure and a ferroelectric capacitor. Manufactures ferroelectric memory.

As described above, in the matrix type ferroelectric memory according to the first embodiment, the n well region 3 is formed on the p type Si substrate 31.
2, p ⁺ Type diffusion layers 34, 35 and n ⁺ A type emitter region 36 is formed to form a semiconductor device having a two-terminal switch structure including a vertical npn transistor and a horizontal pnp transistor, and a protective film is formed on the field oxide film 32 on the surface of the substrate 21.
Base electrode 39, ferroelectric thin film 40 and upper electrode 40 via 38
A ferroelectric capacitor composed of is connected in series to the semiconductor element, and further, an upper electrode 40 and an emitter region.
36 is connected by the third extraction electrode 45.
However, in the case of Example 1, the ferroelectric capacitor is Si
Since the structure is formed on the protective film 38 made of O ₂ , the capacitor has an advantage of having extremely stable characteristics.

(Embodiment 2) Referring to FIG. However, FIG.
The same members as and are denoted by the same reference numerals, and description thereof will be omitted. In the second embodiment, the base electrode 39, which is a structure of the capacitor, is n ⁺ through the barrier layer 51. It is connected to the mold diffusion layer 36. In addition,
n ⁺ Instead of the type diffusion layer 36, it may be connected to the p + type diffusion layer 34. However, the barrier layer 51 is n ⁺ While maintaining ohmic contact with the type diffusion layer 36, the alloying reaction with the base electrode 39 and the base electrode 39 are diffused between the barrier layers 51, n ⁺
It must not have the property of reaching the mold diffusion layer 36. That is, it must be the function of the diffusion prevention layer.
By the way, the barrier layer 51 is determined by the formation temperature of the ferroelectric substance and the heat resistance temperature of the electrode. For example, in the case of PZT (also in the case of PbTiO, PLZT), the formation temperature is 5
Since it is 00 to 650 ° C., Ta, TiN, or TiW can be used, for example. However, higher temperature (650-750 ° C)
For Bi layered perovskites that require
To use.

According to the second embodiment, the base electrode 39, which is a structure of the ferroelectric capacitor, is n ⁺ Since it is mounted on the contact region of the type diffusion layer 36 via the barrier layer 51, the area occupied by the semiconductor element and the ferroelectric capacitor having the two-terminal switch structure can be reduced as compared with the first embodiment. The degree of integration can be improved. Further, due to the existence of the barrier layer 51, the base electrode 39 and n ⁺ The alloying reaction with the type diffusion layer 36 can be avoided, and the component of the base electrode 39 is n ⁺ It is possible to avoid diffusion toward the mold diffusion layer 36.

(Embodiment 3) Referring to FIG. The third embodiment, the n-well region in FIG. 6 and FIG. 7 N ⁺ BL (n
⁺ In this example, it is replaced with a mold embedding layer) 61. When the n-type buried layer 61 is driven at a high speed in the hysteresis of FIG. 2 which greatly reduces the series resistance, the rise after V + Vth is mainly determined by the series resistance of the pnpn2 terminal switch. Therefore, n ⁺ The ON resistance was reduced by the mold burying layer 61. The ρ _s (sheet resistance) of the n-type buried layer 61 is 20 to 60Ω, and the ON resistance is 40 to 20.
Lower to 0Ω.

(Embodiment 4) In Embodiment 4, as shown in FIG. 9, the n-type buried layer 61 and the p ⁺ p ^{+ of} npn type transistor This is an example in which the mold diffusion layer (base) 35 is brought into contact.
As described above, the Vth (threshold voltage) of this pnpn switch is as low as around 2V. Therefore, npn
The base region of the type transistor needs to have a low concentration and a small width.

(Embodiment 5) In Embodiment 5, as shown in FIG. 10, a polycrystalline silicon layer 62 is connected to the emitter region 36 of an npn-type transistor. In addition,
In FIG. 10, 63 and 64 are the first formed by oxidation, respectively.
The second passivation film and the second passivation film are shown. For example, PSG and BPSG are used as the material.
The method of forming these films can be the same as that of the passivation film described in the first embodiment.

(Embodiment 6) In Embodiment 6, as shown in FIG. 11, a polycrystalline silicon layer 62 is used in the emitter region 36 of an npn-type transistor, and one side of the emitter region 36 is an oxide film formed by the LOCOS method. Positioned by 65. According to the sixth embodiment, the emitter region 36 can be positioned in a self-aligned manner, and the device area can be further reduced.

(Embodiment 7) In Embodiment 7, as shown in FIG. 12, an n ⁺ -type n ⁺ -type transistor is used. Mold emitter region 36
And p ^{+ of} pnp type transistor The type diffusion layer (emitter region) 34 is simultaneously positioned by the oxide film 62 formed by the LOCOS oxidation method, and the area is further reduced.

[0036] (Example 8) In this eighth embodiment, as shown in FIG. 13, of the pnp transistor p ⁺ Only the type diffusion layer (emitter region) 34 is positioned by an oxide film 66 formed by the LOCOS method.

(Embodiment 9) In Embodiment 9, as shown in FIG. 14, a base region is formed by a gate oxide film of a CMOS transistor, a gate electrode 67 made of polycrystalline silicon, and an oxide film 68 made by oxidizing polycrystalline silicon. The emitter regions are aligned in the same way.

(Embodiment 10) In Embodiment 10, as shown in FIG. 15, a p ⁺ -type pnp transistor is used. Separate type diffusion layer (base) 34 n ⁺ The configuration is such that the area 69 is introduced.
Thus n ⁺ With the configuration in which the region 69 is introduced, the breakdown voltage can be controlled with higher accuracy.

(Embodiment 11) As shown in FIG. 16, this embodiment 11 is a p ⁺ type p ⁺ -type transistor. Separate type diffusion layer (base) 34 n ⁺ Introduce region 69 and further np
n-type transistor p ⁺ N ⁺ directly under the type diffusion layer (base region) 35 The configuration is such that a mold dummy region 70 is provided. With such a configuration, the breakdown voltage can be controlled with higher accuracy and the CE breakdown voltage (collector-emitter breakdown voltage) of the npn-type transistor can be lowered.

(Embodiment 12) Reference is made to FIGS. 17 (A) and 17 (B). Here, FIG. 17A is a layout configuration diagram when this memory cell is used, and FIG. 17B is XX of FIG. 17A.
A sectional view taken along the line is shown. The basic structure of the memory cell of the twelfth embodiment is the same as that of FIG. Although the X lines 71a and 71b use diffusion layers, metal lines may be used to reduce the resistance. 72a, 72b, 72c in the figure
Is a Y line, and 73 is a contact (opening of the protective film 38 corresponding to the emitter region 36).

(Embodiment 13) FIGS. 18 (A) and 18 (B) are also layout examples, but in this case, FIG. 10 or FIG. 12 capable of higher integration is used as the memory process. in this case,
It was lined with metal to speed up the charging and discharging time of the X-line. Reference numeral 75 in the figure denotes a back contact hole made of metal.

(Embodiment 14) In FIGS. 19A and 19B, ferroelectric capacitors (39, 40, 41) are formed on a LOCOS oxide film 32 and connected in series with a third electrode 45. It was done. Here, the X-line 43 uses wiring for the purpose of lowering the resistance.

Example 15 FIGS. 20A to 20C and FIG.
Refer to. In FIG. 21, 81 is n ⁺ Type sauce (S)
Region, 82 is n ⁺ The drain (D) region of the mold is shown. In the fifteenth embodiment, an example using a MOS type two-terminal switch is shown. As shown in FIG. 20 (A), the gate part is used by floating or grounding the source. Vth (threshold voltage) is BV _SDO or BV _SDS . This Vth is 2
In order to achieve 3 V, the P well region (10
^{14 ~10 16} cm ^-3) and a short channel (0.2～1.5Myu
m) MOS. NMOS is preferred.

(Example 16) Reference is made to FIGS. 22 (A) to 22 (C). In the sixteenth embodiment, a MOS type two-terminal switch in which conductivity modulation is caused by carrier injection is used. In this case, the gate oxide film of the MOS transistor is an extremely thin (5 to 50 nm) oxide film, Si ₃ N ₄ film or laminated film. As shown in FIG. _22C , once the breakdown occurs beyond the BV _SDO voltage, carriers (hot carriers in this case) are injected. This modulates the conductivity I _DS . Since the gate is floating, current flows even when the voltage is V _th or less. Its structure is shown in Figure 21.
Is the same as.

(Embodiment 17) FIGS. 23 (A), 23 (C) and 23 (D)
And FIG. 31. The seventeenth embodiment is an example using a two-terminal switch of a bipolar transistor. In this case, the base region of the npn-type or pnp-type transistor is used by being grounded to the emitter region. Where Vth is BV
_CES withstand voltage. In this case, the ON resistance is small, but the voltage is not ideal because the BV _CED breakdown voltage remains. But,
As shown in FIG. 31, the structure is extremely simple. That is, n
⁺ The buried layer 61 is striped to the X-line, a hole is formed in the field oxide film 38 leaving an active region, and then p ⁺
The ion diffusion of the mold diffusion layer (base region) 35 and the ion implantation of the emitter region 36 are performed, and the barrier layer 51 is formed thereon.
To make a ferroelectric capacitor. Of course, the lower electrode may be omitted.

[0046]

As described above in detail, according to the present invention,
Matrix-type ferroelectrics that can be highly integrated and have various advantages such as forming a ferroelectric capacitor on a protective film to obtain stable characteristics, forming an emitter region in a self-aligned manner, and controlling the breakdown voltage. Can provide memory.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a matrix type ferroelectric memory according to the present invention, FIG. 1 (A) is a characteristic diagram showing a relationship with voltage-polarization amount, and FIG. 1 (B) is a relationship with voltage-current. FIG. 1C is a characteristic diagram showing the relationship between voltage and charge amount.

FIG. 2 is a hysteresis characteristic diagram when a pnpn two-terminal switch and a ferroelectric capacitor are combined.

3A and 3B are explanatory diagrams of a device using a pnpn type two-terminal switch, FIG. 3A is an equivalent circuit, and FIG. 3B is a current-voltage characteristic diagram.

FIG. 4 is a sectional view showing an outline of a device in which a pnpn two-terminal switch and a ferroelectric capacitor are combined.

5 is a schematic circuit diagram of another device different from the device of FIG.

FIG. 6 is a sectional view of the matrix type ferroelectric memory according to the first embodiment of the present invention.

FIG. 7 is a sectional view of a matrix type ferroelectric memory according to a second embodiment of the present invention.

FIG. 8 is a sectional view of a main part of a matrix type ferroelectric memory according to a third embodiment of the present invention.

FIG. 9 is a sectional view of a main part of a matrix type ferroelectric memory according to a fourth embodiment of the present invention.

FIG. 10 is a sectional view of a main part of a matrix type ferroelectric memory according to a fifth embodiment of the present invention.

FIG. 11 is a sectional view of a main part of a matrix type ferroelectric memory according to a sixth embodiment of the present invention.

FIG. 12 is a sectional view of a main part of a matrix type ferroelectric memory according to a seventh embodiment of the present invention.

FIG. 13 is a sectional view of a main part of a matrix type ferroelectric memory according to Example 8 of the present invention.

FIG. 14 is a sectional view of an essential part of a matrix type ferroelectric memory according to Example 9 of the present invention.

FIG. 15 is a sectional view of an essential part of a matrix type ferroelectric memory according to Example 10 of the present invention.

FIG. 16 is a sectional view of an essential part of a matrix type ferroelectric memory according to an eleventh embodiment of the present invention.

FIG. 17 is an explanatory diagram of a matrix type ferroelectric memory according to Example 12 of the present invention, FIG. 17 (A) is a plan view, and FIG.
17B is a sectional view taken along the line XX of FIG.

FIG. 18 is an explanatory diagram of a matrix type ferroelectric memory according to a thirteenth embodiment of the present invention, FIG. 18 (A) is a plan view, and FIG. 18 (B) is a line XX of FIG. 18 (A). FIG.

FIG. 19 is an explanatory diagram of a matrix type ferroelectric memory according to Example 14 of the present invention, FIG. 19 (A) is a plan view, and FIG.
19B is a cross-sectional view taken along the line XX of FIG.

FIG. 20 is an explanatory diagram of a matrix type ferroelectric memory using a MOS type two-terminal switch according to Example 15 of the present invention, and FIG. 20 (A) shows a connection state of a transistor and a ferroelectric capacitor. Schematic circuit diagram, FIG. 20 (B) is a characteristic diagram showing the relationship between voltage and current between source and drain, FIG.
FIG. 6C is a characteristic diagram showing a relationship between voltage and charge amount.

FIG. 21 is a sectional view of a matrix type ferroelectric memory using a MOS type two-terminal switch according to Example 15 of the present invention.

22 is an explanatory diagram of a matrix type ferroelectric memory using a MOS type two-terminal switch in which conductivity modulation is caused by carrier injection according to Example 16 of the present invention, and FIG. 22 is a schematic circuit diagram showing the connection state of the ferroelectric capacitor, FIG. 22 (B) is a characteristic diagram showing the relationship between voltage and current between source and drain, FIG.
FIG. 6C is a characteristic diagram showing a relationship between voltage and charge amount.

FIG. 23 is an explanatory diagram of a matrix type ferroelectric memory using a bipoila type two-terminal switch according to a seventeenth embodiment of the present invention, and FIGS. 23 (A) and (B) are connections between a transistor and a ferroelectric capacitor. Circuit diagram showing the situation of Fig. 23
23C is a characteristic diagram showing the relationship between the voltage and the current between the source and drain, and FIG. 23D is a characteristic diagram showing the relationship between the voltage and the charge amount.

FIG. 24 is a hysteresis characteristic diagram showing a voltage-polarization amount relationship related to a ferroelectric material.

FIG. 25 is a schematic perspective view of a ferroelectric thin film having a simple matrix structure.

FIG. 26 is an explanatory view of the ferroelectric thin film of FIG.
FIG. 26A is a characteristic diagram showing the relationship between the number of disturbance pulses and remanent polarization at various write voltages, and FIG. 26B is a waveform diagram of the write pulse, the disturbance pulse and the read pulse.

FIG. 27 is an ideal hysteresis characteristic diagram showing a voltage-polarization amount relationship related to a ferroelectric material.

FIG. 28 is an explanatory diagram of a simulation for observing the effect of a two-terminal switch, FIG. 28 (A) uses a two-terminal switch and a ferroelectric capacitor, and FIG. 28 (B) shows a diode and a ferroelectric. Using capacity.

29 shows the simulation result of FIG. 28, and FIG.
(A) Two-terminal switch A type current modulation type, Fig. 29
(B) is a 2-terminal switch B type capacitance modulation type, FIG.
(C) is the case of only the ferroelectric material, and FIG. 29 (D) is the case of the serial model.

FIG. 30 is a schematic diagram of a pnpn-type two-terminal switch.

FIG. 31 is a cross-sectional view of a matrix type ferroelectric memory using a bipoiler type two-terminal switch according to a seventeenth embodiment of the present invention.

[Explanation of reference numerals] 31 ... p-type Si substrate, 32 ... field oxide film,
33 ... n well region, 34, 35 ... p ⁺ Type diffusion layer, 36 ... n ⁺
Type emitter region, 37 ... p ⁺ Mold channel stopper area,
38 ... Protective film, 39 ... Base electrode,
40 ... Ferroelectric thin film, 41 ... Upper electrode, 4
2, 63, 64 ... passivation film, 4
3 to 45 ... Extraction electrode, 61 ... n ⁺ Mold buried layer, 62 ... Polycrystalline silicon layer, 66, 68 ... Oxide film, 67 ... Gate electrode.

Claims (1)

[Claims] 1. A p-type base substrate, an n-type first semiconductor layer formed in an element region of the base substrate, and a p-type second semiconductor layer formed on the surface of the first semiconductor layer. A pnpn semiconductor type two-terminal switch formed of an n-type third semiconductor layer formed on the surface of the second semiconductor layer, and connected in series with the two-terminal switch via an insulating film on the base substrate. In a matrix type ferroelectric memory including the formed base electrode, a ferroelectric thin film, and a ferroelectric capacitor having an upper electrode, two p layers formed by separating the second semiconductor layer from each other.
A lateral region of a pnp type transistor, and a third semiconductor layer is provided only in one of the p type regions.
A matrix type ferroelectric memory characterized in that a pn type vertical transistor is formed.