JPH06244243A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a structure, wherein when LSIs are mounted on a substrate having a wiring layer, which is formed using a material different from the material for the substrate as an insulating material, on its surface, damage to connection members, such as pins or solder balls, is reduced even if the substrate is subjected to temperature change. CONSTITUTION:LISs 1 are mounted on a substrate 2 with a thin film wiring layer 3 or are directly mounted on a substrate 2 using solder balls or pins 4. Deformation matching layers 6 consisting of a material having a thermal expansion coefficient different from that of LSI chips are respectively formed on these LSIs 1. By the layers 6, a deformation due to warpage equal to that of the substrate is generated in the LSI chips even at the temperature at the time of normal temperatures subsequent to packaging of a semiconductor device or even at the temperature at the time when the device is working. As a result, damage to connection members, such as the solder balls, can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a semiconductor chip mounting structure, which is suitable for mounting a semiconductor chip having a high heat generation, and a method of manufacturing the same.

[0002]

2. Description of the Related Art To achieve a high speed computer, an LSI
Need to be mounted on the substrate in high density. An example of this is
IBM Journal of Research and Development Vol. 26, No. 1, p. 30 (IB
M J. Res. Development. Vol. 26,
No. 1, January 1982, P.30). Its structure is shown in FIG. In this figure, the substrate 2 is a ceramic multilayer substrate having a thick film wiring layer. Providing a thin film wiring layer 3 having a fine structure on this upper surface is more effective for high-density mounting. Such a structure is EE E 42nd Proceedings.
Electronic Component and Technology Conference Page 1 (IEEE Proce
edings of 42nd Electronic
Components & Technology
Conference, 1992, P.1). In this example, the LSI chip 1 has pads for solder ball connection on its surface, and the solder ball 4
A large number of I / O pins 99 are electrically connected to the entire surface of the chip via. An example of connecting an LSI on a substrate whose coefficient of thermal expansion is different from that of the LSI chip is a volume B (Vol.B) of the 70th Annual Meeting of the Japan Society of Mechanical Engineers.
It is disclosed on page 525.

[0003]

In the above conventional mounting structure, it is necessary to further increase the number of thin film wiring layers in order to achieve higher density in the future. In the thin film wiring layer, a metal material such as aluminum or copper is used for the wiring, and a material such as a polyimide resin having a different thermal expansion coefficient from the substrate is used for the insulating layer. The warp deformation of the substrate due to the temperature change increases. Also, L
The SI is cooled from the back surface of the chip, but the high heat generation of the LSI causes an increase in the temperature gradient in the chip thickness direction during the operation of the LSI, which causes warpage and deformation of the chip. Further, even when the semiconductor chip is connected to a substrate having a different coefficient of thermal expansion, warping deformation occurs due to the force from the connecting member acting on the chip connecting surface. These warp deformations cause a large amount of distortion in the pins for connecting the chips or the solder balls perpendicular to the connection surface, which causes a new problem that the reliability of the semiconductor devices is increased in recent years with the increase in speed.

An object of the present invention is to provide a semiconductor device which prevents damage to the solder balls and pins due to the warp deformation of the above-mentioned chip and substrate and enables high-density mounting.

[0005]

The above object is to provide a semiconductor device comprising a semiconductor element, a substrate on which the semiconductor element is mounted, and a connecting element for electrically connecting the semiconductor element and the substrate. This is achieved by a semiconductor device characterized in that a layer of a material having a thermal expansion coefficient different from that of the semiconductor element is formed on the surface of the element opposite to the surface facing the substrate.

[0006]

According to the above structure, the semiconductor element having the deformation matching layer made of a material having a different coefficient of thermal expansion bonded to the back surface of the semiconductor element undergoes warp deformation when subjected to a temperature change. This amount of deformation can be changed depending on the material characteristics and thickness of the deformation matching layer. Therefore, if the thickness of the deformation matching layer, the substrate or the thin film wiring layer is properly selected, the difference in thermal deformation between the element and the substrate due to temperature changes during solder joining or operation may cause damage to the solder balls, pins, etc. It is possible to keep below the allowable value.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a first embodiment,
The semiconductor chip 1 is mounted on the substrate 2 via a connecting member 4 such as a solder ball. This semiconductor chip is sealed by the cooling member 5 and the substrate 2. A cooling liquid 10 such as Fluorinert flows from an inlet 20 of the cooling member 5, is jetted from a nozzle 7 to cool the semiconductor chip 1, and then flows out from an outlet 21. On top of the substrate 2, a thin film wiring layer 3 having an organic material such as polyimide resin as an insulator is formed. In this substrate 2, the substrate material and the thin film wiring layer 3
Since they have different thermal expansion coefficients from each other, warp deformation occurs due to the temperature change during the LSI chip connection process and semiconductor operation. Therefore, in order to prevent damages to the connecting portions such as the pins or the solder balls 4 due to this deformation, a deformation matching layer 6 formed of a metal thin film having a coefficient of thermal expansion different from that of the chip is provided on the entire back surface of the semiconductor chip 1. ing. The deformation matching layer 6 does not necessarily have to be a metal film, but may be a sprayed film of ceramic or the like.

The operation of the deformation matching layer 6 will be described with reference to FIGS. FIG. 3 shows the warp deformation when the semiconductor chip, the semiconductor chip with the deformation matching layer and the substrate with the thin film layer respectively reach the connection process temperature, the room temperature and the temperature during semiconductor operation. The semiconductor chip 1 is mounted on the substrate 2 via pins or solder balls 4 or the like.
After joining at a temperature of 00 to 300 ° C., the temperature changes to −ΔT _{1 and} the temperature returns to room temperature (about 20 ° C.). After that, when the chip is energized and enters the operating state, the temperature of the semiconductor chip 1 rises by ΔT _{2 on} average. Normally, in this state, 50 to 8
Raise to 5 ° C. Further, the semiconductor chip 1 cools the heat generated on its operating surface from the back surface. A temperature gradient occurs in the semiconductor chip due to these two temperature changes.

In the case of the semiconductor chip 1 having no matching layer, the temperature change returning to room temperature after reaching the substrate bonding temperature-Δ
No warp deformation occurs at T ₁ . Further, although the warp deformation does not occur even if the temperature rises to the operating temperature ΔT ₂ , the warp deformation b occurs due to the temperature gradient in the semiconductor chip. On the other hand, the substrate 2 has the thin film wiring layer 3 on the upper surface thereof, and since the thin film wiring layer 3 is formed of materials having different thermal expansion coefficients, the warp deformation of −a ₂ per 1 ° C. temperature rise within the chip size range. Cause Due to this warp deformation, when the temperature changes to room temperature after chip joining, a deformation of a ₂ ΔT ₁ occurs. Further, when the semiconductor chip is in operation, the temperature of the substrate 2 is not the same as that of the chip, and the temperature of the substrate 2 rises by ΔT _{3 which has} a lower temperature difference than ΔT ₁ . In this case, the deformation of the substrate 2 at the operating temperature is a ₂ (ΔT ₁ −ΔT ₃ ) within the chip size range. Further, when the deformation matching layer 6 is provided on the semiconductor chip 1 so as to cause deformation of −a ₁ per 1 ° C. temperature rise,
The chip 1 has a ₁ ΔT ₁ and a ₁ at room temperature and operating temperature, respectively.
Warp deformation of ₁ (ΔT ₁ −ΔT ₂ ) + b occurs.

FIG. 4 shows the behavior of the semiconductor device when the above structure is used for the semiconductor device. If the substrate has a wiring layer and the chip has a deformation matching layer,
Due to the temperature change from the time of joining to room temperature, a ₁ Δ
At T ₁ , the substrate is deformed by a ₂ ΔT ₁ , and as a result, a deformation difference of (a ₁ −a ₂ ) ΔT ₁ (1) is generated. And, this _{is, a 1 (ΔT 1 -ΔT 2} ) in the chip during operation + b, a substrate with a ₂ (ΔT ₁ -Δ
T ₃ ) is deformed, and the difference is as follows. a ₁ (ΔT ₁ −ΔT ₂ ) + b−a ₂ (ΔT ₁ −ΔT ₃ ) ... (2) The connecting member causes strain and stress to connect the chip and the substrate that cause these deformation differences. Therefore, the strength reliability of the connection portion can be enhanced by sufficiently reducing the difference in deformation.

As shown in FIG. 5, the diagonal length of the chip is d. Further, the thickness, Young's modulus, and coefficient of thermal expansion are represented by h, E, and α, respectively, and these amounts for the deformation matching layer, the semiconductor chip, the thin film wiring layer, and the substrate are respectively subscripted 1, 2, 3, and 4. It is indicated by adding. The heat generation amount per unit area of the chip is represented by q, and the thermal conductivity is represented by λ. At this time,
The above-mentioned a ₁ , a ₂ and b are generally represented as follows.

A ₁ = (3/4) d ² × (α ₁ −α ₂ ) × E ₁ h ₁ / (E ₂ h ₂ ² ) ... (3) a ₂ = (3/4) d ² × (Α ₃ −α ₄ ) × E ₃ h ₃ / (E ₄ h ₄ ² ) (4) b = d ² × α ₂ × q / (8λ) (5)

[0013]

[Table 1]

As an example of the temperature change actually received by the semiconductor device, the thermal expansion coefficient, Young's modulus,
The thickness is determined and the above equations (1) to (3) are calculated. Here, the chip connection structure is the structure shown in FIG. 5, the chip diagonal length d = 20 mm, the heat generation amount per unit area of the chip q = 1 w / mm ² , the thermal conductivity λ = 0.14 w / mm. C, temperature difference ΔT ₁ = 180 ° C., ΔT ₂ = 60 ° C., ΔT ₃ = 30 ° C. As a result, b≈1.1 μm was obtained.

In this case, in order to make both the deformation differences of the above (1) and (2) 0, h ₁ , h ₃ , and a ₁ = a ₂ = b / (ΔT ₂ −ΔT ₃ ) You can choose h ₄ . For example, when the deformation matching layer is made of Ni, h ₁ is about 2.2 μ from the above.
When formed with m 2 and Cr, the thickness is about 4.5 μm. Also, if h ₄ remains 3 mm, h ₃ will be 0.64 mm
The film may be formed so that

However, in practice, it is not necessary to make the deformation difference zero, and it is sufficient if it is not more than the allowable value determined by the bonding strength.
In order to prevent the creep rupture of the solder, it is sufficient to prevent the stress from continuously acting on the solder. For this purpose, it is sufficient if the solder does not yield when the temperature returns to room temperature after stress relaxation due to creep at high temperature during operation, and the strain perpendicular to the connection surface caused by the temperature difference between the operation temperature and room temperature is generated. Should be 0.2% or less. When a chip having a thickness of 0.5 mm is connected with a solder ball having a cross-sectional area density of about 20%, the strain due to the deformation difference δ is about (20 / d) ² δ. Here, δ is a deformation difference (mm), and d is a chip diagonal length. The allowable value δ _al for the deformation difference in this case is approximately as follows. _{^{δ al = 5.0d 2/10 6}} (mm) The value is inversely proportional to the square of the chip thickness, _al [delta] proportional to the cross-sectional area density of the solder joint is as follows. At this time, the allowable value δ _al from the strength to the deformation difference is approximately as follows. ^{_{δ al = 5.0d 2 (κ /}} 0.2) (0.5 / t) 2/10 6 (mm) = 6.25 where ^{(d / t) 2 κ /} 10 6 (mm), d is The chip diagonal length, t is the chip thickness, and κ is the connection solder cross-sectional area density.

In the case of FIG. 5, the connection solder cross-sectional area density is 0.1.
Then, δ _al becomes 1 μm. When the substrate is constructed with the necessary minimum thickness shown in Table 1, 5 μm is deformed by ΔT _1, so h _{4 is set} to 5 mm. In this case, the deformation due to ΔT ₁ is 1.8 μm. 0.8 for Ni and Cr
When a deformation matching layer of μm and 1.6 μm is formed, the deformation difference becomes almost 0 at room temperature and becomes 0.7 μm during operation, which is within the allowable range.

Next, in FIG. 4, there is a wiring layer on the substrate,
If the chip does not have a matching layer, the substrate is deformed by aΔT ₁ even though the chip is not deformed at room temperature, and the connecting member is damaged. When the chip is in operation, the chip is deformed by b, and the substrate is deformed by a (ΔT ₁ −ΔT ₃ ), so the load on the connection portion is reduced, but the temperature is returned to room temperature when stopped, and the load at room temperature and during operation is repeated. In the case where the chip has no matching layer and the substrate has no wiring layer, no load is generated at room temperature, but during operation, only the chip is deformed and a load is generated. When the heat value of the chip is small, b is small and no serious damage is caused, but when the heat value of the chip is large, damage is caused. If the substrate has no wiring layer and the chip has a matching layer, damage will occur both at room temperature and during operation. Such a structure can provide a structure with higher reliability than other structures when the substrate thin film wiring layer is thick or the chip heat generation amount is large.

The structure as described above is not limited to the case of the solder ball, but as shown in FIG. 6, the metal between the LSI chip 1 on which the deformation matching layer 6 is formed and the thin film wiring layer 3 of the substrate 2 is formed. It is also applicable when connecting the balls 11 or the pins with the solder 12.

FIG. 7 is a diagram showing a second embodiment of the present invention. In FIG. 7, the deformation matching layer is partially provided, not on the entire surface of the chip. This partial deformation matching layer can also play the same role as in the first embodiment. And
This is effective when the metal film is not attached to the cut point, because it prevents the metal powder from scattering when cutting the chip. In FIG. 7, in order to make the amount of deformation of the substrate appropriate, instead of changing the thickness of the substrate, a deformation matching layer is formed on the back surface of the substrate. Further, although the deformation matching layer 6 is partially continuous in FIG. 7, the same effect can be obtained even if the deformation matching layer 6 is divided into a plurality of parts.

FIG. 8 is a diagram showing a third embodiment of the present invention. In this example, the chips are not in direct contact with the coolant. Then, through the heat conductive compound 13,
It is cooled by the refrigerant flowing in the flow path 22 provided in the cooling member 5. Since the thermal conductive compound 13 has a small deformation resistance, by providing a deformation matching layer on the chip,
The load of connecting solder can be reduced. As this heat conductive compound, grease containing zinc oxide is known.

FIG. 9 is a diagram showing a fourth embodiment of the present invention. In the above-described embodiments, the deformation matching layer is sufficiently thinner than the chip thickness, but even if the deformation matching layer corresponds to the chip thickness, the same effect as described above can be obtained. In FIG. 9, the deformation matching layer 6 is 0.2 from the coefficient of thermal expansion of the chip.
It is made of aluminum nitride that is as large as × 10 ~ ⁶ / ℃.
It has a thickness of 0 mm. This aluminum nitride plate is bonded to the chip with a heat conductive adhesive 14 such as solder. Thus, the deformation amount a per 1 ° C. when the deformation matching layer is thick
₁ is represented by the following equation (6), which is more strict than the above equation (3). That is, ignoring the influence of the heat conductive adhesive 14,
Using the symbols shown in, the amount of deformation is as follows.

A ₁ = (3/4) × h ₂ × d ² × (α ₁ −α ₂ ) × (1 + m) / {3 (1 + m) ² + (1 + mn) × (m ² + 1 / (m
n))} (6) where m = h ₁ / h ₂ and n = E ₁
/ E ₂ .

The Young's modulus of aluminum nitride is about 2.8 × 10 ⁵ M
Since it is Pa, if the deformation matching layer with the above dimensions is used, ΔT
Similar to the first embodiment by ₁ temperature change can be suppressed to a thermal deformation of 1.8 .mu.m. In this variant matching layer thermal expansion coefficient difference between the chip other than aluminum nitride 1 × 10 ~ ⁶ /
Any material may be used if the temperature is not higher than 0 ° C, but it is preferable that the material is as thin as possible so as not to impair the cooling performance, and the difference in coefficient of thermal expansion is preferably 0.5 × 10 ⁶ / ° C or less.

FIG. 10 is a diagram showing a fifth embodiment of the present invention. In FIG. 10, the chip is connected on a substrate having no thin film wiring layer. The cross-sectional density κ of this connection solder is 0.05
If so, d = 20 mm, and if t = 0.5 mm, δ _al becomes 0.5 μm. On the other hand, if the amount of heat generated per unit area of the chip is q = 1 w / mm ² and the thermal conductivity λ is 0.14 w / mm · ° C, the warp deformation due to the temperature distribution during operation is b ≈ 1.1 μm and δ _al Exceed. Therefore, Ni or Cr on the chip
If the respective deformation matching layers of 1.0 and 2.0 μm are made, a deformation of 0.75 μm occurs at a temperature rise of 60 ° C. during operation, and the deformation difference becomes 0.35 μm, which can be δ _al or less. In this case, a deformation difference of δ _al or more occurs due to the temperature change from the time of chip connection to normal temperature, but this temperature change is small in number,
There is little risk of breakage. In order for the deformation matching layer to fulfill such a role, the deformation due to the temperature rise of 60 ° C. during operation is δ _al.
Is preferably 25% or more.

FIG. 11 is a diagram showing a sixth embodiment of the present invention. In FIG. 11, the chip 6 is placed on a substrate 8 made of alumina, epoxy, polyimide or the like having a different coefficient of thermal expansion from that of the chip.
Are connected. When such a semiconductor device undergoes a temperature change, the substrate expands, which causes a shearing force to act on the bottom surface of the chip via the solder connection portion, causing warpage and deformation of the chip. As a result, the shape shown by the broken line at room temperature as shown in FIG. 12 is deformed as shown by the solid line when the temperature rises during operation and the stress perpendicular to the solder connection interface is generated. Also in this case, the warp deformation can be reduced by the deformation matching layer. According to the calculation result of the finite element method, the vertical strain of the solder joint of this structure due to the temperature change of 60 ° C. is as follows.

Ε _z ≈400 dκ Δα where Δα is the difference in thermal expansion coefficient between the chip and the substrate. For example, d = 20, κ
= 0.2 and Δα = 2/10 ⁶ , ε _z = 0.0032 As described above, since ε _z needs to be 0.002 or less, the deformation matching layer of the chip has ε of 0.0012 or more. need to yield _z . For this purpose, it is necessary to generate deformation of 1.2 μm or more, so the Ni or Cr deformation matching layer is 1.
6 μm and 3.2 μm are required.

FIG. 13 is a diagram showing a seventh embodiment of the present invention. A chip 1 is connected on a substrate 8 having a different coefficient of thermal expansion from the chip, and a deformation matching layer made of a metal foil 15 joined by a solder 14 is provided on the chip.

FIG. 14 is a diagram showing an eighth embodiment of the present invention. The chip is connected on the substrate 8 having a different coefficient of thermal expansion from the chip, and the resin 16 is bonded on the chip as a deformation matching layer.

[0030]

According to the present invention, in a semiconductor device,
When an LSI chip is mounted on a substrate or a substrate having a different thermal expansion coefficient from that of the chip, the warping deformation of the substrate caused by a temperature change acts so that the deformation matching layer cancels the warpage, and a connecting member such as a solder ball. Since the deformation stress of is relaxed, a highly reliable mounting structure can be obtained.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view of a first embodiment of the present invention.

FIG. 2 is a vertical sectional view of a conventional example.

FIG. 3 is an explanatory diagram showing a role of a deformation matching layer.

FIG. 4 is an explanatory diagram showing a role of a deformation matching layer.

FIG. 5 is an explanatory diagram showing a role of a deformation matching layer.

FIG. 6 is a vertical cross-sectional view of a modified example of the connection structure according to the first embodiment.

FIG. 7 is a vertical sectional view of a second embodiment of the present invention.

FIG. 8 is a vertical sectional view of a third embodiment of the present invention.

FIG. 9 is a vertical sectional view of a fourth embodiment of the present invention.

FIG. 10 is a vertical sectional view of a fifth embodiment of the present invention.

FIG. 11 is a vertical sectional view of a sixth embodiment of the present invention.

FIG. 12 is an explanatory diagram of a strain generation mechanism when the chip and the substrate have different thermal expansion coefficients.

FIG. 13 is a vertical sectional view of a seventh embodiment of the present invention.

FIG. 14 is a vertical sectional view of an eighth embodiment of the present invention.

[Explanation of symbols]

 1 LSI Chip 2 Substrate 3 Thin Film Wiring Layer 4 Solder Ball 5 Cooling Member 6 Deformation Matching Layer 7 Nozzle 8 Substrate with Different Coefficient of Thermal Expansion from Chip 10 Fluorinert 11 Metal Ball or Pin 12 Solder 13 Thermal Conductive Compound 14 Solder 15 Metal Foil 16 Deformation Matching Layer 20 Made of Resin 20 Refrigerant Inlet 21 Refrigerant Outlet 23 Refrigerant Flow Path 99 Pin

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroaki Doi, 502 Kintatemachi, Tsuchiura City, Ibaraki Prefecture Hiritsu Seisakusho Co., Ltd.

Claims (14)

[Claims] 1. A heating semiconductor element, a substrate on which the heating semiconductor element is mounted, a wiring layer formed on the surface of the substrate and made of a material different from that of the substrate as an insulator, and the heating semiconductor element and the substrate are electrically connected to each other. In a semiconductor device including a connecting element that electrically connects, a layer of a material having a coefficient of thermal expansion different from that of the heating semiconductor element is provided on a surface of the heating semiconductor element opposite to the surface facing the substrate. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the layer of a material having a thermal expansion coefficient different from that of the heat-generating semiconductor element is a thin film formed by plating, sputtering, thermal spraying or the like. 3. The connecting element is arranged between the heat generating semiconductor element and the substrate, the diagonal length of the heat generating semiconductor element is d (mm), the chip thickness is t (mm), and the solder connection is broken. When the area density is κ, the thermal deformation difference δ (mm) between the heat generating semiconductor element and the substrate is the deformation limit δ expressed by the following equation.
_{For al} (mm), δ _al == 6.25 (d / t) ² κ / 10 ⁶ , and δ ≦ δ _al . The semiconductor device according to claim 1, wherein a thickness is formed. 4. The layer of a material having a coefficient of thermal expansion different from that of the heat-generating semiconductor element is formed of Cr, Ni, or an alloy thereof. Semiconductor device. 5. A heat-generating semiconductor element, a substrate on which the heat-generating semiconductor element is mounted, a wiring layer formed on the surface of the substrate and made of a material different from the substrate as an insulator, and the heat-generating semiconductor element and the substrate are electrically connected to each other. In a method of manufacturing a semiconductor device including a connection element that is electrically connected, a layer of a material having a coefficient of thermal expansion different from that of the heat-generating semiconductor element is formed on a surface of the heat-generating semiconductor element opposite to the surface facing the substrate. A method of manufacturing a semiconductor device, characterized in that the heating semiconductor element and the substrate are electrically connected later. 6. An LSI chip having a solder ball or pin connection end portion, wherein a layer of a material having a thermal expansion coefficient different from that of the LSI chip is formed on a surface opposite to a surface including the connection end portion. Characteristic LSI chip. 7. The LSI chip has a diagonal length d
(Mm), the thickness t (mm), when the modified [delta] and (mm) in the temperature change of 60 ℃, δ> 0.4 (d / t) at ^{2/10 6,} the LSI chip 7. The LSI chip according to claim 6, wherein a thickness of a layer of a material having a different thermal expansion coefficient is formed. 8. The LSI chip according to claim 6, wherein a layer of a material having a coefficient of thermal expansion different from that of the LSI chip covers a central portion of the surface of the LSI chip. 9. A semiconductor device comprising a semiconductor element, a substrate on which the semiconductor element is mounted, and a connection element electrically connecting the semiconductor element and the substrate, wherein a surface of the semiconductor element facing the substrate. A semiconductor device having a layer of a material having a thermal expansion coefficient different from that of the semiconductor element formed on the surface opposite to the above. 10. The semiconductor device according to claim 9, wherein the connection element comprises a solder ball or a pin. 11. The semiconductor device has a diagonal length d
(Mm), the thickness is t (mm), and the deformation is δ (mm) at a temperature change of 60 ° C., so that δ> 0.4 (d / t) ² κ / 10 ⁶ The semiconductor device according to claim 9, wherein a thickness of a layer of a material having a coefficient of thermal expansion different from that of the element is formed. 12. The semiconductor device according to claim 9, wherein the layer of a material having a thermal expansion coefficient different from that of the semiconductor element is formed of Cr, Ni, or an alloy thereof. 13. The semiconductor device according to claim 9, wherein the layer of the material having a thermal expansion coefficient different from that of the semiconductor element is formed of a metal foil joined by solder. 14. The semiconductor device according to claim 9, wherein the layer of a material having a coefficient of thermal expansion different from that of the semiconductor element is formed of resin.