JPH06244070A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To adjust wafers safely with high precision by changing a structure in adhered wafers used as one of separation techniques of a semiconductor device. CONSTITUTION:On a main surface of a first wafer 8, specific patterns 8a, 8b, 8c are formed, and on the rear, reference patterns 10a, 10b, 10c are formed. On the main surface, an integral wafer adhered a second wafer 9 thereto is used, whereby it is possible to directly identify the reference patterns 10a, 10b, 10c from outside and adjust wafers with high precision. Also, the reference patterns 10a, 10b, 10c of the adhered wafer are used as reference to form newly reference patterns 12a, 12b, 12c on the second wafer 9, and a wafer is used in which the surface of the reference patterns of the first wafer 8 is ground, whereby it is possible to directly identify the reference patterns 12a, 12b, 12c from outside and adjust wafers with high precision.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer, and more particularly to a semiconductor wafer having a structure in which a predetermined pattern is incorporated.

[0002]

2. Description of the Related Art An example of a structure in which an oxide film is embedded inside a semiconductor wafer will be described with reference to FIG. In the figure, 1 is
The first semiconductor wafer 2 and the first and second semiconductor wafers showing the second semiconductor wafer are bonded to each other, and three concave portions 1 are formed on the bonding surface of one wafer 1.
a, 1b, 1c are formed. The recess 1a communicates with the outside through a narrow portion 1d formed between the other wafer 2 and the recesses 1b, 1c communicate with each other through the narrow portion 1e and communicate with the outside. This bonded semiconductor wafer 3 is exposed to an oxygen atmosphere to introduce oxygen from the narrow portions 1d, 1e into the wafer, and an oxide film 4 is formed in the recesses 1a, 1b, 1c as shown in FIG. afterwards,
By grinding and polishing up to the plane AA in the drawing, a region completely separated by the oxide film 4 is formed, and various semiconductor elements are formed on this polished surface. ("Selected SOI wafer using bonding technology""Electronicmaterials" 1992 August
Mon. See pages 51 to 55) With the above technique, it is very difficult to form an oxide film having various sizes and shapes in the wafer and to form a floating island-like oxide film in the wafer. Therefore, as a new technique, a silanol group is added to the bonding surface between a wafer on which an oxide film having various shapes is formed in advance and a normal flat wafer, and after drying, the wafer is brought into close contact with the wafer at a high temperature of 1100 ° C for 1 hr. Dehydration condensation by heat treatment,
A direct Si-Si bond is obtained through oxygen diffusion. Then, there is a method of aligning the wafer to which Si-Si is directly bonded. Conventionally, in order to form a pattern on the upper surface of the bonded wafer 3 in a state where the internal oxide film is not exposed, the internal oxide film 4 is formed by using the infrared alignment exposure device shown in FIG.
I am trying to align with. That is, the light from the lamp 5 is irradiated from the lower surface of the wafer 3, the mask 6 is arranged on the upper surface of the wafer 3, and the infrared image of the wafer 3 is photographed by the television camera 7 through the mask 6 and the oxide film inside the wafer 3 is photographed. The reference pattern such as 4 and the alignment pattern of the mask 6 are overlapped to position the element pattern.

[0003]

By the way, in the method of aligning with infrared rays, the bonded wafer 3 is used.
Is opaque, and since the oxide film 4 serving as a reference pattern is extremely thin, the contrast of the infrared image is low and it is difficult to position it with the mask 6 with high accuracy.

Therefore, it is possible to use a laser beam as a light source, but there is a problem that caution is required in terms of safety.

Further, it is necessary to use a high-resolution television camera that senses infrared rays, and processing is required to extract a reference pattern from a signal with low contrast.
There is also a problem that the equipment becomes expensive and the processing time becomes long.

[0006]

SUMMARY OF THE INVENTION The present invention has been proposed for the purpose of solving the above-mentioned problems, in which a predetermined pattern is formed on the main surface of a first wafer and a reference pattern is formed on the back surface. A semiconductor wafer having a second wafer bonded and integrated on the main surface.

[0007]

According to the present invention, the predetermined pattern cannot be identified because the predetermined pattern is formed inside the bonded wafer, but the reference pattern that serves as a reference for positioning can be directly identified from the outside, so that the positioning can be performed with high accuracy. be able to.

[0008]

Embodiment 1 An embodiment of the present invention will be described below with reference to FIGS. 1, 2 and 3. In the figure, reference numerals 8 and 9 denote first and second wafers, respectively. Predetermined patterns 8a, 8b and 8c made of, for example, an insulating film are formed on the main surface of the first wafer 8 and the positions of the prescribed patterns 8a, 8b and 8c are formed on the back surface. Is formed, the second wafer 9 is bonded to the main surface of the wafer 8 to form a bonded wafer 11. As a result, the reference pattern 10 is applied to the bonded wafer 11 described above.
The predetermined patterns 8a, 8b, 8c can be aligned with high precision on the wafer surface of the second wafer 9 based on a, 10b, 10c.

[0009]

Second Embodiment A second embodiment of the present invention will be described below with reference to FIGS. In the figure, the same symbols indicate the same parts. First, in FIG. 4, reference patterns 10a, 10b, 10c are formed so that the positions of the predetermined patterns 8a, 8b, 8c on the main surface of the first wafer 8 can be seen, and the second wafer 9 is formed on the main surface of the wafer 8. A bonded wafer 13 is formed by forming new reference patterns 12a, 12b, 12c on the second wafer 9 based on the reference patterns 10a, 10b, 10c of the bonded first wafer 8. Figure 5
At, the surfaces of the reference patterns 10 a, 10 b, 10 c of the first wafer 8 of the upper bonded wafer 13 are ground to form the bonded wafer 14. As a result, the reference pattern 12 is formed on the bonded wafer 14 described above.
The predetermined patterns 8a, 8b, 8c can be aligned with high precision on the ground wafer surface of the first wafer 8 based on a, 12b, 12c.

[0010]

As described above, according to the present invention, the reference pattern 10a of the first wafer 8 of the bonded wafer 11
Since 10b and 10c and the reference patterns 12a, 12b and 12c of the second wafer 9 of the bonded wafer 14 can be directly photographed, a high-contrast image can be obtained and positioning can be performed with high accuracy.

[Brief description of drawings]

FIG. 1 is a plan view of a bonded wafer showing a first embodiment of the present invention viewed from a side without a reference pattern.

FIG. 2 is a plan view of the bonded wafer according to the first embodiment of the present invention viewed from the side having a reference pattern.

FIG. 3 is a side sectional view of FIGS. 1 and 2.

FIG. 4 is a side sectional view of a bonded wafer in which a reference pattern is formed on the second wafer of the bonded wafer according to the second embodiment of the present invention.

5 is a side sectional view showing the state of the wafer in the next step of FIG.

FIG. 6 is a side sectional view showing a method for manufacturing a semiconductor wafer having a structure in which an oxide film is embedded.

FIG. 7 is a side sectional view showing the state of the wafer in the next step of FIG.

8 is a side sectional view showing a method for aligning the wafer shown in FIG.

[Explanation of symbols]

8 1st wafer 8a, 8b, 8c Predetermined pattern 9 2nd wafer 10a, 10b, 10c Reference pattern on 1st wafer 12a, 12b, 12c Reference pattern on 2nd wafer

Claims (4)

[Claims] 1. A predetermined pattern is formed on a main surface of a first wafer and a reference pattern is formed on a back surface, and a second wafer is bonded and integrated on the main surface. Semiconductor wafer. 2. A new reference pattern is formed on the second wafer of the semiconductor wafer according to claim 1 on the basis of the reference pattern of the first wafer, and the surface of the first wafer on which the reference pattern is present is formed. A semiconductor wafer characterized by being ground. 3. The semiconductor wafer according to claim 1, wherein the predetermined pattern is an insulating layer. 4. The semiconductor wafer according to claim 1, wherein the predetermined pattern constitutes a circuit element.