JPH06242946A - Branching controller - Google Patents

Abstract

PURPOSE:To perform a high-speed loop processing by judging conditions for an instruction to continue a loop in an early stage and letting a branching operation performed in a microprocessor provided with a decrement and branching instruction. CONSTITUTION:This controller is provided with a '1' detector 11 for detecting that a decrement result is '1', a timing latch 12 for holding the detected result, a 1-bit register 13 for holding the state of the timing latch 12 at the time of executing the decrement and branching instruction executed just before and an RS flip-flop 14 for indicating the invalid period of the 1-bit register 13. When the RS flip-flop 14 indicates the invalid period and the updating of counted operands is generated, the 1-bit register 13 is reset.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a branch controller for controlling instruction execution of branch instructions in a microprocessor, and more particularly to a decrement and
The present invention relates to a branch control device that controls a branch instruction.

[0002]

2. Description of the Related Art For processing by software using a microprocessor, the same processing is performed 1) until a specific condition is satisfied, 2) until a specific condition is no longer satisfied.
3) A flow that repeats a predetermined number of times is frequently used. In high-level languages such as FORTRAN and C, these flows are described by DO, WHILE, FOR statements and the like.

Of these flows, a process that is repeated a predetermined number of times is also called a loop process.
For example, it is used when performing binary multiplication processing. Binary multiplication processing includes 1) left shift of multiplicand, 2) left shift of partial product,
3) Check the fixed bit position of the shifted multiplicand,
4) 1-bit processing (in-loop processing) consisting of partial product and addition of multiplier based on the check result is repeated for the number of bits of the partial product. For example, in order to obtain a 16-bit product, 16 iterations (loops) are required.

In order to realize the loop processing by the machine instruction of the microprocessor, the resist or memory operand for storing the count value is defined as the count operand, and the necessary loop number is set immediately before the control is transferred to the loop processing. When the processing in the loop ends, the content of the count operand is decremented by 1 by the execution of the operation instruction (for example, the decrement operation instruction). Then, whether or not the value of the count operand is 0 is reflected in the flag register indicating the state of the microprocessor by executing an arithmetic instruction (for example, a logical arithmetic instruction).

Whether or not the operation result of the flag register indicates 0 is determined by a conditional branch instruction which branches depending on a specific bit state in the flag register. When it is determined that the count operand has become 0,
The conditional branch instruction does not take and ends the loop processing.

On the other hand, if it is determined that the count operand is not 0, the conditional branch instruction is taken and control is transferred to the beginning of the in-loop processing. As described above, the flow processing in which the in-loop processing is repeated the number of times of the loop initially set in the count operand is realized.

If the number of loops is a variable (especially when 0 can be specified), it is judged whether the specified count operand is 0 before the control is transferred to the loop processing. It is necessary to skip the loop processing.

In order to control the flow of the loop processing as described above, 1) update of the count operand, 2) checking of the updated count operand, and 3) continuation of the processing within the loop every time the processing in the loop is executed. Each machine instruction must be executed to process the branch for. Depending on the microprocessor, each of the processes 1) to 3) may be realized by one machine instruction or may be realized by a plurality of instructions.

The above loop processing control becomes an overhead for the essential processing of the in-loop processing. Moreover, since this overhead is accumulated by the number of loops, the performance of the loop processing control greatly affects the performance of the entire loop processing. Therefore, a microprocessor having a dedicated machine instruction for performing loop processing control at high speed is known.

16-bit Intel
The microprocessor i8086 has a machine instruction JCXNZ instruction for processing the above-mentioned loop control with one instruction. This JCXNZ instruction has a branch destination operand,
The count operand is one of the general-purpose registers, 16
It is assumed that the bit register CX is used implicitly. When the JCXNZ instruction is executed, the contents of the CX register are decremented by 1 and the result is 0.
Otherwise, control is transferred to the address specified by the branch destination operand.

On the other hand, when it is determined that the decrement result of the CX register is 0, the control is transferred to the machine instruction located at the address next to the JCXNZ instruction. By using the JCXNZ instruction in this way, 65536 times (16
The loop processing up to the maximum loop number specified by the bit counter operand is realized.

Consider implementing a function similar to the JCXNZ instruction with a conventional microprocessor. FIG. 5 is a block diagram showing the configuration of an instruction execution unit of a 16-bit microprocessor having the same machine instruction (decrement and branch instruction) function as the JCXNZ instruction.

The register file 21 has eight 16-bit registers AX30, BX32, CX33, DX3.
4, SI35, DI36, BP37, SP38, and two sets of 16-bit buses M-Bus and S-Bus.
Connected to. M-Bu from each 16-bit register
Decoders MDEC22a, SD for both s and S-Bus
The contents of the 16-bit register designated by the read register designation signal of the EC 23 can be read.

Further, the value on the M-Bus can be written in the 16-bit register designated by the write register designation signal of the decoder MDEC 22a. The 16-bit binary arithmetic logic unit ALU24 has two inputs M-
It is connected to both Bus and S-Bus. The value on the M-Bus is input to one input of the ALU 24 by the decoder MDEC2.
2a is set by the write register designating signal, and similarly the value on the S-Bus is input to the decoder SDEC at the other input.
It is set by the write register designating signal 23. The operation control decoder ADEC25 specifies the type of operation (arithmetic operation, logical operation) performed by the ALU 24. The calculation result of the calculation performed by the ALU 24 is read to the M-Bus by the read register designating signal of the decoder MDEC 22a.

The status of the operation result of the ALU 24, for example, carry / borrow occurrence, overflow occurrence, operation result is zero, and the sign is the operation status determination circuit STGEN26.
Checked by.

These states are selectively latched into flags in the processor status word PSW27. The contents of this PSW 27 can also be read to the M-Bus.

In addition, the M-Bus has a 16-bit program counter PC28 and a 16-bit register DISP for storing displacement values of branch instructions.
29 is connected, and is read to the M-Bus by the read register designation signal of the decoder MDEC22a02.

MDEC22a, SDEC23, ADEC
The input of 25 is connected to the micro instruction register MR41. MR41 is a micro address register MAR
The contents of the microinstruction memory MMEM42a stored at the address designated by the contents of 43 are latched.

Micro address register MAR43
Holds the address of the next micro name to be executed and latches the output of the micro address generator MAGEN44. The MAGEN 44 includes an incrementer that increments the value of the MAR 43, a branch address generator that generates a branch destination address by using a part of the value of the MR 41, and the like. Although not shown in the drawing, the MAGEN 44 includes an initialization circuit for generating a start address of a microprogram composed of a sequence of a plurality of microinstructions from a decoding result of a machine instruction generated in an instruction decoding unit of the present microprocessor. Is included.

The branch control circuit BRCNT45a is connected to the MR4.
The output of 1 detects that the microinstruction is a branch instruction, selects and determines the necessary branch condition, and the branch is taken.
Notify the MSEQ 46 whether to en. BRCN
The branch condition determined by T45a is STGEN.
The state of the operation result of the ALU 24 generated by 26a is also included. Micro sequencer MSEQ46 is MAGEN44
Control a sequence of microprograms including branch instructions generated by the BRCNT 45a. MSE
The timing signal ENDM generated by Q46 indicates that the microprogram sequence is completed.

The microinstructions stored in the MMEM 42a are as follows: 1) The MDEC 22a and SDEC 23 make MB
a data transfer instruction for controlling data transfer via us and S-Bus, 2) a branch instruction for judging a condition designated by the BRCNT 45a and selectively setting a new address in the MAR 43, 3) an ALU 24 by the ADEC 25
4) Control signal decoder CDEC4
A field command such as a control command for transmitting a control signal to each part of the microprocessor including the command execution part by 7a is included.

Microinstructions that are accessed at one time include:
A plurality of field instructions are included, for example, a plurality of (M-Bu
It is possible to simultaneously describe (execute) a data transfer instruction of s and S-Bus) and an operation instruction and a branch instruction at the same time.

Decrement and
The execution of a branch instruction will be described. When the decrement-and-branch instruction is decoded by the instruction decoding unit (not shown), the head address of the processing microprogram of this machine instruction is set in the MAR 43 via the MAGEN 44. A flow chart of the microprogram for this processing is shown in FIG.

First, in step S11, C is issued by a transfer instruction.
The contents of the X register 33 are transferred to the input of the ALU 24 via the M-Bus by the transfer command. Next in step S12
Then, a decrement operation is designated to the ALU 24 by the operation instruction and the operation is performed (the content of the CX register 33 is decremented by 1). Further, in step S13, the decrement result by the ALU 24 is written back to the CX register 33 via the M-Bus by the transfer instruction by the transfer instruction.

Next, in step S14, the branch instruction determines the zero state generated by STGEN26 in the state of the decrement operation result, and if it is determined to be zero, the branch is taken and it is determined that it is not zero. For example, the branch is not taken because the machine instruction is branched. If zero is determined in step S14, a control command for ending this process is executed in step S15, and the microprogram is ended.

If it is determined in step S14 that the value is not zero, the process proceeds to step 15 to perform branching processing to the target address. In this branch processing, 1) the contents of the PC 28 and the DISP 29 are transferred to the ALU 24 via the M-Bus by a transfer instruction, and 2) the sum of these is calculated as a branch destination (target) address by an operation (addition) instruction, and 3). This result is transferred to the PC 28 via the M-Bus by a transfer instruction. 4) Although not shown in the drawing, the instruction fetch unit of the present microprocessor is initialized and the PC 28
The control instruction for fetching the instruction code from the target address transferred to is executed, and 5) the control instruction for ending this processing is executed in step S16 to end the microprogram.

[0027]

In the conventional microprogram processing described above, in order to confirm that the loop processing is to be continued, C in steps S11 and S12 is used.
It is indispensable to decrement the X register 33 and determine the decrement result in step 14 (a series of processes is called a loop determination process). In order to improve the performance of loop control (reduce the overhead of loop processing control), it is important to perform the above-described loop determination processing at high speed in addition to the branching operation for forming an essential loop in step 15.

However, as described above, the count operand is updated in the loop determination processing (the processing of steps S11 and 12 in the conventional example) and the update result is determined (the processing of step 13 in the conventional example). There is a drawback that the judgment cannot be made until the update of the count operand is completed (series processing is performed).

With the exception of these drawbacks, an object of the present invention is to detect and store that the result is a value immediately before the loop processing end condition is satisfied when updating the count operand,
Another object of the present invention is to provide a branch control device capable of stabilizing the detection state stored in the next loop determination process.

[0030]

According to the structure of the present invention, in a branch controller of a microprocessor having a decrement-and-branch instruction as a machine instruction, a count immediately before the end value condition of the decrement-and-branch instruction is satisfied.・ Detection means for detecting the operand,
Holding means for holding the detection result of the detecting means at a specific timing; determining means for determining the value of the holding means;
And a control unit for selectively performing a branching operation according to a result of the value of the holding unit determined by the determination unit.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an instruction execution unit of a microprocessor which is an embodiment to which the present invention is applied. This microprocessor has a decrement and branch instruction similar to the conventional example. The structure is different from that of the conventional microprocessor in the following points, and the other parts have the same structure.

1) The STGEN 26 includes a mechanism for detecting and holding that the result of the arithmetic operation by the ALU 24 becomes 1.

2) A branch (micro) instruction for determining the state detected by the BRCNT 45 by 1) is added. Therefore, the condition signal CXNONE is added from STGEN 26 to BRCNT 45.

3) The CDEC 47 generates the control signal SETFF which controls the STGEN 26. This control signal is generated in response to the execution of a specific control (micro) instruction.

4) Branches stored in MMEM 42
The microprogram corresponding to the AND / DECREMENT instruction is different.

5) CX register 3 by MDEC 22
The write register designation signal for 3 is connected to STGEN 26.

FIG. 2 shows a part of the difference between the STGEN 26 and the conventional example among these differences. The "1" detector 11 monitors the output (calculation result) of the ALU 24 and detects that it is 1 (0001h). This circuit can be functionally composed of 16-input NOR (negative logical sum) or the like (only the least significant bit is inputted with negative logical logic).

The timing latch 12 latches the output of the "1" detector 11 every time the operation result is read from the ALU 24 and outputs the inverted logic to indicate that the operation result is not 1. This output is held until the calculation result from the ALU 24 is read next time.

The 1-bit register FF (1) 13 is S
The output of the timing latch is stored when the control (micro) instruction that generates the ETFF signal is executed. This S
The ETFF signal is sent to the CX33 in the microprogram corresponding to the decrement and branch instruction processing.
It is generated by the CDEC 47 by the execution of a control command during decrement by the ALU 24 of the contents. FF13
The output CXNONE signal of is connected to the BRCNT 45, and the state can be determined by a branch (micro) instruction.

The FF 13 has a 2-input AND gate 15
Is reset by the output of. The output of the 2-input AND gate 15 is CX except when the microprogram corresponding to the decrement and branch instruction processing is executed.
Indicates that an update to register 33 has occurred. That is, when the CX register 33 is newly set or updated by a machine instruction other than the decrement and branch instruction, it is avoided that the value held by the FF 13 is not guaranteed to be correct. Further, the FF 13 is reset when the present microprocessor is reset.

The RS flip-flop (2) 14 is SE
It is set by the TFF signal and reset by the ENDM signal as well as the microprocessor reset (not shown). The output of the FF 14 indicates the period during which the microprogram corresponding to the decrement-and-branch instruction processing is being executed (excluding the period until the value of the CX 33 is decremented by the ALU 34).

FIG. 3 is a flow chart for explaining the processing of FIG. The operation of the microprogram corresponding to the decrement and branch instruction processing stored in the MMEM 42 will be described.

First, in step S1, the state of the CXNONE signal is determined by a branch (micro) instruction, and STGEN is set.
If it is determined that 26 is not the immediately preceding operation result 1, the branch is not taken. If it is determined that it is 1, the branch is taken for normal loop processing.

If it is determined in step S1 that the value is not 1, the process proceeds to step S2 for branching to the target address (S15 in the conventional example). 1) PC28 and DI
The contents of SP29 are transferred to the ALU 24 via the M-Bus by the transfer command, and 2) the sum of these is obtained as the branch destination (target) address by the operation (addition) command,
3) This result is transferred to P via M-Bus by the transfer command.
Transfer to C28, 4) The target fetched by initializing the instruction fetch unit of this microprocessor and transferring to PC28.
Execute the control instruction that causes the instruction code fetch from the address.

Subsequent to step S2, in step S3 (conventional example S11), the contents of the CX register 33 are transferred by the transfer command to the input of the ALU 24 via the M-Bus by the transfer command. Further, in step S4 (conventional example S12), a decrement operation is designated to the ALU 24 by an operation instruction,
The calculation is performed (the content of the CX register 33 is decremented by 1). Next, in step S5 (conventional example S13), a SETFF signal is generated by a control command, FF13 is sampled, FF14 is set, and step S5 is performed.
Avoid resetting the FF 13 when the CX register 33 is updated by.

Subsequent to step S5, in step S6 (conventional example S13), the decrement result by the AUL 24 is written back to the CX register 33 via the M-Bus by the transfer instruction. Further, step S7 (conventional example S1
In 6), execute the control command to end this process, and
After generating the DM signal and resetting the FF2, the microprogram is terminated.

When it is determined in step S1 that it is 1 (or when the CX register 33 is updated), the process proceeds to step S8 and the same process as the decrement-and-branch process in the conventional example is performed.

In this embodiment, the operation has been described step by step. However, as described above, one microinstruction can describe a plurality of field instructions. Can be described.

This microprogram updates the CX register 33 after the instruction code refetch (branch) operation (corresponding to step S2) (steps S3 to S3).
(Corresponding to S7) is different from the above-described conventional microprogram. When performing a branch operation, there is a delay until a new instruction stream is notified as the instruction fetch section → the instruction decode section → the instruction execution section. Therefore, it takes a normal number to start processing the next machine instruction in the instruction execution section. Invalid periods of clock periods occur.

In this microprogram, the CX register 33 is updated by utilizing this invalid time so that this updating process does not appear as an overhead of executing the microprogram.

As described above, according to this embodiment, when the count operand does not have the value immediately before the end condition due to the immediately preceding decrement and branch instruction, the decrement and branch instruction can be processed at high speed. Also, if the count operand has a value immediately before the end condition, or if the count operand is updated by another machine instruction, a micro-instruction which is one step extra than the conventional microprocessor is required. In loop processing control, the performance when loop processing continues is dominant, and this overhead can be ignored.

Although the control by the microprogram has been described in this embodiment, it is obvious that the equivalent control can be performed by the hardware logic.

FIG. 4 is a block diagram of a calculation status judging circuit for explaining the second embodiment of the present invention. In the present embodiment, the decrement and branch instruction refers to the value of the CX register 33 as a count operand, and also the zero flag ZF16 stored in the PSW 27.
The value of is referred to as the loop processing end condition.

That is, the loop processing end condition is as follows. 1) The content of CX register 33 is 0 as a result of decrement or ZF16 is 1 2) The content of CX register 33 is 0 as a result of decrement or 0 of ZF16 is 0 The decrement-and-branch instruction with these loop processing end conditions is The execution / termination of loop processing is controlled by the result of the arithmetic (machine) instruction executed immediately before. This decrement and branch instruction enables various forms of loop processing control by being used in combination with the decrement and branch instruction that refers to only the count operand described in the first embodiment.

The flag selector FSEL17 selects various flag states (positive logic / negative logic) in the PSW 27 according to a flag selection signal generated by the instruction decoding unit or the instruction execution unit according to the type of branch and decrement instruction. . The 2-input AND gate 18 has one input as the output of the FF 13 and the other input as FSEL.
The output of the FF 13 is masked by the state of the flag connected to the output of the FSEL 17 and selected by the FSEL 17. The output of the 2-input AND gate 18 indicates L indicating the condition for continuing the loop processing.
As the OOPNEND signal, the CX in the first embodiment
It is connected to BRCNT 45 instead of the NONE signal.

In the microprogram corresponding to the decrement and branch instruction, in addition to referring to the decrement result of the CX register 33 after the LOOPNEND signal is determined not to indicate the loop continuation condition in the first step. The process may be the same as the flowchart shown in FIG. 3 except that it is necessary to refer to the state of ZF16.

In the LOOPNEND signal, the value of the result count operand (CX register 33) of the immediately preceding decrement and branch instruction in the FF 13 is 1,
It becomes active when the value of ZF16 is the condition designated by the flag selection signal.

Here, the example in which the zero flag is referred to among the flags stored in the PSW 27 has been described, but the decrement and control which is loop-controlled by the carry flag, the sign flag, or a combination of a plurality of flag states. The present invention can also be applied to branch instructions.

[0059]

As described above, according to the present invention, it is possible to realize a microprocessor capable of executing decrement-and-branch instructions at high speed, and as a result, it is possible to provide high-speed loop processing.

In software processing, a loop processing having a multiple structure is often formed. In this case, the decrement-and-branch instruction is used in the nested structure, and the effect of the present invention is exerted only by the decrement-and-branch instruction used in the innermost loop processing. However, in practice, the inner loop processing is more dominant in the overall processing performance, and it is clear that improving the performance of the innermost loop processing is the most effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

2 is a circuit diagram showing a partial configuration of a calculation status determination circuit in the embodiment of FIG.

FIG. 3 is a flowchart of a microprogram for executing a branch and decrement instruction execution process in the embodiment of FIG.

FIG. 4 is a circuit diagram showing a partial configuration of a calculation status determination circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a configuration of an instruction execution unit of a conventional microprocessor.

6 is a branch diagram of the microprocessor of FIG.
The flowchart of the microprogram which performs the execution process of an AND decrement instruction.

[Explanation of symbols]

 11 “1” Detector 12 Timing Latch 13 1-bit Register 14 RS Flip-Flop 15, 18 2-Input AND Gate 16 Zero Flag 17 Flag Selector 21 Register File 22, 22a Decoder for M-Bus 23 S-Bus Decoder 24 Binary arithmetic and logic unit 25 Operation control decoder 26, 26a Operation status determination circuit 27 Processor status word 28 Program counter 29 Displacement register 31-38 (AX to SP) register 41 Micro instruction register 42, 42a Micro instruction memory 43 Micro address register 44 Micro address generator 45, 45a Branch control circuit 46 Micro sequencer 47, 47a Control signal decoder

Claims (2)

[Claims] 1. A branch control device of a microprocessor having a decrement and branch instruction as a machine instruction, and a detection means for detecting a count operand immediately before a condition for ending the decrement and branch instruction is satisfied, Holding means for holding the detection result of the detection means at a specific timing, judgment means for judging the value of the holding means, and control for selectively branching operation based on the result of judgment of the value of the holding means by the judgment means. And a branch control device. 2. The invalidating means for invalidating the value held in the holding means, wherein the invalidating means invalidates the held value of the holding means based on the detection result of the detecting means. Branch control device.