JPH06237101A - High frequency switch - Google Patents
High frequency switchInfo
- Publication number
- JPH06237101A JPH06237101A JP5022683A JP2268393A JPH06237101A JP H06237101 A JPH06237101 A JP H06237101A JP 5022683 A JP5022683 A JP 5022683A JP 2268393 A JP2268393 A JP 2268393A JP H06237101 A JPH06237101 A JP H06237101A
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- Japan
- Prior art keywords
- terminal
- antenna
- field effect
- effect transistor
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Transceivers (AREA)
- Waveguide Switches, Polarizers, And Phase Shifters (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高周波回路に用いる高
周波スイッチに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency switch used in a high frequency circuit.
【０００２】[0002]
【従来の技術】近年、急速に普及しつつある移動体通信
機器においては、安定した送信および受信を行う目的で
様々な方式のダイバーシチが用いられている。そのダイ
バーシチのうち、アンテナ切り換え送信ダイバーシチお
よび検波後切り換え受信ダイバーシチを行うには、２本
のアンテナ、２系統の受信系および１系統の送信系の接
続切り換えを行うための高周波スイッチが必要である。2. Description of the Related Art In recent years, various types of diversity have been used in mobile communication devices which are rapidly becoming widespread, for the purpose of stable transmission and reception. In order to perform antenna switching transmission diversity and post-detection switching reception diversity among the diversity, a high frequency switch for switching connection between two antennas, two reception systems and one transmission system is required.
【０００３】以下に図面を参照しながら、上記した従来
の高周波スイッチの一例について説明する。An example of the above-mentioned conventional high frequency switch will be described below with reference to the drawings.
【０００４】図２は従来の高周波スイッチの回路図を示
すものである。図２において、201は第１の受信端子、2
02は第１のアンテナ端子、203は送信端子、204は第２の
アンテナ端子、205は第２の受信端子、206は第１の電界
効果トランジスタ(ＦＥＴ１)、207は第２の電界効果ト
ランジスタ(ＦＥＴ２)、208は第３の電界効果トランジ
スタ(ＦＥＴ３)、209は第４の電界効果トランジスタ(Ｆ
ＥＴ４)、210は第５の電界効果トランジスタ(ＦＥＴ
５)、211は第６の電界効果トランジスタ(ＦＥＴ６)、21
4，215，216，217，218，219は制御端子、222，223，22
4，225，226，227は抵抗である。FIG. 2 is a circuit diagram of a conventional high frequency switch. In FIG. 2, 201 is the first receiving terminal, 2
02 is a first antenna terminal, 203 is a transmitting terminal, 204 is a second antenna terminal, 205 is a second receiving terminal, 206 is a first field effect transistor (FET1), and 207 is a second field effect transistor ( FET2), 208 is a third field effect transistor (FET3), 209 is a fourth field effect transistor (F
ET4), 210 is a fifth field effect transistor (FET)
5), 211 are sixth field effect transistors (FET6), 21
4,215,216,217,218,219 are control terminals, 222,223,22
4, 225, 226 and 227 are resistors.
【０００５】以上のように構成された高周波スイッチに
ついて、以下その動作について説明するが、以下、ドレ
イン端子とソース端子のどちらか一方を接地し、他方を
接続端子とし、ゲート端子を制御端子とした電界効果ト
ランジスタを並列ＦＥＴと略称し、ＦＥＴ１とＦＥＴ６
が該当する。ドレイン端子とソース端子をそれぞれ接続
端子とし、ゲート端子を制御端子とした電界効果トラン
ジスタを直列ＦＥＴと略称し、ＦＥＴ２ないしＦＥＴ５
が該当する。The operation of the high-frequency switch configured as described above will be described below. Hereinafter, one of the drain terminal and the source terminal is grounded, the other is a connection terminal, and the gate terminal is a control terminal. Field effect transistors are abbreviated as parallel FETs, and FET1 and FET6
Is applicable. A field-effect transistor having a drain terminal and a source terminal as connection terminals and a gate terminal as a control terminal is abbreviated as a series FET.
Is applicable.
【０００６】そして、電界効果トランジスタのゲート−
ソース間電圧がピンチオフ電圧以上である状態をＯＦＦ
状態と略称し、ゲート−ソース間電圧がゼロボルトであ
る状態をＯＮ状態と略称する。The gate of the field effect transistor
OFF when the source voltage is higher than the pinch-off voltage
It is abbreviated as a state, and a state in which the gate-source voltage is zero volt is abbreviated as an ON state.
【０００７】アンテナ切り換え送信ダイバーシチおよび
検波後切り換え受信ダイバーシチ方式では、送信時には
第１のアンテナ端子202と送信端子203または第２のアン
テナ端子204と送信端子203のうち、どちらか一方を接
続、他方を遮断し、接続した方のアンテナを用いて送信
する。受信時には第１のアンテナ端子202と第１の受信
端子201を接続して受信すると共に、第２のアンテナ端
子204と第２の受信端子205を接続して２系統の受信を行
う。以上、送信２種類、受信１種類の接続をしたとき
の、各々の電界効果トランジスタの動作状態を(表１)に
示す。In the antenna switching transmission diversity and post-detection switching reception diversity systems, either one of the first antenna terminal 202 and the transmission terminal 203 or the second antenna terminal 204 and the transmission terminal 203 is connected and the other is connected at the time of transmission. Block and transmit using the connected antenna. At the time of reception, the first antenna terminal 202 and the first reception terminal 201 are connected to receive, and the second antenna terminal 204 and the second reception terminal 205 are connected to perform two-system reception. The operation state of each field effect transistor when two types of transmission and one type of reception are connected is shown in Table 1 above.
【０００８】[0008]
【表１】 [Table 1]
【０００９】[0009]
【発明が解決しようとする課題】しかしながら上記のよ
うな構成では、第１のアンテナ端子202と送信端子203の
間および第２のアンテナ端子204と送信端子203の間の接
続遮断時のアイソレーションが不足し、２本のアンテナ
のうち一方のアンテナを用いて送信を行っているとき
に、他方のアンテナより不要な電波の放射が生じるとい
う問題点を有していた。However, in the above-mentioned configuration, the isolation between the first antenna terminal 202 and the transmission terminal 203 and between the second antenna terminal 204 and the transmission terminal 203 at the time of disconnection is eliminated. There is a shortage, and there is a problem that when transmitting using one of the two antennas, unnecessary radio waves are emitted from the other antenna.
【００１０】本発明は上記問題点に鑑み、不要な電波の
放射を抑圧する高周波スイッチを提供することを目的と
する。In view of the above problems, it is an object of the present invention to provide a high frequency switch that suppresses unnecessary radio wave radiation.
【００１１】[0011]
【課題を解決するための手段】上記問題点を解決するた
めに本発明の高周波スイッチは、従来の高周波スイッチ
回路の第１のアンテナ端子と送信端子の間の直列ＦＥＴ
の第１のアンテナ端子側接続端子、および第２のアンテ
ナ端子と送信端子の間の直列ＦＥＴの第２のアンテナ端
子側接続端子に、それぞれ並列ＦＥＴを接続した回路で
ある。In order to solve the above problems, a high frequency switch of the present invention is a series FET between a first antenna terminal and a transmission terminal of a conventional high frequency switch circuit.
Is a circuit in which parallel FETs are connected to the first antenna terminal side connection terminal and the second FET terminal side connection terminal of the series FET between the second antenna terminal and the transmission terminal, respectively.
【００１２】[0012]
【作用】本発明によれば、並列ＦＥＴを接続したことに
より、第１のアンテナ端子と送信端子の間、および第２
のアンテナ端子と送信端子のアイソレーションを増大
し、２本のアンテナのうち一方のアンテナを用いて送信
を行っているときに、他方のアンテナからの不要な電波
の放射を抑圧することとなる。According to the present invention, since the parallel FETs are connected, it is possible to connect the first antenna terminal and the transmission terminal, and
The isolation between the antenna terminal and the transmission terminal is increased, and when one of the two antennas is used for transmission, unnecessary radio wave emission from the other antenna is suppressed.
【００１３】[0013]
【実施例】図１は本発明の一実施例における高周波スイ
ッチの回路図である。図１において、101は第１の受信
端子、102は第１のアンテナ端子、103は送信端子、104
は第２のアンテナ端子、105は第２の受信端子、106は第
１の電界効果トランジスタ (ＦＥＴ１)、107は第２の電
界効果トランジスタ(ＦＥＴ２)、108は第３の電界効果
トランジスタ(ＦＥＴ３)、109は第４の電界効果トラン
ジスタ(ＦＥＴ４)、110は第５の電界効果トランジスタ
(ＦＥＴ５)、111は第６の電界効果トランジスタ(ＦＥＴ
６)、112は第７の電界効果トランジスタ(ＦＥＴ７)、11
3は第８の電界効果トランジスタ(ＦＥＴ８)、114，11
5，116，117，118，119，120，121は各ＦＥＴ１ないし
ＦＥＴ８のゲート端子であり、これを制御端子とする。
122，123，124，125，126，127，128，129は抵抗であ
る。1 is a circuit diagram of a high frequency switch according to an embodiment of the present invention. In FIG. 1, 101 is a first receiving terminal, 102 is a first antenna terminal, 103 is a transmitting terminal, 104
Is a second antenna terminal, 105 is a second receiving terminal, 106 is a first field effect transistor (FET1), 107 is a second field effect transistor (FET2), and 108 is a third field effect transistor (FET3). 109 is a fourth field effect transistor (FET4), 110 is a fifth field effect transistor
(FET5), 111 is a sixth field effect transistor (FET
6), 112 are seventh field effect transistors (FET7), 11
3 is an eighth field effect transistor (FET8), 114 and 11
5, 116, 117, 118, 119, 120 and 121 are gate terminals of the FETs 1 to 8 and are used as control terminals.
122, 123, 124, 125, 126, 127, 128, 129 are resistors.
【００１４】図１に示すように、第１の電界効果トラン
ジスタ106(ＦＥＴ１)は、ドレイン端子およびソース端
子のどちらか一方を接地し、他方を第１の接続端子106-
1とし、ゲート端子を制御端子114とした並列ＦＥＴ１を
構成する。第２の電界効果トランジスタ107(ＦＥＴ２)
はドレイン端子とソース端子のどちらか一方を第２の接
続端子107−2とし、他方を第３の接続端子107-3とし、
ゲート端子を制御端子115とした直列ＦＥＴ２を構成す
る。第３の電界効果トランジスタ108(ＦＥＴ３)はドレ
イン端子およびソース端子のどちらか一方を接地し、他
方を第４の接続端子108-4とし、ゲート端子を制御端子1
16とした並列ＦＥＴ３を構成する。第４の電界効果トラ
ンジスタ109(ＦＥＴ４)はドレイン端子とソース端子の
どちらか一方を第５の接続端子109-5とし、他方を第６
の接続端子109-6とし、ゲート端子を制御端子117とした
直列ＦＥＴ４を構成する。第５の電界効果トランジスタ
110(ＦＥＴ５)はドレイン端子とソース端子のどちらか
一方を第７の接続端子110-7とし、他方を第８の制御端
子110-8とし、ゲート端子を制御端子118とした直列ＦＥ
Ｔ５を構成する。第６の電界効果トランジスタ111(ＦＥ
Ｔ６)はドレイン端子およびソース端子のどちらか一方
を接地し、他方を第９の接続端子111-9とし、ゲート端
子を制御端子119とした並列ＦＥＴ６を構成する。第７
の電界効果トランジスタ112(ＦＥＴ７)はドレイン端子
とソース端子のどちらか一方を第10の接続端子112-10と
し、他方を第11の接続端子112-11とし、ゲート端子を制
御端子120とした直列ＦＥＴ７を構成する。第８の電界
効果トランジスタ113(ＦＥＴ８)はドレイン端子および
ソース端子のどちらか一方を接地し、他方を第12の接続
端子113-12とし、ゲート端子を制御端子121とした並列
ＦＥＴ８を構成する。As shown in FIG. 1, in the first field effect transistor 106 (FET1), one of the drain terminal and the source terminal is grounded, and the other is the first connection terminal 106-.
1 and the parallel FET 1 having the gate terminal as the control terminal 114 is configured. Second field effect transistor 107 (FET2)
Either the drain terminal or the source terminal as the second connection terminal 107-2 and the other as the third connection terminal 107-3,
The series FET 2 having the gate terminal as the control terminal 115 is configured. In the third field effect transistor 108 (FET3), either the drain terminal or the source terminal is grounded, the other is the fourth connection terminal 108-4, and the gate terminal is the control terminal 1
16 parallel FET 3 is configured. In the fourth field effect transistor 109 (FET4), one of the drain terminal and the source terminal is the fifth connection terminal 109-5, and the other is the sixth terminal 109-5.
The serial FET 4 having the gate terminal as the control terminal 117 and the connection terminal 109-6 as shown in FIG. Fifth field effect transistor
110 (FET5) is a series FE in which one of the drain terminal and the source terminal is the seventh connection terminal 110-7, the other is the eighth control terminal 110-8, and the gate terminal is the control terminal 118.
Configure T5. Sixth field effect transistor 111 (FE
T6) constitutes a parallel FET 6 in which one of the drain terminal and the source terminal is grounded, the other is the ninth connection terminal 111-9, and the gate terminal is the control terminal 119. 7th
In the field effect transistor 112 (FET7), one of the drain terminal and the source terminal is the tenth connection terminal 112-10, the other is the eleventh connection terminal 112-11, and the gate terminal is the control terminal 120 in series. Configure FET7. The eighth field effect transistor 113 (FET8) constitutes a parallel FET8 in which one of the drain terminal and the source terminal is grounded, the other is the twelfth connection terminal 113-12, and the gate terminal is the control terminal 121.
【００１５】さらに前記第１の受信端子101と前記第１
の接続端子106-1を接続し、前記第１の接続端子106-1と
前記第２の接続端子107-2を接続し、前記第３の接続端
子107-3と前記第１のアンテナ端子102を接続する。Further, the first receiving terminal 101 and the first receiving terminal 101
Connecting terminal 106-1, connecting the first connecting terminal 106-1 to the second connecting terminal 107-2, connecting the third connecting terminal 107-3 to the first antenna terminal 102. Connect.
【００１６】また、前記第１のアンテナ端子102と前記
第４の接続端子108-4を接続し、前記第４の接続端子108
-4と前記第５の接続端子109-5を接続し、前記第６の接
続端子109-6と前記送信端子103を接続し、前記送信端子
103と前記第７の接続端子110-7を接続する。Further, the first antenna terminal 102 and the fourth connection terminal 108-4 are connected to each other, and the fourth connection terminal 108 is connected.
-4 and the fifth connection terminal 109-5 are connected, the sixth connection terminal 109-6 and the transmission terminal 103 are connected, and the transmission terminal
103 and the seventh connection terminal 110-7 are connected.
【００１７】また、前記第８の接続端子110-8と前記第
９の接続端子111-9を接続し、前記第９の接続端子111-9
と前記第２のアンテナ端子104を接続し、前記第２のア
ンテナ端子104と前記第10の接続端子112-10を接続し、
前記第11の接続端子112-11と前記第12の接続端子113-12
を接続し、前記第12の接続端子113-12と前記第２の受信
端子105を接続する。Further, the eighth connection terminal 110-8 and the ninth connection terminal 111-9 are connected to each other, and the ninth connection terminal 111-9 is connected.
And the second antenna terminal 104 are connected, the second antenna terminal 104 and the tenth connection terminal 112-10 are connected,
The eleventh connection terminal 112-11 and the twelfth connection terminal 113-12
And the twelfth connection terminal 113-12 and the second reception terminal 105 are connected.
【００１８】以上のように構成された高周波スイッチに
ついて、以下その動作について説明する。The operation of the high frequency switch configured as described above will be described below.
【００１９】各々の電界効果トランジスタＦＥＴ１〜Ｆ
ＥＴ８の動作状態を(表２)に示す通りに組み合わせ、制
御することにより、送信時には第１のアンテナ端子102
と送信端子103または第２のアンテナ端子104と送信端子
103のうち、どちらか一方を接続、他方を遮断し、受信
時には第１のアンテナ端子102と第１の受信端子101を接
続して受信すると共に、第２のアンテナ端子104と第２
の受信端子105を接続して２系統の受信を行い、アンテ
ナ切り換え送信ダイバーシチおよび検波後切り換え受信
ダイバーシチを行う。Each field effect transistor FET1 to F
By combining and controlling the operating states of the ET8 as shown in (Table 2), the first antenna terminal 102 during transmission can be controlled.
And the transmission terminal 103 or the second antenna terminal 104 and the transmission terminal
Of the 103, one of them is connected and the other is cut off, and at the time of reception, the first antenna terminal 102 and the first reception terminal 101 are connected for reception, and the second antenna terminal 104 and the second antenna terminal 104 are connected.
The reception terminal 105 is connected to perform two-system reception, and antenna switching transmission diversity and post-detection switching reception diversity are performed.
【００２０】[0020]
【表２】 [Table 2]
【００２１】[0021]
【発明の効果】以上説明したように本発明の高周波スイ
ッチは、従来の高周波スイッチの第１のアンテナ端子と
送信端子の間の直列ＦＥＴの第１のアンテナ端子側接続
端子、および第２のアンテナ端子と送信端子の間の直列
ＦＥＴの第２のアンテナ端子側接続端子にそれぞれ並列
ＦＥＴを接続したことにより、第１のアンテナ端子と送
信端子の間、および第２のアンテナ端子と送信端子の間
のアイソレーションを増大し、２本のアンテナのうち一
方のアンテナを用いて送信を行っているときに、他方の
アンテナより放射される不要な電波の放射を抑圧するこ
ととなる。As described above, the high frequency switch of the present invention includes the first antenna terminal side connection terminal of the series FET between the first antenna terminal and the transmission terminal of the conventional high frequency switch, and the second antenna. Between the first antenna terminal and the transmission terminal and between the second antenna terminal and the transmission terminal by connecting the parallel FETs to the second antenna terminal side connection terminal of the series FET between the terminal and the transmission terminal, respectively. When the transmission is performed using one of the two antennas, the unnecessary radio wave emitted from the other antenna is suppressed.
【図１】本発明の一実施例における高周波スイッチの回
路図である。FIG. 1 is a circuit diagram of a high frequency switch according to an embodiment of the present invention.
【図２】従来の高周波スイッチの回路図である。FIG. 2 is a circuit diagram of a conventional high frequency switch.
101，201…第１の受信端子、 102，202…第１のアンテ
ナ端子、 103，203…送信端子、 104，204…第２のア
ンテナ端子、 105，205…第２の受信端子、106，206…
第１の電界効果トランジスタ(ＦＥＴ１)、 107，207…
第２の電界効果トランジスタ(ＦＥＴ２)、 108，208…
第３の電界効果トランジスタ(ＦＥＴ３)、 109，209…
第４の電界効果トランジスタ(ＦＥＴ４)、 110，210…
第５の電界効果トランジスタ(ＦＥＴ５)、 111，211…
第６の電界効果トランジスタ(ＦＥＴ６)、 112…第７
の電界効果トランジスタ(ＦＥＴ７)、 113…第８の電
界効果トランジスタ(ＦＥＴ８)、 114，115，116，11
7，118，119，120，121，214，215，216，217，218，21
9…制御端子、 122，123，124，125，126，127，128，
129，222，223，224，225，226，227…抵抗。101, 201 ... First receiving terminal, 102, 202 ... First antenna terminal, 103, 203 ... Transmitting terminal, 104, 204 ... Second antenna terminal, 105, 205 ... Second receiving terminal, 106, 206 …
First field effect transistor (FET1), 107, 207 ...
Second field effect transistor (FET2), 108, 208 ...
Third field effect transistor (FET3), 109, 209 ...
Fourth field effect transistor (FET4), 110, 210 ...
Fifth field effect transistor (FET5), 111, 211 ...
Sixth field effect transistor (FET6), 112 ... Seventh
Field effect transistor (FET7), 113 ... Eighth field effect transistor (FET8), 114, 115, 116, 11
7, 118, 119, 120, 121, 214, 215, 216, 217, 218, 21
9 ... Control terminal, 122, 123, 124, 125, 126, 127, 128,
129,222,223,224,225,226,227 ... Resistance.
Claims (1)
続された直列電界効果トランジスタＦＥＴ４の前記第１
のアンテナ端子側の第５の接続端子、および第２のアン
テナ端子と前記送信端子の間に接続された直列電界効果
トランジスタＦＥＴ５の前記第２のアンテナ端子側の第
８の接続端子に、それぞれ並列電界効果トランジスタＦ
ＥＴ３，ＦＥＴ６が接続され、第１の受信端子と前記第
１のアンテナ端子の間に並列および直列の各電界効果ト
ランジスタＦＥＴ１，ＦＥＴ２が、また第２の受信端子
と前記第２のアンテナ端子の間に直列および並列の各電
界効果トランジスタＦＥＴ７，ＦＥＴ８がそれぞれ接続
され、前記各電界効果トランジスタＦＥＴ１ないしＦＥ
Ｔ８のＯＮ／ＯＦＦ動作の組み合わせ制御により前記第
１，第２のアンテナ端子と第１，第２の受信端子の接
続、第１，第２のアンテナ端子と送信端子の接続および
遮断を行うようにしたことを特徴とする高周波スイッ
チ。1. The first of the series field effect transistor FET4 connected between the first antenna terminal and the transmission terminal.
Of the serial field effect transistor FET5 connected between the second antenna terminal and the transmission terminal on the second antenna terminal side, respectively. Field effect transistor F
ET3 and FET6 are connected, and parallel and series field effect transistors FET1 and FET2 are provided between the first receiving terminal and the first antenna terminal, and between the second receiving terminal and the second antenna terminal. Field effect transistors FET7 and FET8 connected in series and in parallel with the field effect transistors FET1 to FE, respectively.
By the combined control of ON / OFF operation of T8, the connection between the first and second antenna terminals and the first and second reception terminals and the connection and disconnection between the first and second antenna terminals and the transmission terminals are performed. A high-frequency switch characterized in that
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5022683A JPH06237101A (en) | 1993-02-10 | 1993-02-10 | High frequency switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5022683A JPH06237101A (en) | 1993-02-10 | 1993-02-10 | High frequency switch |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06237101A true JPH06237101A (en) | 1994-08-23 |
Family
ID=12089668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5022683A Pending JPH06237101A (en) | 1993-02-10 | 1993-02-10 | High frequency switch |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06237101A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997023053A1 (en) * | 1995-12-18 | 1997-06-26 | Matsushita Electric Industrial Co., Ltd. | Transmitter-receiver circuit for radio communication and semiconductor integrated circuit device |
| JP2008306758A (en) * | 2003-11-11 | 2008-12-18 | Murata Mfg Co Ltd | High frequency module |
| US9252819B2 (en) | 2009-11-20 | 2016-02-02 | Hitachi Metals, Ltd. | High frequency circuit, high frequency circuit component, and communication apparatus |
-
1993
- 1993-02-10 JP JP5022683A patent/JPH06237101A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997023053A1 (en) * | 1995-12-18 | 1997-06-26 | Matsushita Electric Industrial Co., Ltd. | Transmitter-receiver circuit for radio communication and semiconductor integrated circuit device |
| US6341216B1 (en) | 1995-12-18 | 2002-01-22 | Matsushita Electric Industrial Co., Ltd. | Transmitter-receiver circuit for radio communication and semiconductor integrated circuit device |
| JP2008306758A (en) * | 2003-11-11 | 2008-12-18 | Murata Mfg Co Ltd | High frequency module |
| US7904031B2 (en) | 2003-11-11 | 2011-03-08 | Murata Manufacturing Co., Ltd. | High-frequency module for transmitting and receiving transmission-reception signals of at least three communication systems using a single antenna |
| US9252819B2 (en) | 2009-11-20 | 2016-02-02 | Hitachi Metals, Ltd. | High frequency circuit, high frequency circuit component, and communication apparatus |
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