JPH06237005A - Photodetector element and manufacture thereof - Google Patents

Photodetector element and manufacture thereof

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Publication number
JPH06237005A
JPH06237005A JP5020450A JP2045093A JPH06237005A JP H06237005 A JPH06237005 A JP H06237005A JP 5020450 A JP5020450 A JP 5020450A JP 2045093 A JP2045093 A JP 2045093A JP H06237005 A JPH06237005 A JP H06237005A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
region
pixel
conductivity type
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5020450A
Other languages
Japanese (ja)
Inventor
Kosaku Yamamoto
功作 山本
Yoshihiro Miyamoto
義博 宮本
Soichiro Hikita
聡一郎 匹田
Yoshio Watanabe
芳夫 渡邊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5020450A priority Critical patent/JPH06237005A/en
Publication of JPH06237005A publication Critical patent/JPH06237005A/en
Withdrawn legal-status Critical Current

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  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To obtain a photodetector element, whose dark current is decreased with respect to the photodetector element such as a photodiode. CONSTITUTION:Impurities, whose conductivity type is reverse with respect to a one-conductivity type HgCdTe substrate (P type) 1, are introduced into a specified pattern. An n-type layer (pixel region) 11 comprising a p-n junction region is provided in a photodetector element. In this photodetector element, the distribution of the concentration of the impurity carrier in the n-type layer 11 is made steep at the central part of the p-n junction region but gentle at the peripheral part of the p-n junction part.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は光検知素子、およびその
製造方法に係り、特に水銀・カドミウム・テルル(HgCd
Te)の化合物半導体基板に設けた赤外線検知素子、およ
びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light sensing element and a method for manufacturing the same, and more particularly to mercury-cadmium-tellurium (HgCd).
Te), an infrared detector provided on a compound semiconductor substrate, and a method for manufacturing the same.

【0002】[0002]

【従来の技術】p型のHgCdTe基板の所定領域に該基板と
逆伝導型の不純物原子を所定のパターンにイオン注入し
て形成した従来の光起電力型の赤外線検知素子について
説明する。
2. Description of the Related Art A conventional photovoltaic infrared detecting element formed by implanting impurity atoms of a conductivity type opposite to that of a p-type HgCdTe substrate in a prescribed pattern in a prescribed region will be described.

【0003】図8(a)に示すように、p型のHgCdTe基板1
にn型の不純物のボロン(B+ ) イオンを、レジスト膜
( 図示せず) をマスクとして用いてイオン注入法を用い
て導入し、n+ 層2を形成する。
As shown in FIG. 8 (a), a p-type HgCdTe substrate 1 is used.
Boron (B + ) ions, which are n-type impurities, are added to the resist film.
Using an ion implantation method (not shown) as a mask, an n + layer 2 is formed.

【0004】次いで図8(b)と図8(d)に示すように、該Hg
CdTe基板1上に硫化亜鉛(ZnS)の表面保護膜3を蒸着等
で形成し、該表面保護膜3の所定位置に接続用孔4を形
成後、金、或いはインジウム等の電極5を蒸着、および
レジスト膜を用いたリフトオフ等を用いて形成する。
Then, as shown in FIGS. 8 (b) and 8 (d), the Hg
A surface protective film 3 of zinc sulfide (ZnS) is formed on the CdTe substrate 1 by vapor deposition or the like, a connection hole 4 is formed at a predetermined position of the surface protective film 3, and then an electrode 5 of gold, indium or the like is vapor deposited, And a lift-off process using a resist film.

【0005】また、上記した方法の他に、図8(c)に示す
ように、ボロンをイオン注入した後、HgCdTe基板を所定
温度で加熱し、前記イオン注入したボロン原子を拡散さ
せてn+ 層2を拡張した方法もある。
In addition to the above-mentioned method, as shown in FIG. 8 (c), after ion implantation of boron, the HgCdTe substrate is heated at a predetermined temperature to diffuse the ion-implanted boron atoms to n +. There is also a method of expanding layer 2.

【0006】またその他の方法として、前記したn+
2を設けることで形成されたフォトダイオードに赤外線
を照射して検知する場合、該赤外線が光電変換されて形
成される少数キャリアの間のクロストーク現象を防止す
るために、n+ 層で形成されたpn接合領域の周辺部に
所定の間隔を隔てて格子状にn+ 層をイオン注入法で形
成して画素間のクロストークを防止する方法が採られて
いる。
As another method, when the photodiode formed by providing the n + layer 2 is irradiated with infrared rays for detection, the infrared rays are photoelectrically converted to cross the minority carriers. In order to prevent the talk phenomenon, cross talk between pixels is prevented by forming an n + layer in a lattice shape at a peripheral portion of a pn junction region formed by the n + layer with a predetermined interval by an ion implantation method. The method is adopted.

【0007】[0007]

【発明が解決しようとする課題】然し、従来の方法で形
成すると、このフォトダイオードを動作するために逆方
向バイアス電圧を印加すると、図9に示すように表面保
護膜3を介して矢印Aに示すように、表面リーク電流が
発生することが多く、この表面リーク電流がノイズとな
り、暗電流の発生の原因となる。
However, when formed by the conventional method, when a reverse bias voltage is applied to operate this photodiode, as shown in FIG. As shown, a surface leak current is often generated, and this surface leak current becomes noise and causes a dark current.

【0008】この表面リーク電流を減少するには、フォ
トダイオード6のpn接合領域の実際に電圧が印加され
ている領域、つまり空乏層を拡大し、pn接合領域に掛
かる電界強度を減少させると良い。そのためにはpn接
合領域を形成したHgCdTe基板1を200 °C の温度で熱処
理し、pn接合領域を緩やかな濃度勾配のGraded Junct
ion にすると良い。
In order to reduce the surface leak current, it is advisable to expand the region where the voltage is actually applied, that is, the depletion layer in the pn junction region of the photodiode 6 to reduce the electric field strength applied to the pn junction region. . For that purpose, the HgCdTe substrate 1 on which the pn junction region is formed is heat-treated at a temperature of 200 ° C, and the pn junction region is graded with a gentle concentration gradient.
I recommend setting it to ion.

【0009】然し、n+ 層2とp型のHgCdTe基板1の境
界のpn接合部分の全体をGraded Junction にすると、
+ 層2より発生する暗電流が多くなり、フォトダイオ
ード6の特性が劣化する。この理由は、n+ 層2のキャ
リア濃度が減少すると、少数キャリアの濃度が増加し、
また少数キャリアのフライトタイムが長くなることによ
り拡散長が増加するために上記した暗電流が増加する。
However, if the entire pn junction at the boundary between the n + layer 2 and the p-type HgCdTe substrate 1 is made a graded junction,
The dark current generated from the n + layer 2 increases and the characteristics of the photodiode 6 deteriorate. The reason is that when the carrier concentration of the n + layer 2 decreases, the concentration of minority carriers increases,
In addition, the dark current described above increases because the diffusion length increases as the flight time of minority carriers increases.

【0010】また従来の方法で、pn接合領域の周囲を
格子状のn+ 層で囲む構造では、格子状のn+ 層の幅が
広い程、クロストークは減少するが、このn+ 層のため
に光電流も減少する。
[0010] In conventional methods, in the structure surrounding the pn junction region by a lattice-like n + layer, as the width of the lattice-like n + layer is wide, the cross-talk is reduced, but the n + layer Therefore, the photocurrent also decreases.

【0011】従って赤外線検知素子の要求される性能、
種類によって、n+ 層の幅を制御して、光信号の量、ク
ロストークの度合いを所定の値に制御する方法を採って
いるのが現状である。
Therefore, the required performance of the infrared detecting element,
At present, a method is employed in which the width of the n + layer is controlled depending on the type to control the amount of optical signal and the degree of crosstalk to predetermined values.

【0012】然し、上記の方法ではHgCdTe結晶の組成
や、不純物原子の導入量等の結晶のパラメータ、或いは
赤外線検知素子の製造工程に於ける種々のパラメータに
より、信号量や、クロストークの発生度合い等を所定の
値に制御することは困難である。
However, in the above method, the signal amount and the degree of occurrence of crosstalk are determined by the composition of the HgCdTe crystal, crystal parameters such as the amount of impurity atoms introduced, and various parameters in the manufacturing process of the infrared detection element. It is difficult to control, etc. to a predetermined value.

【0013】本発明は上記した問題点を解決し、表面リ
ーク電流の発生の原因となるpn接合領域の周辺部のキ
ャリア濃度勾配を緩くしたGraded Junction 構造とし、
+層で発生する暗電流の増加を防止した状態で表面リ
ーク電流の発生を防止した光検知素子、およびその製造
方法の提供を目的とする。
The present invention solves the above problems and provides a graded junction structure in which the carrier concentration gradient in the peripheral portion of the pn junction region, which causes the generation of surface leakage current, is made gentle.
It is an object of the present invention to provide a photodetection element in which surface leak current is prevented from occurring while preventing an increase in dark current generated in the n + layer, and a method for manufacturing the same.

【0014】[0014]

【課題を解決するための手段】本発明の光検知素子は請
求項1に示すように、一伝導型の半導体基板に該基板と
逆伝導型の不純物を所定のパターンに導入し、pn接合
領域よりなる画素領域を設けた光検知素子に於いて、前
記画素領域の不純物キャリア濃度分布を、前記pn接合
領域の中央部では急峻とし、前記pn接合領域の周辺部
では緩やかにしたことを特徴とする。
According to a first aspect of the present invention, there is provided a pn junction region in which a one-conductivity type semiconductor substrate is doped with impurities of a reverse conduction type to the semiconductor substrate of a one-conductivity type in a predetermined pattern. In the photo-detecting element provided with the pixel region, the impurity carrier concentration distribution in the pixel region is steep in the central portion of the pn junction region and is gentle in the peripheral portion of the pn junction region. To do.

【0015】また請求項2に示すように、前記画素領域
の周辺部、画素領域間の中央の領域、或いは画素領域の
周辺部と画素領域間の中央の領域の何れかに幅、或いは
深さが制御可能な前記半導体基板の逆伝導型層を設けた
ことを特徴とする。
According to a second aspect of the present invention, the width or the depth is provided in any of the peripheral area of the pixel area, the central area between the pixel areas, or the central area between the peripheral area of the pixel area and the pixel area. A reverse conductivity type layer of the semiconductor substrate that can be controlled.

【0016】また請求項3に示すように、前記半導体基
板の逆伝導型層が、該半導体基板上に形成された陽極酸
化膜を加熱処理して設けていることを特徴とする。また
請求項4に示すように、一伝導型の半導体基板に該基板
と逆伝導型の不純物を所定のパターンに導入し、pn接
合領域よりなる画素領域を設けて光検知素子を製造する
方法に於いて、前記画素領域の周辺部、画素領域間の中
央の領域、或いは画素領域の周辺部と画素領域間の中央
の領域のうちの何れかの領域に陽極酸化膜を形成し、次
いで該基板を加熱処理して基板と陽極酸化膜の界面に形
成された水銀リッチ層の水銀を基板に導入して該基板の
水銀空孔を上記水銀で埋めて基板の逆伝導型層を形成
し、前記画素領域の中央部に基板と逆伝導型の不純物原
子を導入することを特徴とする。
According to a third aspect of the present invention, the reverse conductivity type layer of the semiconductor substrate is provided by heating the anodic oxide film formed on the semiconductor substrate. According to a fourth aspect of the present invention, there is provided a method of manufacturing a photodetecting element by introducing an impurity of a conductivity type reverse to that of a semiconductor substrate of one conductivity type into a predetermined pattern and providing a pixel region including a pn junction region. In the peripheral area of the pixel area, the central area between the pixel areas, or the central area between the peripheral area of the pixel area and the pixel area, an anodic oxide film is formed, and then the substrate is formed. Is heat-treated to introduce mercury in a mercury-rich layer formed at the interface between the substrate and the anodic oxide film into the substrate to fill the mercury vacancies in the substrate with the mercury to form a reverse conduction type layer of the substrate. It is characterized in that impurity atoms having a conductivity type opposite to that of the substrate are introduced into the central portion of the pixel region.

【0017】また請求項5に示すように、前記画素領域
間の中央の領域に陽極酸化膜を形成後、前記画素領域の
中央部に基板と逆伝導型の不純物原子を導入して画素領
域を形成し、次いで該基板上に保護膜を形成して前記保
護膜に接続用孔を形成後、電極を形成して光検知素子を
形成し、次いで前記光検知素子を形成した基板を加熱処
理して基板と陽極酸化膜の界面に形成された水銀リッチ
層の水銀を基板に導入して該基板の水銀空孔を上記水銀
で埋めて基板の逆伝導型層を形成し、光検知素子の光電
流およびクロストーク量の制御を可能としたことを特徴
とする。
According to a fifth aspect of the present invention, after forming an anodic oxide film in the central region between the pixel regions, an impurity atom having a conductivity type opposite to that of the substrate is introduced into the central region of the pixel region to form the pixel region. Formed, and then a protective film is formed on the substrate to form a connection hole in the protective film, and then an electrode is formed to form a photodetection element, and then the substrate on which the photodetection element is formed is subjected to heat treatment. The mercury in the mercury-rich layer formed at the interface between the substrate and the anodic oxide film is introduced into the substrate to fill the mercury holes in the substrate with the mercury to form the reverse conduction type layer of the substrate. It is characterized in that the current and the amount of crosstalk can be controlled.

【0018】[0018]

【作用】pn接合領域の中央部は従来通りに形成し、リ
ーク電流の発生原因となるpn接合部の周辺部の接合の
濃度勾配を緩くしてGraded Junction にする。このこと
により、n+ 層に発生する暗電流を殆ど増加すること無
く、表面リーク電流が低減できる。pn接合領域の周辺
部をGraded Junction にする方法は、n+ 層の形成領域
の周辺部にイオン注入した後、熱処理して周辺部をGrad
ed Junction にした後、pn接合領域の中央部にイオン
注入する。
The central portion of the pn junction region is formed as usual, and the concentration gradient of the junction at the peripheral portion of the pn junction, which causes the leakage current, is made gentle to form a graded junction. As a result, the surface leak current can be reduced without substantially increasing the dark current generated in the n + layer. How to the peripheral portion of the pn junction region Graded Junction, after ion implantation in the peripheral portion of the formation region of the n + layer, Grad peripheral portion is heat-treated
After the ed junction, ions are implanted in the central part of the pn junction region.

【0019】またpn接合領域の周辺部に陽極酸化膜を
形成後、100 °C 近傍で所定時間、熱処理してn層を形
成し、陽極酸化膜を除去して、不純物原子をイオン注入
する。このように陽極酸化膜を形成すると、陽極酸化膜
とHgCdTe基板表面との境界面には、Hgが多く含まれた水
銀リッチ層が形成されるようになり、この水銀リッチ層
が形成されたHgCdTe基板を熱処理すると、HgがHgCdTe結
晶基板内に拡散し、p型のHgCdTe結晶内のアクセプタと
なるHg空孔を埋めるので、HgCdTe結晶基板の表面層を10
14/cm3のn型層に変換できる。このことは実験により確
認している。
After forming the anodic oxide film around the pn junction region, heat treatment is performed at about 100 ° C. for a predetermined time to form an n layer, the anodic oxide film is removed, and impurity atoms are ion-implanted. When the anodic oxide film is formed in this way, a mercury-rich layer containing a large amount of Hg is formed at the interface between the anodic oxide film and the HgCdTe substrate surface. When the substrate is heat-treated, Hg diffuses into the HgCdTe crystal substrate and fills the Hg holes that serve as acceptors in the p-type HgCdTe crystal.
It can be converted to an n-type layer of 14 / cm 3 . This has been confirmed by experiments.

【0020】なお、p型のHgCdTe結晶をHgガス内で熱処
理することで、Hgをp型のHgCdTe結晶に導入してn層を
形成することも可能であるが、Hgガスの通過を防止する
適当なマスクが存在せず、またHgの拡散量の制御も困難
で実用性に乏しい。更にHgCdTe結晶に形成されたn型層
と、該n型層に接続する電極用の金属膜の接続が良好に
ならないので、現状ではこの方法も実用にはならない。
It is also possible to introduce Hg into the p-type HgCdTe crystal to form the n-layer by heat-treating the p-type HgCdTe crystal in the Hg gas, but to prevent passage of the Hg gas. There is no suitable mask, and it is difficult to control the amount of Hg diffusion. Furthermore, since the connection between the n-type layer formed on the HgCdTe crystal and the metal film for the electrode connected to the n-type layer is not good, this method is not practical at present.

【0021】図7にこのような不純物原子をHgCdTe基板
にイオン注入した後と、更にイオン注入後、拡散した場
合のHgCdTe基板に於けるキャリア濃度と、HgCdTe基板に
該基板の陽極酸化膜を形成後、該基板を熱処理した場合
のHgCdTe基板に於けるキャリア濃度の濃度分布図を示
す。
FIG. 7 shows the carrier concentration in the HgCdTe substrate after ion implantation of such impurity atoms into the HgCdTe substrate, and further after ion implantation and diffusion, and the anodic oxide film of the substrate is formed on the HgCdTe substrate. After that, a concentration distribution diagram of carrier concentration in the HgCdTe substrate when the substrate is heat-treated is shown.

【0022】図の曲線aはp型のHgCdTe基板にボロン
(B+ ) イオンをイオン注入した直後のHgCdTe基板のキ
ャリア濃度分布図、曲線bは前記ボロン(B+ ) イオン
をイオン注入した後、更にHgCdTe基板を熱処理した場合
のHgCdTe基板のキャリア濃度分布図、曲線cはHgCdTe基
板に該基板の陽極酸化膜を形成後、該基板を熱処理した
場合のHgCdTe基板のキャリア濃度分布図であって、dは
HgCdTeのキャリア濃度である。
The curve a in the figure is a carrier concentration distribution chart of the HgCdTe substrate immediately after the boron (B + ) ion is ion-implanted into the p-type HgCdTe substrate, and the curve b is the boron (B + ) ion-implanted after the ion implantation. Further, the carrier concentration distribution diagram of the HgCdTe substrate when the HgCdTe substrate is further heat-treated, the curve c is the carrier concentration distribution diagram of the HgCdTe substrate when the substrate is heat-treated after the anodic oxide film of the substrate is formed on the HgCdTe substrate, d is
It is the carrier concentration of HgCdTe.

【0023】上記したキャリア濃度分布図により、画素
間を囲むように格子状に陽極酸化膜を形成し、フォトダ
イオードを作製後、100 °C で熱処理を行い、該陽極酸
化膜とHgCdTe基板の界面の水銀リッチ層を拡散すること
で、n型の格子状の逆伝導型層が形成できる。
According to the above carrier concentration distribution chart, an anodic oxide film is formed in a grid pattern so as to surround pixels, a photodiode is manufactured, and then heat treatment is performed at 100 ° C. to form an interface between the anodic oxide film and the HgCdTe substrate. By diffusing the mercury-rich layer described above, an n-type lattice-shaped reverse conduction type layer can be formed.

【0024】そしてフォトダイオードの光電流値や、ク
ロストークの発生量が所定の値に到達した時点で、Hgを
拡散する熱処理作業を停止すると、フォトダイオードを
一旦形成した後に、更に形成後のフォトダイオードの特
性を制御することも可能となる。
When the photocurrent value of the photodiode or the amount of crosstalk generated reaches a predetermined value, the heat treatment work for diffusing Hg is stopped. After the photodiode is once formed, the photodiode after the formation is further formed. It is also possible to control the characteristics of the diode.

【0025】このように画素が形成されるpn接合領域
の周辺部のみを、選択的にGraded Junction にすること
で、n型層で発生する暗電流成分を殆ど増加することな
く、かつ表面リーク電流を減少させることが可能とな
る。
By selectively forming the graded junction only in the peripheral portion of the pn junction region where the pixel is formed, the dark current component generated in the n-type layer is hardly increased and the surface leak current is reduced. Can be reduced.

【0026】またpn接合領域の周辺部に格子状に所定
の幅と深さを有する陽極酸化膜を形成してフォトダイオ
ードを一旦形成し、更にこのフォトダイオードを形成し
た後に、基板を熱処理するとフォトダイオードのクロス
トーク量を最適な値に制御することが可能なる。
Further, an anodic oxide film having a predetermined width and depth is formed in a lattice shape on the periphery of the pn junction region to form a photodiode once, and after the photodiode is formed, the substrate is heat treated to form a photo diode. It is possible to control the amount of diode crosstalk to an optimum value.

【0027】[0027]

【実施例】以下、図面を用いて本発明の実施例につき詳
細に説明する。図1(a)と図1(b)は本発明の光検知素子の
第1実施例の断面図と平面図である。図示するように、
p型のHgCdTe基板1に所定のパターンでB+ イオンがイ
オン注入されてn+ 層2が形成され、このn+ 層2の画
素領域の周囲を格子状に囲むように低濃度のn型層11が
形成されている。
Embodiments of the present invention will be described in detail below with reference to the drawings. 1 (a) and 1 (b) are a cross-sectional view and a plan view of a first embodiment of a photo-detecting element of the present invention. As shown,
p-type B + ions in a predetermined pattern HgCdTe substrate 1 is in the n + layer 2 is formed the ion implantation, the low-concentration n-type layer of so as to surround the periphery of the pixel region of the n + layer 2 in a lattice 11 are formed.

【0028】この低濃度のn型層11は、B+ イオンを画
素領域を囲むように格子状に選択的にイオン注入した
後、該HgCdTe基板1を熱拡散して形成しても良く、或い
は、画素領域を囲むように格子状に選択的にHgCdTeの陽
極酸化膜を形成後、HgCdTe基板1を熱処理して、陽極酸
化膜とHgCdTe基板の境界面に形成された水銀リッチ層を
拡散して形成しても良い。
The low-concentration n-type layer 11 may be formed by selectively implanting B + ions in a lattice shape so as to surround the pixel region and then thermally diffusing the HgCdTe substrate 1. After the HgCdTe anodic oxide film is selectively formed in a lattice pattern so as to surround the pixel region, the HgCdTe substrate 1 is heat-treated to diffuse the mercury-rich layer formed on the interface between the anodic oxide film and the HgCdTe substrate. You may form.

【0029】更にHgCdTe基板1上にZnS の表面保護膜3
を設け、この表面保護膜3に接続用孔4を設け、金、或
いはInの電極5を設けて光検知素子を形成する。このよ
うにすると、pn接合の周辺部がGraded Junction にな
っているので、pn接合領域に掛かる電界強度を減少
し、表面リーク電流が減少し暗電流の低下を図ることが
できる。
Further, a surface protective film 3 of ZnS is formed on the HgCdTe substrate 1.
Is provided, a connection hole 4 is provided in the surface protection film 3, and a gold or In electrode 5 is provided to form a photodetection element. By doing so, since the peripheral portion of the pn junction is a graded junction, the electric field strength applied to the pn junction region can be reduced, the surface leakage current can be reduced, and the dark current can be reduced.

【0030】図2(a)と図2(b)は本発明の光検知素子の第
2実施例の断面図と平面図である。本実施例が第1実施
例と異なる点は、n+ 層2の画素領域より所定の間隔を
隔てた状態で、n型層11を設けた点にある。この構造を
採ると、暗電流の発生を防止する効果は第1実施例に比
較して劣るが、画素間に発生するクロストーク現象を防
止する効果はある。
2 (a) and 2 (b) are a sectional view and a plan view of a second embodiment of the photo-detecting element of the present invention. The present embodiment differs from the first embodiment in that the n-type layer 11 is provided in a state of being separated from the pixel region of the n + layer 2 by a predetermined distance. If this structure is adopted, the effect of preventing the generation of dark current is inferior to that of the first embodiment, but there is the effect of preventing the crosstalk phenomenon that occurs between pixels.

【0031】図3(a)と図3(b)は本発明の光検知素子の第
3実施例の断面図と平面図である。本実施例は第1実施
例と第2実施例を組み合わせた構造で、n+ 層2の画素
領域の周辺部と、画素領域より所定の間隔を隔てた位置
にn型層11を設けた構造を採っており、工程数は第1実
施例と第2実施例に比較し多くなるが、暗電流の発生防
止とクロストークの発生防止に最も効果がある。
3 (a) and 3 (b) are a sectional view and a plan view of a third embodiment of the photo-detecting element of the present invention. This embodiment is a combination of the first embodiment and the second embodiment, and has a structure in which the n-type layer 11 is provided in the peripheral portion of the pixel region of the n + layer 2 and at a position separated from the pixel region by a predetermined distance. Although the number of steps is larger than in the first and second embodiments, it is most effective in preventing dark current and crosstalk.

【0032】次に本発明の光検知素子の製造工程につい
て述べる。第1実施例として図4(a)に示すように、レジ
スト膜(図示せず)をマスクとして用いて、p 型のHgCd
Te基板1のpn接合の形成予定領域の周辺部にB+ イオ
ンをイオン注入してn型のイオン注入層12を形成する。
Next, the manufacturing process of the photo-detecting element of the present invention will be described. As a first embodiment, as shown in FIG. 4A, a p-type HgCd film is formed by using a resist film (not shown) as a mask.
B + ions are ion-implanted into the peripheral portion of the region where the pn junction is to be formed on the Te substrate 1 to form an n-type ion implantation layer 12.

【0033】続いて、図4(b)に示すように、このイオン
注入層12を有するHgCdTe基板1を200 ℃の温度で1時間
熱処理し、pn接合の形成予定領域の周辺部に所定の緩
やかなキャリア濃度勾配を有するn型層11(Graded Jun
ction )を形成する。
Subsequently, as shown in FIG. 4 (b), the HgCdTe substrate 1 having the ion-implanted layer 12 is heat-treated at a temperature of 200 ° C. for 1 hour, and a predetermined grading is formed on the peripheral portion of the region where the pn junction is to be formed. N-type layer 11 (Graded Junction)
ction) is formed.

【0034】その後、図4(c)に示すように、レジスト膜
( 図示せず) をマスクとしてpn接合の形成予定領域に
矢印に示すように、B+ イオンをイオン注入し、更に熱
処理して注入されたイオン注入層をn+ 層2に形成す
る。
Then, as shown in FIG. 4 (c), a resist film is formed.
As shown by an arrow, B + ions are ion-implanted in a region where a pn junction is to be formed using (not shown) as a mask, and further heat treatment is performed to form an ion-implanted layer into the n + layer 2.

【0035】最後に、図4(d)に示す如くp 型のHgCdTe基
板1表面にZnS 膜の表面保護膜3を蒸着により形成後、
該表面保護膜3に接続用孔4を形成後、In、或いは金を
蒸着し、該蒸着膜をリフトオフ法等を用いて所定のパタ
ーンに形成して電極5を形成する。
Finally, as shown in FIG. 4 (d), after the surface protective film 3 of ZnS film is formed on the surface of the p-type HgCdTe substrate 1 by vapor deposition,
After forming the connection hole 4 in the surface protective film 3, In or gold is vapor-deposited, and the vapor-deposited film is formed into a predetermined pattern by a lift-off method or the like to form the electrode 5.

【0036】第2実施例としては、図5(a)に示すよう
に、p 型のHgCdTe基板1上の全面に該基板の陽極酸化膜
13を形成後、該陽極酸化膜13上にpn接合形成予定領域
以外の部分にレジスト膜14を形成し、該レジスト膜14を
マスクとして弗化水素酸と弗化アンモニウムの混合液で
陽極酸化膜13を選択的にエッチングして除去し、更にレ
ジスト膜14を除去する。この状態を図5(b)に示す。
As a second embodiment, as shown in FIG. 5A, the anodic oxide film of the p-type HgCdTe substrate 1 is formed on the entire surface of the substrate.
After forming 13, the resist film 14 is formed on the anodic oxide film 13 in a region other than the region where the pn junction is to be formed, and the anodic oxide film is formed by using the resist film 14 as a mask and a mixed solution of hydrofluoric acid and ammonium fluoride. 13 is selectively etched and removed, and further the resist film 14 is removed. This state is shown in FIG. 5 (b).

【0037】次に、図5(c)に示すように、HgCdTe基板1
を所定時間熱処理し、陽極酸化膜13とHgCdTe基板1の界
面に形成されたHgリッチ層15を拡散し、図5(d)に示すよ
うにn型層11を形成することで、pn接合の形成予定領
域の周辺部に所定の緩やかなキャリア濃度勾配を有する
Graded Junction を形成して、その後陽極酸化膜13をエ
ッチング除去する。
Next, as shown in FIG. 5 (c), the HgCdTe substrate 1
Is heat-treated for a predetermined time to diffuse the Hg-rich layer 15 formed at the interface between the anodic oxide film 13 and the HgCdTe substrate 1 to form the n-type layer 11 as shown in FIG. Has a certain gradual carrier concentration gradient in the periphery of the planned formation region
A graded junction is formed, and then the anodic oxide film 13 is removed by etching.

【0038】そして、図5(e)に示すように、レジスト膜
(図示せず)をマスクとしてpn接合の形成予定領域に
+ イオンを矢印のようにイオン注入し、更に熱処理し
て注入されたイオン注入層をn+ 層2に形成する。
Then, as shown in FIG. 5 (e), B + ions are ion-implanted in a region where a pn junction is to be formed as shown by an arrow using a resist film (not shown) as a mask, and further heat-treated and implanted. The ion implantation layer is formed on the n + layer 2.

【0039】第3実施例としては、図6(a)に示すよう
に、p 型のHgCdTe基板1の全面に該基板の陽極酸化膜13
を形成後、レジスト膜14をマスクとして画素間領域の以
外の領域の陽極酸化膜13を前記したエッチング液で選択
エッチングする。
As a third embodiment, as shown in FIG. 6A, the anodic oxide film 13 of the p-type HgCdTe substrate 1 is formed on the entire surface of the substrate 1.
After the formation, the resist film 14 is used as a mask to selectively etch the anodic oxide film 13 in the region other than the inter-pixel region with the above-described etching solution.

【0040】その後、図6(b)に示すように、陽極酸化膜
13を残したまま、画素形成予定領域にB+ イオンを矢印
のようにイオン注入してn+ 層2を形成する。この陽極
酸化膜13とHgCdTe基板1の境界面にはHgリッチ層15が形
成されている。
Then, as shown in FIG. 6 (b), the anodic oxide film is formed.
While leaving 13, the B + ions are ion-implanted into the pixel formation planned region as shown by the arrow to form the n + layer 2. A Hg rich layer 15 is formed on the boundary surface between the anodic oxide film 13 and the HgCdTe substrate 1.

【0041】続いて、図6(c)に示すようにHgCdTe基板1
表面にZnS 膜の表面保護膜3を蒸着により形成する。次
に、図6(d)に示すように、該表面保護膜3に接続用孔4
を形成後、In、或いは金を蒸着し、該蒸着膜をリフトオ
フ法等を用いて所定のパターンに形成して電極5を設け
てフォトダイオードを形成する。
Subsequently, as shown in FIG. 6C, the HgCdTe substrate 1
A surface protective film 3 of ZnS film is formed on the surface by vapor deposition. Next, as shown in FIG. 6 (d), the surface protection film 3 is provided with a connecting hole 4
After formation of In, gold or In is vapor-deposited, the vapor-deposited film is formed into a predetermined pattern by a lift-off method or the like, and the electrode 5 is provided to form a photodiode.

【0042】そして、図6(e)に示すように、このように
形成したフォトダイオードを有するHgCdTe基板1の熱処
理温度、熱処理時間を制御して熱処理し、前記したHgリ
ッチ層15のHgを拡散してn型層11に形成することによ
り、所定の光信号量、クロストーク発生量を有する光検
知素子を形成する。
Then, as shown in FIG. 6E, the HgCdTe substrate 1 having the photodiode thus formed is heat-treated by controlling the heat treatment temperature and the heat treatment time to diffuse the Hg of the Hg rich layer 15 described above. Then, the n-type layer 11 is formed to form a photodetector having a predetermined optical signal amount and a predetermined crosstalk generation amount.

【0043】[0043]

【発明の効果】以上述べたように、本発明の光検知素
子、およびその製造方法によると、n型層に発生する暗
電流は、従来の方法で形成した場合と同様で、表面リー
ク電流の発生の少ない光検知素子が得られる。また画素
間に陽極酸化膜を形成することで、光検知素子形成後に
クロストーク発生量を所定の値に制御できる。
As described above, according to the photodetector of the present invention and the manufacturing method thereof, the dark current generated in the n-type layer is the same as in the case of the conventional method, and the dark current It is possible to obtain a light-sensing element with less generation. Further, by forming the anodic oxide film between the pixels, the amount of crosstalk generated can be controlled to a predetermined value after the photodetector element is formed.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の光検知素子の第1実施例の断面図と
平面図である。
FIG. 1 is a cross-sectional view and a plan view of a first embodiment of a photo-detecting element of the present invention.

【図2】 本発明の光検知素子の第2実施例の断面図と
平面図である。
FIG. 2 is a cross-sectional view and a plan view of a second embodiment of the photo-detecting element of the present invention.

【図3】 本発明の光検知素子の第3実施例の断面図と
平面図である。
FIG. 3 is a cross-sectional view and a plan view of a third embodiment of the photo-detecting element of the present invention.

【図4】 本発明の光検知素子の第1実施例の製造方法
を示す断面図である。
FIG. 4 is a cross-sectional view showing the manufacturing method of the first embodiment of the photodetecting element of the present invention.

【図5】 本発明の光検知素子の第2実施例の製造方法
を示す断面図である。
FIG. 5 is a cross-sectional view showing the manufacturing method of the second embodiment of the light-sensing element of the present invention.

【図6】 本発明の光検知素子の第3実施例の製造方法
を示す断面図である。
FIG. 6 is a cross-sectional view showing the manufacturing method of the third embodiment of the photodetecting element of the present invention.

【図7】 本発明のn型層のHgCdTe基板に於ける濃度分
布図である。
FIG. 7 is a concentration distribution diagram of an n-type layer HgCdTe substrate of the present invention.

【図8】 従来の光検知素子の製造方法を示す断面図と
平面図である。
8A and 8B are a cross-sectional view and a plan view showing a conventional method for manufacturing a photodetecting element.

【図9】 従来の光検知素子の不都合を示す説明図であ
る。
FIG. 9 is an explanatory view showing the inconvenience of the conventional photodetector.

【符号の説明】[Explanation of symbols]

1 HgCdTe基板 2 n+ 層 3 表面保護膜 4 接続用孔 5 電極 11 n型層 12 イオン注入層 13 陽極酸化膜 14 レジスト膜 15 Hgリッチ層1 HgCdTe Substrate 2 n + Layer 3 Surface Protective Film 4 Connection Hole 5 Electrode 11 n-type Layer 12 Ion Implantation Layer 13 Anodized Film 14 Resist Film 15 Hg Rich Layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 渡邊 芳夫 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshio Watanabe 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 一伝導型の半導体基板(1) に該基板と逆
伝導型の不純物を所定のパターンに導入し、pn接合領
域よりなる画素領域(2) を設けた光検知素子に於いて、 前記画素領域(2) の不純物キャリア濃度分布を、前記p
n接合領域の中央部では急峻とし、前記pn接合領域の
周辺部では緩やかにしたことを特徴とする光検知素子。
1. A photodetection device comprising a one-conduction type semiconductor substrate (1) having a pixel pattern (2) consisting of a pn junction region, which is obtained by introducing impurities of a reverse-conduction type to the substrate in a predetermined pattern. , The impurity carrier concentration distribution of the pixel region (2) is
A photodetection element, characterized in that the central part of the n-junction region is made steep and the peripheral part of the pn-junction region is made gentle.
【請求項2】 請求項1記載の画素領域(2) の周辺部、
画素領域(2) 間の中央の領域、或いは画素領域(2) の周
辺部と画素領域間の中央の領域の何れかに幅、或いは深
さが制御可能な前記半導体基板(1) の伝導型とは異なる
逆伝導型層(11)を設けたことを特徴とする光検知素子。
2. A peripheral portion of the pixel region (2) according to claim 1,
The conductivity type of the semiconductor substrate (1) whose width or depth can be controlled either in the central region between the pixel regions (2) or in the central region between the peripheral region of the pixel region (2) and the pixel region A photo-detecting element, which is provided with a reverse conductivity type layer (11) different from the above.
【請求項3】 請求項2に記載の逆伝導型層(11)が、半
導体基板に逆導電型の不純物を導入した拡散層、或いは
該半導体基板上に形成された陽極酸化膜(13)を加熱処理
して設けていることを特徴とする光検知素子。
3. The reverse conductivity type layer (11) according to claim 2, comprising a diffusion layer in which impurities of reverse conductivity type are introduced into a semiconductor substrate, or an anodic oxide film (13) formed on the semiconductor substrate. A photo-detecting element, which is provided by being heat-treated.
【請求項4】 一伝導型の半導体基板(1) に該基板と逆
伝導型の不純物を所定のパターンに導入し、pn接合領
域よりなる画素領域(2) を設けて光検知素子を製造する
方法に於いて、 前記画素領域(2) の周辺部、画素領域(2) の間の中央の
領域、或いは画素領域(2) の周辺部と画素領域(2) 間の
中央の領域のうちの何れかの領域に陽極酸化膜(13)を形
成し、 次いで半導体基板(1) を加熱処理して半導体基板(1) と
陽極酸化膜(13)の界面に形成された水銀リッチ層(15)の
水銀を半導体基板(1) に導入して該半導体基板(1) の水
銀空孔を上記水銀で埋めて半導体基板(1) の逆伝導型層
(11)を形成し、 前記画素領域(2) の中央部に半導体基板(1) と逆伝導型
の不純物原子を導入することを特徴とする光検知素子の
製造方法。
4. A photo-sensing element is manufactured by introducing an impurity of a conductivity type opposite to that of a semiconductor substrate (1) of one conductivity type into a predetermined pattern and providing a pixel region (2) consisting of a pn junction region. In the method, in the peripheral area of the pixel area (2), the central area between the pixel areas (2), or the central area between the peripheral area of the pixel area (2) and the pixel area (2). A anodic oxide film (13) is formed on any region, and then the semiconductor substrate (1) is heat treated to form a mercury-rich layer (15) formed at the interface between the semiconductor substrate (1) and the anodic oxide film (13). Of the reverse conductivity type layer of the semiconductor substrate (1) by introducing mercury of the above into the semiconductor substrate (1) and filling the mercury holes of the semiconductor substrate (1) with the above mercury.
(11) is formed, and an impurity atom of a conductivity type opposite to that of the semiconductor substrate (1) is introduced into the central portion of the pixel region (2).
【請求項5】 一伝導型の半導体基板(1) に該半導体基
板(1) と逆伝導型の不純物を所定のパターンに導入し、
pn接合領域よりなる画素領域(2) を設けて光検知素子
を製造する方法に於いて、 前記画素領域(2) 間の中央の領域に陽極酸化膜(13)を形
成後、前記画素領域(2) の中央部に半導体基板(1) と逆
伝導型の不純物原子を導入して画素領域(2) を形成し、 次いで該半導体基板(1) 上に表面保護膜(3) を形成して
前記表面保護膜(3) に接続用孔(4) を形成後、電極(5)
を形成して光検知素子を形成し、 次いで前記光検知素子を形成した半導体基板(1) を加熱
処理して該半導体基板(1) と陽極酸化膜(13)の界面に形
成された水銀リッチ層(15)の水銀を半導体基板(1) に導
入して該半導体基板(1) の水銀空孔を上記水銀リッチ層
(15)の水銀で埋めて半導体基板(1) 逆伝導型層(11)を形
成し、光検知素子の光電流およびクロストーク量の制御
を可能としたことを特徴とする光検知素子の製造方法。
5. An impurity of opposite conductivity type to the semiconductor substrate (1) is introduced into a predetermined pattern in the one conductivity type semiconductor substrate (1),
In a method of manufacturing a photodetector by providing a pixel region (2) consisting of a pn junction region, an anodic oxide film (13) is formed in a central region between the pixel regions (2), and then the pixel region (2) is formed. A pixel region (2) is formed by introducing impurity atoms of the opposite conductivity type to the semiconductor substrate (1) in the central part of 2), and then a surface protective film (3) is formed on the semiconductor substrate (1). After forming the connection hole (4) in the surface protective film (3), the electrode (5)
To form a photo-sensing element, and then heat-treating the semiconductor substrate (1) on which the photo-sensing element is formed to form a mercury-rich layer formed at the interface between the semiconductor substrate (1) and the anodized film (13). The mercury in the layer (15) is introduced into the semiconductor substrate (1) so that the mercury vacancies in the semiconductor substrate (1) are removed from the mercury-rich layer.
Manufacture of a photo-detecting element characterized in that the semiconductor substrate (1) is filled with mercury of (15) to form a reverse-conduction type layer (11), and the photocurrent and crosstalk amount of the photo-detecting element can be controlled. Method.
JP5020450A 1993-02-09 1993-02-09 Photodetector element and manufacture thereof Withdrawn JPH06237005A (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
JP5020450A JPH06237005A (en) 1993-02-09 1993-02-09 Photodetector element and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH06237005A true JPH06237005A (en) 1994-08-23

Family

ID=12027408

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH06237005A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173487A (en) * 2004-12-17 2006-06-29 Omron Corp Imaging device
JP2007311664A (en) * 2006-05-19 2007-11-29 Sharp Corp Color sensor, manufacturing method therefor, sensor, and electronic equipment
CN105762209A (en) * 2016-04-15 2016-07-13 中国科学院上海技术物理研究所 Low-damage buried mercury cadmium telluride detector chip
WO2023061235A1 (en) * 2021-10-14 2023-04-20 南京大学 New silicon-carbide-based lateral pn junction extreme ultraviolet detector based on selected area ion implantation, and preparation method therefor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173487A (en) * 2004-12-17 2006-06-29 Omron Corp Imaging device
JP2007311664A (en) * 2006-05-19 2007-11-29 Sharp Corp Color sensor, manufacturing method therefor, sensor, and electronic equipment
US7605354B2 (en) 2006-05-19 2009-10-20 Sharp Kabushiki Kaisha Color sensor, production method thereof, sensor, and electronics device
CN105762209A (en) * 2016-04-15 2016-07-13 中国科学院上海技术物理研究所 Low-damage buried mercury cadmium telluride detector chip
WO2023061235A1 (en) * 2021-10-14 2023-04-20 南京大学 New silicon-carbide-based lateral pn junction extreme ultraviolet detector based on selected area ion implantation, and preparation method therefor

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