JPH06236449A - Analog multiplier - Google Patents

Abstract

PURPOSE:To provide an analog multiplier for high frequency which can reduce the leakage of carrier signals. CONSTITUTION:An analog multiplier functions as a Gilbert cell which constructs a 1st differential circuit with pairs of transistors TRs 5 and 7 and TRs 6 and 8, a 2nd differential circuit with a pair of TRs 1 and 2, and a 3rd differential circuit with a pair of TRs 3 and 4 respectively. Then the multiplier supplies a 1st high frequency signal between the input terminals 21 and 22 and a 2nd high frequency signal between the input terminals 23 and 24 and generates a multiplication signal between the output terminals 25 and 26 respectively. The collectors of TRs 5 and 7 are connected to the emitters of TRs 1 and 2 respectively, and the collectors of TRs 6 and 8 are connected to the emitters of TRs 3 and 4 respectively. Furthermore a resistor 13 and a resistor 14 are connected between the emitters of TRs 1 and 2 and the emitters of TRs 3 and 4 respectively as the feedback resistors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Gilbert cell type analog multiplier, and more particularly to an analog multiplier adapted to a high frequency band such as microwaves.

[0002]

2. Description of the Related Art An example of an analog multiplier (multiplier or double balanced modulator) called Gilbert cell is disclosed in Japanese Patent Publication (Showa 48-20932, date of publication: 1973).
25). This analog multiplier
The first high-frequency signal of the balanced form and the second high-frequency signal are multiplied, and the multiplication result of the two high-frequency signals is produced at the output terminal in the balanced form. In other words, this analog multiplier modulates a second high frequency signal (modulated signal = carrier signal) with a first high frequency signal (eg baseband signal = BB signal) to produce a balanced modulation signal. .

An improvement means for using this analog multiplier in a high frequency band such as microwave is disclosed in another patent publication (Patent Document 3).
-49206, date of publication: July 26, 1991). In this analog multiplier, high frequency characteristics are improved by monolithically integrating the respective constituent elements.

A conventional analog multiplier will be described below with reference to the drawings.

FIG. 3 is a circuit diagram of a conventional analog multiplier.

In this analog multiplier, the six transistors shown in the figure form three differential circuits. That is, in the first differential circuit, the emitters of the two transistors 5 and 6 are connected to each other by the resistors 15 and 16, and the resistors 15 and 16 are connected.
Is grounded through a common constant current source 31, and the balanced first high frequency signal received between the input terminals 21 and 22 is applied to the bases of the transistors 5 and 6. The second differential circuit connects the emitters of the two transistors 1 and 2 in common and connects them to the collector of the transistor 5, and receives the second differential circuit of the balanced type received between the input terminals 23 and 24.
The high frequency signal at the bases of transistors 1 and 2. The third differential circuit connects the emitters of the two transistors 3 and 4 in common and connects them to the collector of the transistor 6, and outputs the second high frequency signal to the transistor 3
And 4 bases.

In this analog multiplier, a connection point 25 where collectors of one of the transistors (transistors 1 and 3) of the second and third differential circuits are commonly connected is passed through a resistor 27 and the other transistor is connected. Connection point 2 where collectors of (transistors 2 and 4) are commonly connected
6 are connected together to the power supply terminal 20 through the resistor 28. These connection points 25 and 26 are also output terminals for producing a balanced modulation signal in which the second high-frequency signal is modulated by the first high-frequency signal. A predetermined bias (offset voltage) is supplied to the input terminals 21 to 24 from a bias voltage supply circuit (not shown).

Next, the operation of the analog multiplier of FIG. 3 will be described. When a first high frequency signal is applied between the input terminals 21 and 22, a high frequency signal of opposite phase is generated at the collectors of the transistors 5 and 6. Here, the input terminals 23 and 24
When the second high frequency signal applied between and is in positive phase (when the voltage of the input terminal 23 is higher than the voltage of the input terminal 24), the internal resistance of the transistors 2 and 3 becomes high and the transistor 6 The collector output power of the output terminal 26
Then, the collector output power of the transistor 5 is generated at the output terminal 25. On the contrary, when the second high-frequency signal has a reverse phase (when the voltage of the input terminal 24 is higher than the voltage of the input terminal 23), the internal resistance of the transistors 2 and 3 becomes low, so that the transistor 6 Collector output power is produced at output terminal 25 and collector output power of transistor 5 is produced at output terminal 26. Therefore, when the second high frequency signal is in positive phase, the first high frequency signal is in positive phase and is output between the output terminals 25 and 26, and when the second high frequency signal is in antiphase, the first high frequency signal is in high phase. The frequency signal is inverted and output.

When the second high frequency signal has a voltage of 0, the internal resistances of the transistors 1, 2, 3 and 4 are substantially equal, so that the bridge circuit formed by these four internal resistances is balanced. The first high frequency signal is not output between the output terminals 25 and 26. Therefore, when either one of the first and second high frequency signals has a zero voltage, the output between the output terminals 25 and 26 necessarily becomes zero, thereby forming a double balanced modulator.

FIGS. 4 and 5 are signal waveform diagrams for explaining the operation of the analog multiplier of FIG. The operation of this analog multiplier will be described below with reference to FIGS.

The analog multiplier of FIG. 3 applies an ideal rectangular wave having a repetition period Tr as a second high frequency signal (hereinafter also referred to as a carrier signal) between the input terminals 23 and 24, and the input terminal 21 For the sake of simplicity of explanation, a DC potential with a terminal voltage of 0 V is applied between points 22 and 22. In the ideal state, this analog multiplier produces a collector current I4 of transistor 4 and a collector current I2 of transistor 2 as shown in FIG. The current I28 flowing through the resistor 28 and generated at the output terminal 26 is I2 + I4. Now, if the constants of the respective components forming the pair of the analog multiplier are balanced, the current I28 maintains a constant value,
The analog multiplier does not leak the carrier signal at the output terminal 26. However, when the frequency of the carrier signal becomes high, particularly when microwaves of 1 GHz or more are generated, variations in the transistors 1 to 6 and imbalance of parasitic capacitances of wirings to the electrode connection parts of these transistors 1 to 6 are lost. Further, the imbalance of the second high frequency signal becomes large, and this analog multiplier causes overshoot of the carrier signal in the currents I4 and I2, resulting in leakage of the carrier signal in the output terminal 26 (25). Occurs.

The signal waveform diagram of FIG. 5 is obtained by comparing the analog multiplier of FIG. 3 with the SPICE circuit simulation method (for example, M
icrowave SPICE User's Guid
eVersion3.0 Nov. 1990, this SPI
CE simulations were obtained by solving steady state and transient linear and non-linear circuits and performing AC and DC analysis). This analog multiplier includes silicon bipolar transistors 1 to 6 having a cutoff frequency and a maximum oscillation frequency of 16 GHz and a rated collector current of 5.3 mA, and a current of 8 mA (I
5 + I6) constant current source 31, resistors 27 and 12 with a resistance of 200 ohms, resistor 1 with a resistance of 60 ohms
5 and 16 are used, a DC potential of 0 V is applied between the input terminals 21 and 22, and a frequency of 2 GHz is applied between the input terminals 23 and 24.
The second high frequency signal of (switching cycle Tr = 500 ps) is applied. This signal waveform has currents I2 and I4.
Overshoot occurs, and as a result, a current I28 that is not a constant value is generated at the output terminal 26. The carrier signal leak due to the current I28 is caused by the output terminals 25 and 26.
It is -47.0 dBm between.

[0013]

The above-mentioned analog multiplier has the above-mentioned first and second high-frequency signals in order to suppress the leakage of the carrier signal (second high-frequency signal) to the output terminal. The offset voltage applied to the input terminal of was changed. However, adjustment of this offset voltage
There is a drawback that not only the structure of the bias voltage supply circuit is complicated but also a great amount of adjustment time is required.

The effect of adjusting the offset voltage is as follows.
If the temperature and frequency are out of a certain range, it is difficult to keep the balance of the circuit parameters due to the temperature dependence of the transistor characteristics.

Furthermore, when this analog multiplier is integrated into an integrated circuit, the bias voltage supply circuit is provided outside the integrated circuit to adjust the voltage, and the effect of miniaturization by integration is achieved. Will be killed.

[0016]

SUMMARY OF THE INVENTION An analog multiplier of the present invention receives a first high frequency signal between two terminals, a first input terminal, and a second high frequency signal between two terminals. A second input terminal, an output terminal for generating a multiplication signal obtained by multiplying the first and second high frequency signals between the two terminals, and each base is connected to one of the first input terminals, respectively. A first differential circuit including first and second transistor circuits, each emitter of which receives a current supply from a common constant current source; and an emitter of which receives a current supply from the collector of the first transistor circuit. A first transistor whose collector is connected to one of the output terminals and an emitter are supplied with current from the collector of the first transistor circuit, and a collector is connected to another one of the output terminals. The second includes a transistor each respective bases of the first and second transistors that are continued respectively connected to one of said second input terminal 2
Differential circuit, a third transistor whose emitter is supplied with current from the collector of the second transistor circuit and whose collector is connected to one of the output terminals, and whose emitter is the collector of the second transistor circuit. A fourth transistor having a collector connected to another one of the output terminals and having a collector connected to another one of the output terminals, each of the bases of the third and fourth transistors being one of the second output terminals. And a third differential circuit connected to each of the Gilbert cell type analog multipliers, wherein the first transistor circuit includes fifth and sixth transistors having bases and emitters coupled to each other, respectively. The second transistor circuit is
A seventh and an eighth transistor having a base and an emitter coupled to each other, wherein the emitter of the first transistor and the collector of the fifth transistor are
The emitter of the second transistor and the collector of the sixth transistor, the emitter of the third transistor and the collector of the seventh transistor, the emitter of the fourth transistor and the eighth transistor, respectively. Collectors are respectively connected, and further, the first
And the emitters of the second transistors are connected via a first resistor, and the emitters of the third and fourth transistors are connected via a second resistor.

One of the analog multipliers is the first
A first input terminal for receiving a high frequency signal, a second input terminal for receiving a second high frequency signal between two terminals, and a multiplication signal obtained by multiplying the first and second high frequency signals by 2 An output terminal generated between two terminals, an emitter commonly connected to receive a current from a constant current source, a base commonly connected to one of the first input terminals, and an emitter Third and fourth transistors that are commonly connected and that are supplied with current from the constant current source and have their bases commonly connected to another one of the first input terminals;
The emitter is connected to the collector of the first transistor, the collector is connected to the power supply through the first resistor, and is connected to one of the output terminals, and the base is the second terminal.
A fifth transistor connected to one of the input terminals of
The emitter is connected to the collector of the second transistor, the collector is connected to the power supply through a second resistor and is connected to another one of the output terminals, and the base is connected to the other of the second input terminals. A sixth transistor connected to one of the above, an emitter connected to the collector of the fourth transistor, a collector connected to the collector of the fifth transistor, and a base connected to the base of the sixth transistor. An eighth transistor having an emitter connected to the collector of the fourth transistor, a collector commonly connected to the collector of the sixth transistor, and a base commonly connected to the base of the fifth transistor. A transistor, the emitters of the fifth and sixth transistors are connected via a third resistor, and And the emitter of the eighth transistor being connected through a fourth resistor.

[0018]

The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

This analog multiplier further adds transistors 7 and 8 to the first differential circuit in the Gilbert cell type analog multiplier of FIG. That is, the emitter and base of the transistor 7 are
Are commonly connected to the emitter and the base, respectively. Further, the collector of the transistor 5 is connected only to the emitter of the transistor 1 in the second differential circuit, and instead, the collector of the transistor 7 is connected to the emitter of the transistor 2. Similarly, the emitter and the base of the transistor 8 are commonly connected to the emitter and the base of the transistor 6, respectively, and the collector of the transistor 6 is connected only to the emitter of the transistor 3.
Is connected to the emitter of the transistor 4.
Also, the emitter of the transistor 1 and the emitter of the transistor 2 are connected via the resistor 13, and the emitter of the transistor 3 and the emitter of the transistor 4 are connected to the resistor 1.
4 are connected.

The resistors 11 and 12 have their resistances changed in order to equalize the levels of the balanced multiplication signals generated between the output terminals 25 and 26. However, the resistors 27 and 27 of FIG. 28 respectively.

In this analog multiplier, for convenience of explanation,
When the voltage of the first high-frequency signal (hereinafter, also referred to as BB signal) is 0V (since the leak amount of the carrier signal does not change regardless of the voltage of the BB signal), the input terminal 23
Current I6 flowing through the transistor 6 when the second high frequency signal (carrier signal) applied between
Flows through the resistor 14 to the transistor 4. Therefore, the emitter potential of the transistor 4 increases as the carrier signal applied to the input terminals 23 and 24 changes from the negative phase to the positive phase, and the negative feedback operation is performed so as to keep the base-emitter voltage of the transistor 4 constant. A rapid increase in the current I4 of the transistor 4 is suppressed. That is, when the carrier signal changes from the reverse phase to the positive phase, the output current I4 changes smoothly without abrupt change. When the carrier signal changes from the positive phase to the negative phase, the transistor 2
The current I2 flowing through changes as described above. As a result,
The current I12 generated between the output terminals 25 and 26 undergoes a smooth change, and the overshoot component which causes the carrier signal leakage is reduced.

If the resistance values of the resistors 13 and 14 for negative feedback are too small, the effect of reducing the overshoot of the currents I2 and I4 (and the currents I1 and I3 flowing through the transistors 1 and 3) is lost, and conversely it is large. If it is too much, the transistors 5 to 8 will be saturated and the desired characteristics cannot be obtained. Therefore, the resistance values of the resistors 13 and 14 are appropriately determined in consideration of the parameters of the transistors 1 to 8 and the level of the multiplication signal.

FIG. 2 is a signal waveform diagram of the analog multiplier of FIG.

This signal waveform diagram was also obtained by the above SPICE simulation. Also in this analog multiplier, the characteristic parameters of the transistors 1 to 8, the carrier signal waveform and the BB signal waveform are the same as those of the multiplier of FIG. However, the resistance value of each of the resistors 11 and 12 is set to 140 ohms. Further, the resistance value of each of the resistors 13 and 14 is set to 40 ohms. Here, the carrier signal is obtained from an unbalance / balance conversion circuit (not shown), and the multiplication signal is supplied to a circuit equivalent to an emitter follower (not shown). Input terminal 2
When it is necessary to supply the BB signal between 1 and 22, this supply is performed using a balance circuit.

The overshoot of currents I2 and I4 in FIG. 2 is clearly reduced compared to that of currents I2 and I4 in FIG. In fact, the carrier signal leak between the output terminals 25 and 26 in the simulation is -56.0 dBm, which is about 10 compared with the conventional example.
dB improvements have been made.

When the analog multiplier described above is integrated on a semiconductor substrate such as syrincon or gallium arsenide, it is sufficiently practical even at high frequencies such as microwave bands due to the effect of miniaturization and uniform characteristics. This was confirmed by the above simulation.

As described above, according to the present invention, in the Gilbert-type cell type analog multiplier, two differential transistors forming the first differential circuit are connected in parallel, and the collectors of the respective transistors are connected. Second each
Since the emitters of the differential transistors of the second and third differential circuits are connected to each other by emitters of the differential transistors of the second and third differential circuits, respectively, the resistors of the second and third differential circuits are connected to each other. The output current of the differential circuit of No. 3 can be suppressed from overshooting, and therefore carrier signal leakage can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an analog multiplier according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining the embodiment of FIG.

FIG. 3 is a circuit diagram of a conventional analog multiplier.

FIG. 4 is one of signal waveform diagrams for explaining the operation of the analog multiplier of FIG.

5 is another diagram of signal waveforms for explaining the operation of the analog multiplier of FIG.

[Explanation of symbols]

 1-8 Transistor 11-16,27,28 Resistor 20 Power supply 21-24 Input terminal 25,26 Output terminal 31 Constant current source

Claims (4)

[Claims] 1. A first input terminal for receiving a first high frequency signal between two terminals, a second input terminal for receiving a second high frequency signal between two terminals, and the first and first An output terminal for generating a multiplication signal obtained by multiplying two high frequency signals between two terminals, and each base is connected to one of the first input terminals, and each emitter is connected to a common constant current source. A first differential circuit including first and second transistor circuits respectively receiving current supply; an emitter receiving current supply from a collector of the first transistor circuit and a collector connected to one of the output terminals A first transistor and a second transistor whose emitter is supplied with current from the collector of said first transistor circuit and whose collector is connected to another one of said output terminals. A second differential circuit in which each of the bases of the first and second transistors is connected to one of the second input terminals, and an emitter receives current from the collector of the second transistor circuit. And a collector connected to one of the output terminals, respectively.
And a fourth transistor whose emitter is supplied with current from the collector of the second transistor circuit and whose collector is connected to another one of the output terminals. The bases of the third and fourth transistors And a third differential circuit each connected to one of the second output terminals, the Gilbert cell type analog multiplier, wherein the first transistor circuit connects the base and the emitter to each other. Fifth and sixth transistors coupled to each other, the second transistor circuit includes seventh and eighth transistors having respective bases and emitters coupled to each other, and the emitter of the first transistor and the fifth transistor The collector of the second transistor is the emitter of the second transistor and the sixth transistor. Is connected to the emitter of the third transistor and the collector of the seventh transistor, and the emitter of the fourth transistor is connected to the collector of the eighth transistor, respectively. And the emitters of the second transistor are connected via a first resistor, and the third and fourth
An analog multiplier in which the emitter of the transistor is connected through a second resistor. 2. The resistance value of the first resistor and the resistance value of the second resistor are substantially equal to each other.
The described analog multiplier. 3. The analog multiplier according to claim 1, wherein the analog multiplier is integrated on a semiconductor substrate. 4. A first input terminal for receiving a first high frequency signal, a second input terminal for receiving a second high frequency signal between two terminals, and the first and second high frequency signals. An output terminal that produces a multiplication signal obtained by multiplying by
First and second transistors having emitters commonly connected and receiving current supply from a constant current source and having bases commonly connected to one of the first input terminals; and emitters commonly connected to the constant current source. The base receives the current supply and is the first
Third and fourth commonly connected to another one of the input terminals of
And a collector of the first transistor is connected to the collector of the first transistor, the collector is connected to the power source through the first resistor, and is connected to one of the output terminals, and the base is connected to the second input terminal. Fifth connected to one
And a collector of the second transistor, the emitter of which is connected to the collector of the second transistor, the collector of which is connected to the power supply through a second resistor and the other of which is connected to the base of the second terminal. A sixth transistor connected to another one of the input terminals, an emitter connected to the collector of the fourth transistor, and a collector connected to the fifth transistor.
A seventh transistor having a base commonly connected to the collector of the transistor and a base commonly connected to the base of the sixth transistor; and an emitter connected to the collector of the fourth transistor and a collector connected to the collector of the sixth transistor. An eighth transistor having a common connection and a base commonly connected to the base of the fifth transistor, wherein the emitters of the fifth and sixth transistors are connected through a third resistor and the seventh transistor is connected. And an emitter of the eighth transistor connected via a fourth resistor.