JPH06232853A - Bidirectional cable communication system - Google Patents

Abstract

PURPOSE:To communicate information through a single cable transmission line in the system for performing bidirectional communication through cable transmission lines respectively arranged on the sending side and the returning side. CONSTITUTION:One cable transmission line 1 allocates time to a sending block and a returning block, the channel of the sending block performs time division multiplex arrangement, and the channel of the returning block also performs time division multiplex arrangement. Further, a synchronizing pulse to be inserted to the sending block and a synchronizing pulse to be inserted to the returning block are formed as synchronizing pulses to be distinguished and detected, and the final channel of the returning block is formed as an idle channel. Thus, even when a transmitting signal is delayed in the cable transmission line 1, the time division arranged channel in the returning block can be surely rearranged at the original channel on the sending side 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bidirectional wired communication system suitable for use in a simultaneous interpretation system for international conferences.

[0002]

2. Description of the Related Art FIG. 7 shows a block diagram of a conventional wire communication system used in a simultaneous interpretation system for an international conference or the like.

In FIG. 7, 1-1 is a wired transmission line such as a coaxial cable laid between a transmitting device 2-1 on the sending side 2 and a receiving device 3-2 on the returning side 3, and 1-2 is a returning line. A wired transmission line such as a coaxial cable laid between the transmitting device 3-1 on the side 3 and the receiving device 2-2 on the sending side 2, 10 is an oscillator for giving a clock signal to the timing generator 11, 11
Is a timing generator for generating timing for time division multiplexing of channels, 12 is a synchronization pulse generator for generating synchronization pulses indicating timing of time division multiplexed channels, 13 is a multiplexer for time division multiplexing of channels CH0 to CH6, 14 Is a PPM modulation circuit that performs pulse position modulation (hereinafter referred to as PPM modulation) on each of the time-division multiplexed channels, and 15 is an additional circuit that adds a synchronization pulse to the PPM modulation output.
Is an oscillator 10, a timing generator 11, a sync pulse generator 12, a multiplexer 13, and a PPM modulator 1.
4 and additional circuit 15.

Further, 16 is a PPM for PPM demodulating the time division multiplexed channel transmitted from the return side 3.
A demodulator, 17 is a demultiplexer for rearranging the PPM-demodulated time division multiplexed channel into each original channel,
Reference numeral 18 is a sync pulse detection circuit that detects a sync pulse from the transmitted signal, 19 is a sync oscillator that oscillates synchronously with the detection pulse from the sync pulse detection circuit 18, and 20 is a time division multiplex that receives a clock from the sync oscillator 19 A timing generator that generates timing for rearranging channels, 21 is an output terminal, and the receiver 2-2 on the sending side 2 is a PPM demodulator 16 and a demultiplexer 1
7, a synchronous pulse detection circuit 18, a synchronous oscillator 19, a timing generator 20, and an output terminal 21.

The transmitting device 3-1 on the returning side 3 has the same structure as the transmitting device 2-1 on the sending side 2, and the receiving device 3-2 on the returning side 3 and the receiving device 2-2 on the sending side 2 are the same. With the same configuration, corresponding blocks are indicated by adding a dash to the reference numerals, and detailed description thereof will be omitted. The frame configuration of the wired communication system shown in FIG. 7 is shown in FIG. 8, and the operation of the wired communication system shown in FIG. 7 will be described with reference to FIG.

In FIG. 8, (a) shows a frame structure of a signal transmitted from the transmitting side 2. Block 1 to block 8 constitute one frame, of which block 1 is a block for transmitting a sync pulse. Blocks 2 to 8 are blocks for transmitting time-division multiplexed channels CH0 to CH6, respectively. Further, FIG. 3B shows a frame structure of a signal transmitted from the return side 3,
One frame is composed of block 9 to block 16,
The block 9 is a block for transmitting a synchronization pulse, and the blocks 10 to 16 are blocks for transmitting the time-division multiplexed channels CH7 to CH13.

In the wired communication system shown in FIG. 7, the sending side 2 is provided, for example, at a control desk at an international conference hall,
The returning side 3 is provided in the interpreter's booth, and the sending side 2 of the control console and the returning side 3 provided in the interpreter's booth are connected by two transmission lines 1-1 and 1-2. There is. In this figure, voices in languages such as English, French, German, and Japanese spoken by the participants of the international conference are applied to the multiplexer 13 via any one of the channels CH0 to CH6, and the respective channels CH0. .. to CH6 are time-divisionally multiplexed and arranged by the multiplexer 13 to be allocated to each of the blocks 2 to 8 which are divided in time as shown in FIG. 8A, and are arranged on the time axis.

The timing at which the multiplexer 13 allocates each block is the timing generator 11.
The timing generator 11 operates by the clock from the oscillator 10 and outputs a predetermined timing. Further, the timing pulse of the timing generator 11 is also applied to the synchronization pulse generator 12, and the synchronization pulse generator 12 generates the synchronization pulse at the timing of the block 1 shown in FIG. Apply. The additional circuit 15 adds a synchronization pulse to the time-division multiplexed channels CH0 to CH6 of blocks 2 to 8 as shown in FIG. 8A, and transmits the time-division multiplexed signal to a wired transmission line 1-1 such as a coaxial cable. Send to.

A signal obtained by time-division-multiplexing voices of various languages transmitted via the transmission line 1-1 is delayed by the propagation time of the transmission line 1-1, and then received by the receiving device 3-2 on the return side 3.
To reach. The receiving device 3-2 detects the sync pulse from the arrived time division multiplexed signal by the sync pulse detection circuit 18 'and applies the detected sync pulse to the sync oscillator 19', so that the sync oscillator 19 'is controlled by the feed side 2. It is synchronized with the sync pulse and oscillates at a frequency that is multiple times that frequency.

The timing generator 20 'operates using the output pulse from the synchronous oscillator 19' as a clock to generate the timing of blocks 2 to 8 as shown in FIG. 8 (a). In addition, the time division multiplexed signal is a PPM demodulator 1
6'performs PPM demodulation based on the timing pulse from the timing generator 20 'and applies it to the demultiplexer 17'. The demultiplexer 17 'operates according to the timing pulse from the timing generator 20', rearranges the applied time division multiplexed channel to each of the original channels CH0 to CH6, and outputs it.

Channels CH0 to CH6 demodulated in the receiving device 3-2 are connected to a simultaneous interpreter,
Simultaneous interpreters use these channels CH0
To CH6, the selected language is translated into another language and transmitted from the transmitting device 3-1 on the return side 3 to the transmitting side 2. Since the configuration of the transmission device 3-1 is the same as that of the transmission device 2-1, and its operation is also the same, a detailed description of the operation of the transmission device 3-1 is omitted, but the channels CH7 to CH13 of the transmission device 3-1 are omitted. Multiple languages are simultaneously translated by multiple simultaneous interpreters using
(F) It is sent via the transmission line 1-2 for returning.

The receiving device 2-2 on the sending side is the transmitting device 3-1.
The channel CH7 which is time-division-multiplexed based on the timing of this sync pulse is detected.
By re-arranging CH13 to the original channel, various languages translated by the simultaneous interpreter are demodulated. The receiving device 2-2 is the receiving device 3-2.
Although the description of the detailed operation of the receiving device 2-2 is omitted because it has the same configuration and the same operation as the receiving device 2-2, the language transmitted on the simultaneously translated channels CH7 to CH12 output from the demultiplexer 17 is used for the international conference. It is sent to the participating participants, and the participant selects, for example, a native language from the various languages that are simultaneously translated and understands the content.

The time-division multiplexed signal transmitted from the transmitter 3-1 of the return side 3 is described as the same timing as the timing of the transmitter 2 as shown in FIG. The paths are the transmission path 1-1 for sending and the transmission path 1 for returning.
-2 are independent transmission paths, it is not necessary to have any relationship between the timing of the transmission device 2-1 and the timing of the transmission device 3-1. Each timing is arbitrary. Can be the timing of.

[0014]

However, in the wired communication system of the simultaneous interpretation system shown in FIG. 7, the distance between the control console at the international conference hall and the interpreter's booth may reach several hundred meters. There is a problem that it is disadvantageous in terms of cost and use efficiency of the transmission line to lay two wired transmission lines in the meantime.

In order to solve this problem, a single wire transmission line connecting the sending side and the returning side is used and the frame of the sending section shown in FIG. 8A and the returning section shown in FIG. 8B. It is conceivable that one wire transmission path may be used for both sending and returning by time-allocating the transmission time with the frame. However, in this case, the returning side 3 needs to be sent back in synchronization with the sending side 2, but since the wired transmission line has a propagation time, the timing of the synchronization pulse received by the returning side 3 is the same as that of the sending side 2. It becomes the timing which delayed the pulse.

The timing sent back from the returning side 3 synchronized with this delayed timing reaches the sending side 2 after being further delayed, and the timing pulse generated from the timing generator of the sending side 2 is used. Therefore, even if the frame received by the sending side 2 is attempted to be demultiplexed into each channel, the time position of the timing pulse and the channel rearranged by this timing pulse are displaced due to the above delay time, and the time division multiplexed channel is obtained. Sometimes it became impossible to relocate to the original channels. As described above, according to the above-mentioned method, it is impossible to have one wired transmission line because the wired transmission line has a propagation time. Therefore, an object of the present invention is to provide a two-way wired communication system that uses one wired transmission line and can demodulate a time division multiplexed channel from a transmission signal delayed by the wired transmission line.

[0017]

In order to achieve the above object, in the bidirectional wire communication system of the present invention, one wire transmission line connecting the sending side and the returning side is provided and one frame is used as a sending section. By configuring a return section and time-allocating the transmission time of the sending section and the returning section, the wired transmission path is commonly used for sending and returning. Further, the return-side transmitting device is provided with means for generating a second return synchronization pulse, and
In the transmitting device on the return side, the last channel time-division multiplexed is set as an empty channel, and the generated return synchronization pulse is transmitted to the transmission side together with the time-division multiplexed channel.

Further, in the receiving device on the sending side, the return synchronization pulse is detected from the transmitted signal, and the timing pulse based on the timing of the detected return synchronization pulse is generated, and the timing pulse is used for time division multiplexing. It is arranged to rearrange the created channels to the original channels. In addition, for example, the pulse width of the feed synchronization pulse is set to be relatively wide so that the first feed synchronization pulse transmitted from the feed side and the return synchronization pulse transmitted from the return side are detected separately. The pulse width of the sync pulse is relatively narrow.

[0019]

In the bidirectional wired communication system as described above,
The time-division multiplexed channel transmitted from the return side,
Since demultiplexing is performed based on the timing of the second synchronization pulse transmitted from the return side, even if the time division multiplexed signal is delayed in the wired transmission line, it is possible to surely rearrange the original channel regardless of the delay time. I can. In addition, since the last channel time-division multiplexed in the transmitter on the return side is an empty channel, even if the last channel of the return section is delayed and superimposed on the feed section, it has no effect on the signal of the feed section. Absent. Therefore, one frame in which the sending section and the returning section are time-allocated can be transmitted by one transmission path, so that the wired transmission path can be easily laid and the cost can be reduced.

[0020]

1 is a block diagram of a two-way wired communication system according to the present invention. In FIG. 1, reference numeral 1 is a wired transmission line shared by the sending side 2 and the returning side 3, and 10 is a timing generator 1.
An oscillator for giving a clock signal to 1; a timing generator for generating a timing of a feed section; a feed sync pulse generator for generating a feed sync pulse showing a timing of a time division multiplexed channel of the feed section;
Reference numeral 3 is a multiplexer for time-division multiplexing and arranging channels CH0 to CH6, 14 is a PPM modulation circuit for PPM modulating each of the time-division-multiplexing arranged channels, 15 is an additional circuit for adding a synchronization pulse to the PPM modulation output, and SW1 is a sending section. Is a switch connected to the resistance Rm side during the return period and connected to the impedance Zo side during the return period, and the transmitter 2-1 on the sending side 2 includes the oscillator 10 and the timing generator 1.
1, feed sync pulse generator 12, multiplexer 13,
It is composed of a PPM modulator 14, an additional circuit 15, and a switch SW1.

Further, 16 is a PPM demodulator for PPM demodulating the signal in the sending section transmitted from the transmission line 1, 17
Is a demultiplexer for rearranging the PPM-demodulated time-division multiplexed channel to each of the original channels CH7 to CH12, and 18 is a return for detecting a return synchronization pulse from the transmitted return section using the timing pulse from the timing generator 11. A sync pulse detection circuit, 19 is a sync oscillator that oscillates in synchronization with a detection pulse from the return sync pulse detection circuit 18, and 20 receives a clock from the sync oscillator 19 to generate timing pulses to be applied to the multiplexer 17 and the PPM demodulator 16. It is a timing generator, and the receiving device 2-2 on the sending side 2 is directly connected to the transmission line 1, and includes the PPM demodulator 16 and the demultiplexer 1.
7, a return sync pulse detection circuit 18, a sync oscillator 19, and a timing generator 20.

Further, 33 is a timing generator 4.
Channels CH7-CH at timings generated from 0
A multiplexer for arranging 12 in a time division multiplex manner and a PPM for performing a PPM modulation for each channel in the time division multiplex arrangement
A modulator, 32 is a sync pulse generator that indicates the timing of time division multiplexed channels in the return section, 35 is an additional circuit that adds a sync pulse to the PPM modulation output, and SW2 is connected to the resistor Rm side during the return section, The transmitter 3-1 on the return side 3 is a switch connected to the impedance Zo side during the sending section, and the multiplexer 33, the PPM modulator 34, the return synchronization pulse generator 32, the additional circuit 35,
It is composed of a switch SW2.

Further, 36 is a PPM demodulator for PPM demodulating the time division multiplexed channels transmitted in the sending section, 3
7 is a demultiplexer for rearranging the time-division multiplexed channel to the original channel, 38 is a feed sync pulse detection circuit for detecting a feed sync pulse from the transmitted feed section, 39 is a detection from the feed sync pulse detection circuit 38 Synchronous oscillator that oscillates synchronously by pulses, 40 is a synchronous oscillator 3
Is a timing generator that receives the clock from 9 and applies the timing pulse to the demultiplexer 37 and the timing to apply to the multiplexer 33.
The receiving device 3-2 on the return side is directly connected to the transmission line 1,
It is composed of a PM demodulator 36, a demultiplexer 37, a sync pulse detection circuit 38, a sync oscillator 39, and a timing generator 40.

The structure of one frame of the bidirectional wired communication system shown in FIG. 1 is shown in FIG. 2, and the operation of the bidirectional wired communication system shown in FIG. 1 will be described with reference to FIG. FIG. 2A shows one frame composed of a feed section and a return section which are time-allocated, and the feed section is composed of blocks 1 to 8 in which a relatively wide feed sync pulse is
Channels CH0 to CH6 from block 2 to block 8
Are assigned respectively. Further, the return section is composed of blocks 9 to 16 and a relatively narrow return synchronization pulse is allocated to the block 9 and channels CH7 to CH12 are allocated to the blocks 10 to 15 respectively, and the block 16 is an empty channel. .

Further, FIG. 2B shows the time positions of the delayed blocks 9 to 16 when the signal in the return section is delayed by the wired transmission line 1 and reaches the sending side 2, and FIG. Another example of the structure of one frame in which the blocks 2 and 10 are also empty channels is shown in FIG. In the two-way wired communication system shown in FIG. 1, the sending side 2 is provided at the control desk of the international conference hall, and the returning side 3 is provided at the interpreter's booth. The sending side 2 of the control desk and the interpreter's booth are provided. The provided return side 3 is connected by a transmission line 1.

In this figure, voices in languages such as English, French, German, and Japanese spoken by the participants of the international conference are applied to the multiplexer 13 via any of the channels CH0 to CH6, respectively. Channels CH0 to CH6 are assigned to each of blocks 2 to 8 which are divided in time as shown in FIG. 1A by being time-division multiplexed by the multiplexer 13 and arranged on the time axis.

The timing at which the multiplexer 13 allocates each block is the timing generator 11.
The timing generator 11 operates by the clock from the oscillator 10 and outputs a predetermined timing.

The timing pulse of the timing generator 11 is also applied to the feed sync pulse generator 12, and the feed sync pulse generator 12 generates the feed sync pulse at the timing of block 1 shown in FIG. A sending sync pulse is applied to the circuit 15. The feed sync pulse generated by the feed sync pulse generator 12 is shown in FIG.
As shown in (1), unlike the return synchronization pulse, the pulse has a relatively wide width compared to the pulse of each channel.

The addition circuit 15 adds the feed synchronization pulse of block 1 to the time-division multiplexed channels CH0 to CH6 of blocks 2 to 8 as shown in FIG. The time-division multiplexed signal is sent to the wired transmission line 1 via the switch SW1 which is switched to the transmission device 2-1 side during the period.

The time division multiplexed signals in various languages transmitted via the transmission line 1 are delayed by the transmission line 1 based on the propagation time and reach the receiving device 3-2 on the return side 3. The receiver 3-2 detects the feed sync pulse from the arrived time division multiplex signal by the feed sync pulse detection circuit 38 and applies the detected feed sync pulse to the sync oscillator 39. The synchronous oscillator 39 is synchronized with the feed sync pulse and oscillates at a frequency that is a multiple thereof.

The timing generator 40 operates using the output pulse from the synchronous oscillator 39 as a clock to generate the timings of block 2 to block 8 as shown in FIG. By the timing pulse from the timing generator 40, the demultiplexer 37 causes the time-division-multiplexed channels CH0 to CH.
6 is rearranged to the original channel and output.

Each of the output channels CH0 to CH6 is sent to a simultaneous interpreter, and the simultaneous interpreter selects a language to be translated from these channels CH0 to CH6 and simultaneously translates the selected language into another language. And sends back from the transmitting device 3-1 on the returning side 3 to the sending side 2. Note that the simultaneous interpreter can also select channels CH7 to CH12 so that other simultaneous interpreters can select and listen to the translated language as well.

In the transmission device 3-1, various languages translated by a plurality of simultaneous interpreters are CH7 to CH1.
2 is applied to the multiplexer 33 via either
Each of the channels CH7 to CH12 is processed by the multiplexer 33 as shown in FIG.
Are allocated to blocks 15 to be time-division multiplexed. The timing at which the multiplexer 33 allocates each block is performed by the timing pulse from the timing generator 40, and the timing generator 40 operates by the clock of the synchronous oscillator 39 as described above and outputs the timing of the feed section. .

Further, the timing pulse from the timing generator 40 is also applied to the return synchronization pulse generator 32, and the return synchronization pulse generator 32 is relatively equal to the pulse width of each channel as shown in FIG. 1 (a). A return sync pulse having a narrow width is generated at the timing of block 9 and applied to the additional circuit 35. The additional circuit 35 is a channel C of blocks 10 to 15 which are time-division multiplexed.
From H7 to CH12, block 9 as shown in FIG.
Of the transmitting device 3 by adding the return synchronization pulse of
The time-division multiplexed signal is sent to the transmission line 1 via the switch SW2 which is switched to the -1 side.

The time-division multiplex signals, which are sent back through the transmission line 1 and are simultaneously translated, are transmitted through the transmission line 1.
Then, the signal arrives at the receiving device 2-2 on the sending side 2 with a delay at.
The return synchronization pulse detection circuit 18 of the reception device 2-2 detects a return synchronization pulse from the transmitted return section. The detected return synchronization pulse is applied to the synchronization oscillator 19, and the synchronization oscillator 19 synchronizes with the return synchronization pulse and oscillates a clock having a frequency multiple thereof. This synchronous oscillator 1
The clock 9 is applied to the timing generator 20, and the timing generator 20 generates the timing pulse applied to the PPM demodulator 16 and the timing pulse applied to the demultiplexer 17. In the PPM demodulator 16 using this timing pulse, the transmitted time division multiplexed signal in the return section is PPM demodulated by the PPM demodulator 16 and applied to the demultiplexer 17. The demultiplexer 17 operates according to the timing pulse from the timing generator 20 and rearranges the time-division multiplexed channels to the original channels CH7 to CH12 and outputs them.

Each channel CH of the demultiplexer 17
The outputs of 7 to CH12 are sent to the participants of the international conference, and the participants understand the utterance contents of the speaker by selecting, for example, a channel in a native language from the languages translated by the simultaneous interpreter. The impedance Zo is made equal to the characteristic impedance of the wired transmission line 1 and functions as a terminating impedance for preventing reflection.
The resistor Rm is a resistor inserted for impedance matching between the impedance Zo of the transmission path and the transmission device 2-1 or the transmission device 3-1. As described above, by providing the impedance Zo and the resistance Rm, it is possible to prevent the reflection at the terminal. Therefore, the transmission line 1
Since the reflected signal is suppressed as much as possible, the receiving device can receive without error.

The receiving device 2-2 on the sending side operates as described above, but the block in the returning section arrives at the sending side 2 as shown in FIG. After the delayed time. Therefore, the receiving device of the sending side 2 uses the timing of the sending side of blocks 10 to 16 as shown in FIG. 2A, and the blocks 10 to 16 of the received return section shown in FIG. When the channels are rearranged, as understood from the figure, the channels are rearranged across two blocks, and it becomes impossible to demodulate each channel.

However, in the two-way wired communication system shown in FIG. 1, the return sync pulse is inserted and transmitted in the return section and rearranged at the timing of the return sync pulse of the block 9 shown in FIG. Figure 2
Each channel in the return section shown in (b) can be rearranged at correct timing without straddling two blocks.

Further, the reason for distinguishing and detecting the sending synchronization pulse and the returning synchronization pulse is that the receiving device 3-2 on the returning side and the receiving device 2-2 on the sending side are directly connected to the transmission line 1. Synchronous pulse detection circuit 18, 38 of both receivers
Both the feed sync pulse and the return sync pulse are input to. Since the return synchronization pulse is delayed and transmitted to the transmission line as described above, the synchronization between the both synchronization pulses is not established and it is impossible to establish synchronization using both the synchronization pulses.

As described above, since it is possible to synchronize only one of the sync pulses, for example, the pulse width of the feed sync pulse is made relatively wide, and the pulse width of the return sync pulse is made relatively narrow so that both sync pulses are synchronized. Can be separately detected, the synchronization pulse detection circuit 38 provided on the return side detects only the feed synchronization and establishes synchronization, and the synchronization pulse detection circuit 18 provided on the transmission side detects only the return synchronization pulse. It is configured to synchronize.

As described above, the block of the return section is delayed and received by the receiving device 2-2. Therefore, the block 16 of the delayed return section and the block 1 of the sending section are delayed.
There is a risk that and will collide with each other in time, and the information of the block that has collided with time will be lost. In order to prevent such a situation, in the present invention, the final block 16 is an empty channel as shown in FIG. That is, by making the block 16 an empty channel, it is possible to prevent the information of the block 1 from being lost even if the block 16 collides with the block 1.

FIG. 2C shows the structure of another frame.
In this figure, in addition to block 16, blocks 2 and 10 are also used as free channels. This means that in order to send a PPM modulated pulse signal using the next block of sync pulses, the PPM modulated pulse signal using the next block of sync pulses must not affect the sync pulse. . Therefore, it is necessary to take measures such as limiting the input of the PPM-modulated signal. Therefore,
As shown in FIG. 2 (c), the block next to the sync pulse is set to an empty channel so that the receiver can transmit the sync pulse without error in detection without taking measures such as input limitation. become.

Next, the configurations of the feed synchronization pulse detection circuit 38 and the return synchronization pulse detection circuit 18, which can detect the feed synchronization pulse and the return synchronization pulse separately, will be described.
First, regarding the feed synchronization pulse detection circuit 38,
Since the pulse width of the feed sync pulse is set relatively wide as described above, a block diagram of the feed sync detection circuit 38 for detecting the feed sync pulse is shown in FIG. In FIG. 3, 101 is an integrator that integrates the signal pulse of the transmitted feed section, 102 is an identification circuit for identifying that the output level of the integrator 101 exceeds the reference level Vref, and 103 is the transmitted feed section. An input terminal to which a signal pulse is input, 104 is an integrator 101
Is a reset switch for resetting the integrating capacitor Cs, 105 is a constant current source for generating a constant current supplied to the integrator 101, and 106 is an output terminal for outputting the detected detection output.

FIG. 4 shows an operation waveform diagram of the feed synchronization detection circuit shown in FIG. In FIG. 4, (a) is a diagram showing an input signal pulse in the feed section, and (b) is an integrator 101.
Of FIG. 3 is a diagram showing an output waveform of the discriminating circuit 102. FIG. The operation of the feed synchronization detection circuit shown in FIG. 3 will be described with reference to FIG. When the signal pulse in the feed section applied to the input terminal 103 in this figure rises as shown in FIG. 4, the reset switch 104
Is turned off, and the integrating circuit 101 integrates the constant current Is from the constant current source. Therefore, the output of the integrator 101 rises linearly as shown in FIG. Next, when the signal pulse in the feeding section falls, the reset switch 1
Since 04 is "on" and the integrating capacitor Cs is reset, the output of the integrator 101 is reset to zero.

For this reason, the integrator 101 integrates the constant current Is only when the signal pulse in the feed section rises, so the output waveform of the integrator 101 is shown in FIG. 4 (b).
As shown in, a sawtooth waveform having a height proportional to the width of the signal pulse is obtained. Such a sawtooth wave shown in FIG. 4B is applied to the identification circuit 102, compared with the reference voltage Vref, and when the level of the sawtooth wave exceeds the reference voltage Vref,
The discrimination circuit 102 outputs an output pulse as shown in FIG. Since the level of the sawtooth wave exceeds the reference voltage Vref only when the width of the signal pulse is wide, the identification circuit 102 outputs only when the feed synchronization pulse having a relatively wide width is applied to the integrator 101. Generate a pulse,
The feed sync pulse can be detected.

Next, FIG. 5 shows a block of a return sync pulse detecting circuit for detecting a return sync pulse having a relatively narrow pulse width which is almost the same as the pulse width of each channel. In FIG. 5, 111 is a timing generator provided in the receiving device 2-1 on the sending side, 112 is a flip-flop set by a timing pulse from the timing generator 111 and reset by a signal pulse in the return section, 113 is a flip-flop. A monostable multivibrator that outputs a pulse of a predetermined width triggered by the falling edge of the pulse, 114 is an output line from which the timing pulse of the timing generator 111 is output, 115 is an input terminal to which the signal pulse of the return section is input, 116 Is an output terminal to which a detection output is output.

FIG. 6 shows an operation waveform diagram of the return sync pulse detection circuit shown in FIG. 6A is a diagram showing the waveform of the transmitted pulse signal in the return section, FIG. 6B is a diagram showing timing pulses of the timing of the block 9 output from the timing generator 111, and FIG. An output waveform diagram of the flip-flop 112, and FIG. 7D is a diagram showing an output pulse of the monostable multivibrator 113.
The operation of the return synchronization detection circuit shown in FIG. 5 will be described with reference to the operation waveform diagram shown in FIG. In FIG. 5, the timing generator 111 outputs the timing pulse shown in FIG. 6B to the line 114 at the timing of the block 9 shown in FIG. The flip-flop 112 is set by the timing pulse output to the line 114 and reset by the pulse signal transmitted after the timing of the block 9.

The pulse transmitted in block 9 is the same as in FIG.
As shown in (a), it is a return synchronization pulse, and if it is not delayed in the transmission line, it is transmitted at the timing shown by the broken line in FIG. 6 (a). It is input to the input terminal 115 at such timing. Therefore, the output waveform of the flip-flop 112 is shown in FIG.
As shown in (c), the waveform rises at the rising edge of the block 9 and falls at the rising edge of the input return synchronization pulse. The monostable multivibrator 113 is triggered by the falling edge of the output waveform of the flip-flop 112, and the detection pulse as shown in FIG. 6D is output from the output terminal 116, and the return synchronization pulse can be detected.

In the above description, the number of channels in the sending section is 6 or 7 and the number of channels in the returning section is 5 or 6; however, the number of channels is not limited to this, and one frame can be configured with any number of channels. . The wired transmission path is not limited to the coaxial cable, and an optical cable may be used. Further, in the configuration shown in FIG. 1, although the channel selection is performed after returning to each channel, the receiving device is provided with the channel select function and the gate pulse for extracting only a specific block is created by using the timing generator. Then, a desired channel may be selected. However, in this case, a plurality of receiving devices are required for each of the sending side and the returning side.

Further, the synchronizing pulse detecting circuit is configured to be able to detect both the sending synchronizing pulse and the returning synchronizing pulse, and is configured to be able to select and detect one of the sending synchronizing pulse and the returning synchronizing pulse. May be received. In particular, by configuring the sync pulse detection circuit of the receiving device on the return side as described above,
The simultaneous interpreter can hear the language translated by another simultaneous interpreter by using the channel selection function of the receiving device.

[0051]

Since the present invention is configured as described above, since the time division multiplexed signal transmitted from the return side is demultiplexed based on the timing of the return synchronization pulse transmitted from the return side, the wired Even if the time division multiplexed signal is delayed on the transmission line, it can be rearranged to the original channel regardless of the delay time. In addition, since the time-division-multiplexed final channel is set as an empty channel in the transmitter on the return side, even if the final channel in the return section is delayed and superimposed on the transmission section, it does not affect the signal in the transmission section. . Therefore, by allocating time to the sending section and the returning section to form one frame, it is possible to use the two-way wired communication system with one wired transmission path.

[Brief description of drawings]

FIG. 1 is a block diagram of a two-way wired communication system of the present invention.

FIG. 2 is a timing diagram of the two-way wired communication system of the present invention.

FIG. 3 is a diagram showing a feed synchronization pulse detection circuit.

FIG. 4 is an operation waveform diagram of a feed synchronization pulse detection circuit.

FIG. 5 is a diagram showing a return synchronization pulse detection circuit.

FIG. 6 is an operation waveform diagram of the return synchronization pulse detection circuit.

FIG. 7 is a block diagram of a conventional wired communication system.

FIG. 8 is a timing diagram of a conventional wired communication system.

[Explanation of symbols]

1, 1-1, 1-2 Wired transmission line 2 Sending side 2-1 Sending side transmitting device 2-2 Sending side receiving device 3 Returning side 3-1 Returning side transmitting device 3-2 Returning side receiving device 10, 10 'Oscillator 11, 20, 11', 20 ', 40 Timing generator 12, 12', 32 Synchronous pulse generator 13, 13 ', 33 Multiplexer 14, 14', 34 PPM modulator 15, 15 ', 35 Additional circuit 16, 16 ', 36 PPM demodulator 17, 17', 37 Demultiplexer 18, 18 ', 38 Synchronous pulse detection circuit 19, 19', 39 Synchronous oscillator 20, 20 ', 40 Timing generator 103 Input terminal 104 Reset Switch 106 Detection output terminal 111 Timing generator 112 Flip-flop 113 Monostable multivibrator 114 Timing generator Output line 115 of Nerator 115 Input terminal 116 Detection output terminal CH0-13 channel Rm Matching resistor Zo Impedance SW1, SW2 switch

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H04J 3/16 A 9371-5K

Claims (4)

[Claims] 1. A wired communication system in which a sending section for sending a signal from a sending side and a returning section for processing and sending back a signal sent on the returning side are time-allocated, wherein the sending section has a first synchronization pulse. And a plurality of feed channels time-division-multiplexed at a timing based on the timing of the first sync pulse, and the return section includes a second sync pulse that can be detected separately from the first sync pulse and a final channel. An empty channel, which is composed of a plurality of return channels time-division-multiplexed at the timing based on the second synchronization pulse, the receiving means on the return side detects the first synchronization signal, and the detected first synchronization A means for rearranging the time-division-multiplexed feed channels to the respective channels based on the timing of the signal; Is detected and the means for rearranging the time-division-multiplexed return channel to each channel based on the timing of the detected second synchronizing signal is not affected by the propagation delay due to the wired transmission path. A two-way wired communication system characterized by doing so. 2. The bidirectional wired communication system according to claim 1, wherein the signal in the channel is PPM-modulated. 3. The first synchronizing pulse detecting means comprises an integrating means for integrating the first synchronizing pulse and an identifying means for identifying an output level of the integrating means, and the output level of the integrating means has a predetermined identifying level. The two-way wired communication system according to claim 1 or 2, wherein when the identification means identifies that it has exceeded, a sync pulse is detected. 4. The second synchronizing pulse detecting means includes means for generating a timing pulse of a block in which the second synchronizing pulse is located on the sending side, and a second synchronizing pulse input in an inverted state at the timing pulse. The two-way wired communication system according to any one of claims 1 to 3, characterized in that it comprises a bistable means that recovers with a pulse, and a means that generates a detection pulse when the bistable means recovers.