JPH06232747A - A/d converter circuit and a/d conversion method - Google Patents

Abstract

PURPOSE:To execute high speed operation without causing deterioration in accuracy and to execute conversion in response to a degree of emphasis of high speed performance or accuracy by adopting a so-called nesting structure for a conversion sections of plural stages. CONSTITUTION:A 1st stage conversion section 1 consists of an A/D converter ADC1c receiving an analog signal IN to be converted. Furthermore, a 2nd stage conversion section 2 connects an output terminal of a just preceding stage conversion section (the 1st stage conversion section 1) to a DAC 2a and an output terminal of the DAC 2a connects to one input of a differential amplifier 2b. An analog signal IN to be converted is given to the other input terminal of the differential amplifier 2b and its output terminal is connected to the ADC2c. Moreover, the output terminal of the ADC2c and the output terminal of the ADC1c are connected to a digital correction circuit 2d having an over range arithmetic operation function. Then the configuration of 3rd and succeeding conversion sections is the same as the configuration of the 2nd stage conversion section. However, a differential amplifier of each stage amplifies a difference between the analog signal IN and an output of a DAC of a concerned stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-digital conversion circuit and an analog-digital conversion method,
The present invention relates to the above sub-ranging conversion circuit and conversion method, which can perform high-speed operation without causing deterioration of accuracy and can easily perform conversion according to the degree of importance of high-speed performance and accuracy.

[0002]

2. Description of the Related Art Analog-digital (AD) conversion circuits are classified into various types such as a flash type, a successive approximation type, a dual slope type, etc., depending on the conversion method. Ideally, these conversion circuits are high-speed and high-precision, but depending on the conversion principle and conversion method, there are some that are suitable for high-speed operation and those that are suitable for high-precision operation. It's not easy. FIG. 4 is a graph showing the relationship between conversion speed and accuracy (or resolution) of AD conversion circuits used in commercially available electronic devices. As shown in the figure, the A-D conversion circuit generally decreases in speed if the accuracy is increased and conversely decreases in accuracy if the speed is increased.

By the way, an A-D conversion circuit using a sub-ranging method is used for applications requiring a balance between speed and accuracy. FIG. 5 shows a sub-ranging type A-D conversion circuit having a four-stage configuration. In this sub-ranging type A-D conversion circuit, an ADC (analog-digital converter) 5c forming the first stage conversion unit 5 first roughly A-D-converts the converted analog signal IN, and outputs the converted output. The data is output to the n-bit output digital correction circuit 9 and the second stage conversion unit 6.

The second stage converter 6 converts the digital signal from the ADC 5c into a DAC (digital-analog converter) 6
a is converted into an analog signal, the difference amplifier 6b obtains the difference between the converted analog signal IN and the analog signal from the DAC 6a, and the difference is re-converted to A by the ADC 6c.
-D conversion, and the converted output is the digital correction circuit 9
And output to the third stage conversion unit 7.

In the third stage conversion section 7, in the same manner as described above,
The DAC 7a converts the output of the ADC 6c in the preceding stage into an analog signal, and the differential amplifier 7b converts it into an analog signal.
The difference between the analog output of b and the analog output from the DAC 7a is obtained, this is A / D converted by the ADC 7c, and this converted output is output to the digital correction circuit 9 and the fourth stage conversion unit 8.

Thereafter, by repeating the same steps up to the final stage (in this case, up to the next stage), a highly accurate (n-bit in the figure) A-D conversion result can be obtained. In the sub-ranging A / D conversion circuit, the accuracy is improved by increasing the number of stages of the conversion unit, but on the other hand, as described above, the time required for conversion becomes long.

By the way, a general A / D conversion circuit is required to have a higher accuracy and a higher speed as a matter of course, while satisfying the speed or accuracy requirements depending on its application and standard. Therefore, in designing an actual AD conversion circuit, if a certain speed or accuracy is determined, a circuit optimized for this is designed. This allows
An A-D conversion circuit designed on the premise of a certain application, standard, etc. usually cannot always meet other applications, standards, etc. (that is, other speed, accuracy).

However, in many cases such as a general-purpose tester or a measuring instrument, it is often required to change the speed and accuracy of the A-D conversion circuit widely depending on the object to be measured. In some cases, it may be desired to operate at high speed with a higher speed than accuracy, and conversely with a higher accuracy than a high speed.

In the sub-ranging type A-D conversion circuit shown in FIG. 5, it is possible to meet the wide range of speed and accuracy requirements as described above by appropriately switching the number of stages according to the application. .

[0010]

However, the one designed on the basis of a certain speed or accuracy always has a desired speed and accuracy even if it is diverted to another application requiring a speed or accuracy of a different reference. It is difficult to combine both. For example, in the A / D conversion circuit of FIG. 5, as described up to the third stage or the second stage, the output from the first stage conversion unit to the conversion unit of the last stage to the previous stage is extracted and m bits (m <N)
When used as the A-D conversion circuit of, the relationship between the speed and the accuracy is as shown in the plot of “x” in FIG. 4, and the point is in the area below the originally expected characteristic (line L in the figure). Since it is located, desired characteristics of speed and accuracy cannot be obtained. The point P in the figure shows the initial speed and accuracy.

In other words, when an A-D conversion circuit as described above is used in combination for different purposes, it is inferior in accuracy compared to other A-D conversion circuits of the same speed, and conversely. In comparison with an A / D conversion circuit having the same accuracy, it is inferior in terms of speed. Therefore, when one A-D conversion circuit is used for various purposes, either the speed or the accuracy cannot be satisfied.

The reason why such an inconvenience occurs will be described in more detail together with the operation principle of the sub-ranging type A-D conversion circuit. In the sub-ranging type A-D conversion circuit, when trying to obtain n-bit precision (resolution) at the final stage, the ADC of each stage does not need n-bit precision. For example, as shown in FIG. 6A, when two stages of sub-ranging A / D conversion are performed with two k-bit ADCs to obtain a digital output, k-bits of the first-stage conversion unit 10 (that is, ADC 10c) are used. Lower k'bits and the higher k'bits of the k bits of the ADC 11c of the second stage converter 11 are overlapped as shown in FIG. Choose smaller than 2 × k such that ′ = 2 × k−k ′ <2 × k. Then, the digital correction circuit 12 performs a digital operation (overrange operation) on both ADC outputs to obtain an AD conversion result with k-bit accuracy. In addition, in the same figure (A), the 2nd conversion part 11 has DAC11a, the difference amplifier 1 like the 2nd-4th conversion part of FIG.
It has 1b.

From the operating principle of the sub-ranging type A-D conversion circuit, the following can be easily understood. That is, in FIG. 5, when the final stage is n bits,
DAC (6a, 7a, 8a), difference amplifier (6b, 7)
High precision of n bits is required for analog circuits such as b, 8b). For reference, blocks for which such accuracy is required are shown by hatching in FIG.

In the sub-ranging type A-D conversion circuit having the above-mentioned configuration, m bits (m <n) are extracted from the digital signal from the first stage conversion unit to the second or third stage conversion unit to operate at high speed. Case, line L of the graph in FIG.
In order to obtain a characteristic that transitions up, the faster the conversion rate, the lower the number of stages. In particular, the circuit including the ADC 5c of the first conversion unit, the DAC 6a of the second conversion unit, and the digital correction circuit 6b shown in FIG. 5 is required to operate at high speed.
And the digital correction circuit 6b is originally required to have a high accuracy of n bits. In general, it is difficult for the above-mentioned circuit to meet the requirements for high speed and high precision, so high speed is sacrificed in order to realize n-bit precision, and the preceding stage portion (from the first stage conversion unit to the second or third stage). The speed is insufficient when only m bits are extracted from the digital signal (up to the stage conversion unit).

The present invention has been proposed in order to solve the above-mentioned problems, and the speed and accuracy are appropriately selected according to the application, standard, etc., and the deterioration of the speed and accuracy is sometimes made. A single A-D conversion that does not occur
An object of the present invention is to provide a sub-ranging type A-D conversion circuit and an A-D conversion method that can be realized by a conversion circuit.

[0016]

The inventor of the present invention has found that a conventional sub-ranging type A-D conversion circuit is a so-called "forward feed".
We paid attention to the structure (cascade connection). If a so-called "nested" (nesting connection) structure is adopted instead of the connection, the first-stage conversion unit (or the conversion unit having a small number of stages) requiring the highest speed operation requires high-precision operation. The predetermined bit (smaller than the original output bit of the A / D conversion circuit)
Within the range, it is possible to concentrate on the speedup of the circuit, and the desired speed and precision can be obtained even when only the first stage (or the conversion unit with a smaller number of stages) digital output is taken out and the high speed operation is performed. Therefore, the present invention has been completed.

That is, the AD conversion circuit of the present invention has 3
Comprising at least two stages of conversion units, at least the second
The DAC that receives the output of the previous stage conversion unit after the stage
And a differential amplifier that receives the output of the DAC and the converted analog signal and that amplifies the differential signal between them.
An ADC whose input is the output of the differential amplifier;
And a digital circuit for outputting a predetermined digital signal, which has at least one conversion section.

The digital circuit may be a latch that simply holds two inputs (the ADC on the input side of the digital circuit and the digital output of the immediately preceding stage),
It may be a digital correction circuit that performs overrange calculation on the two inputs.

In addition, the output of the digital circuit of at least one stage other than the final stage can be appropriately extracted as the output of the conversion circuit.

Further, the A-D conversion method of the present invention is the first
To M-th (M ≧ 3) conversion steps, in the first conversion step, the converted analog signal is converted into an n _1- bit digital signal, and the k-th (where k = 2, 3, ...
.., M), the _nk-1 bit digital signal converted by the conversion step of the immediately preceding stage is returned to an analog signal, and the difference between this analog signal and the analog signal to be converted is amplified to obtain a difference. After obtaining the signal and converting the difference signal into a digital signal of n ′ _k bits,
And the digital signal from said n _k-1 bit digital signal, and obtains the digital signal of n _k bits. Here, when an n _k bit digital signal is to be obtained, n _k−1 bits are placed in the higher order and n ′ _k bits are placed in the lower order, and they are simply arranged (n _k = n
_k-1 + n ' _k ) or both digital signals may be subjected to overrange calculation and corrected to obtain n _k bits (n _k <n _k-1 + n' _k ).

[0021]

The typical operation of the present invention will be described below.
In the present invention, the converted analog input signal is AD-converted by the first-stage conversion unit with a predetermined resolution, and the n _1- bit digital signal is output to the second-stage conversion unit (first conversion step).

In the second stage converter, the n _1- bit digital signal is returned to an analog signal by a DAC, the difference between the converted analog signal and the analog signal from the DAC is obtained by a difference amplifier, and this difference is obtained by the ADC. AD conversion. Thus, n _'2-bit digital difference signal are determined. And by the digital circuit,
A predetermined digital signal of n ₂ bits is obtained from the n _1- bit digital signal from the ADC of the first stage and the n ₂ ′ digital difference signal from the ADC of the stage (second).
Conversion step). When the digital circuit is a digital correction circuit having an overrange calculation function, a margin can be provided for the accuracy of the ADC on the input side of the digital correction circuit and the accuracy of the digital output of the immediately preceding conversion unit. it can.

Third, fourth, ..., Kth, ..., Mth
The configuration of each conversion unit is the same as the configuration of the second stage conversion unit. However, these digital circuits input the digital signal from the digital circuit of the immediately preceding stage and the digital signal from the ADC of the relevant stage. The differential amplifier in each stage obtains the difference between the converted analog signal and the output of the DAC in the relevant stage (third, fourth, ..., Mth conversion step).

In the present invention, the accuracy of the analog circuit in the second and subsequent conversion sections is affected by the number of output bits of the digital circuit, but is not affected by the number of output bits of the AD conversion circuit. . For this reason, the accuracy is not required as it goes to the front stage, and high-speed operation can be performed. On the other hand, the higher the accuracy of the analog circuit in the conversion section of each stage is, the higher the number of output bits of the digital circuit is, and therefore the higher precision output can be obtained. When a digital correction circuit that performs an overrange calculation is used as the digital circuit of the output stage of the conversion unit after the second stage, the accuracy of the ADC on the input side of the digital correction circuit and the digital value of the conversion unit of the immediately preceding stage are used. Output accuracy is eased.

Although the present invention basically has a "nested" structure for the conversion unit of each stage, this "nested" structure is mixed with the conventional "progressive" structure shown in FIG. You can also

[0026]

1 is a diagram showing an embodiment of a sub-ranging type A-D conversion circuit of the present invention. In the embodiment shown in FIG.
A digital correction circuit that performs an overrange calculation is used as the digital circuit, and the A-D conversion circuit includes four stages (that is, M = 4) of conversion units. The first-stage conversion unit 1 to which the converted analog signal IN is input is n ₁
It is composed of a bit ADC 1c.

The conversion unit 2 of the second stage is composed of the DAC 2a,
Differential amplifier 2b, and is composed of n _'2 bits ADC2c and digital correction circuit 2d. The output terminal of the first stage conversion unit 1 (that is, the output terminal of the ADC 1c) is connected to the DAC 2a, and the output terminal of the DAC 2a is connected to one input of the difference amplifier 2b. The converted analog signal IN is input to the other input terminal of the differential amplifier 2b, and the output terminal of the differential amplifier 2b is ADC2.
connected to c. The output terminal of the ADC 2c and the output terminal of the ADC 1c are connected to a digital correction circuit 2d having an n ₂ bit output and having an overrange calculation function.

Similar to the second stage conversion unit 2, the third conversion unit 3
ADC is DAC3a, differential amplifier 3b, n _{'of 3} bits
Is constituted by a digital correction circuit 3d and 3c and _{n 3} bit output, the fourth-stage conversion unit 4 DAC3a, it is constituted by the difference amplifier 3b, n _'4 bit ADC4c and _{n 4-bit} output of the digital correction circuit 3d. In each of the conversion units of the third and fourth stages, the output terminal of the preceding stage (that is, the digital correction circuit 2 for the third conversion unit 3)
The output terminal of d, the digital correction circuit 3d) for the fourth conversion unit 4 is connected to the DAC (3a or 4a), and the converted analog signal IN is the difference amplifier (3b,
4b) and other connection states are the same as the connection states of the corresponding constituent elements in the second conversion unit.

The operation of the circuit shown in FIG. 1 will be described below. The number of overrange bits between the output of the AD converter 1c and the output of the AD converter 2c is q ₂ , and the digital correction circuit 2
The number of overrange bits between d and the AD conversion unit 3c is q ₃ , the output of the digital correction circuit 3d and the AD conversion unit 4c.
Number overrange bits of the output when the _{q 4,} the _{n 2 = n '2 + n} 1 -q 2 n 3 = n' 3 + n 2 -q 3 n 4 = n '4 + n 3 -q 4. Here, n ₁ <n ₂ <n ₃ <n ₄ is satisfied.

For example, the number of overrange bits is all 2 bits (that is, q _{2 to} q ₄ is 2), and n ₁ =
If n ₂ ′ = n ₃ ′ = n ₄ ′ = 6, then n ₂ = 10, n
A _{3 = 14, n 4 = 18} . In the figure, the number of bits of each part is shown by (), and a state diagram of overranging is also shown. In this case, D of the second stage conversion unit 2
The AC2a and the differential amplifier 2b have a precision of 4 bits, the DAC 3a of the third stage conversion unit 3 has a precision of 14 bits, and the DAC 4a of the fourth stage conversion unit 4 has a precision of 16 bits. used. Note that, in FIG. 1, the DAC 4a and the digital correction circuit 4b, which require the maximum accuracy, are shown by hatching for comparison with FIG.

Comparing the circuit of FIG. 1 with the conventional A-D conversion circuit described in FIG. 5, the digital correction circuits 2d and 3d are added as a whole.
Stage, third stage ADC 2c, 3c and difference amplifier 2b,
The number of bits of 3b is reduced to 10/16 and 14/16. As a result, in the conversion circuit of the present embodiment shown in FIG. 1, as compared with the circuit shown in FIG. 5 (however, the output bit of the digital correction circuit 9 is 18 bits), the processing speed is significantly increased. Can be up.

Further, the DAC 2a of the second and third stage converters,
Since the circuits of 3a and the differential amplifiers 2b and 3b can be simplified, the cost can be reduced as compared with the conventional A-D conversion circuit shown in FIG. Furthermore, FIG.
As shown in, the outputs OUT _{1 to} OUT ₄ can be taken out from any of the first-stage conversion unit 1 to the fourth-stage conversion unit 4. As described above, the preceding stage has a higher speed, and the subsequent stage has a higher accuracy. In the circuit of FIG. 2, any of the outputs OUT _{1 to} OUT ₄ can be used as appropriate according to the application, standard, etc., so that either high speed or high accuracy can be supported.

FIG. 3 shows another embodiment of the present invention in the case of having a conversion section in which a "nested" structure and a "sequential feed" structure are mixed. The A-D conversion circuit of the present embodiment includes a first stage conversion unit 1, a second stage conversion unit 2 and a third stage conversion unit 3 '.
It is composed by. The first stage conversion unit 1 and the second stage conversion unit 2 are the first stage conversion unit 1 and the second stage conversion unit 2 of FIG.
It has the same configuration as. Also, the third stage conversion unit 3 '
Is composed of a DAC 3'a, a difference amplifier 3'b, an ADC 3'c and a digital correction circuit 3'd.

Here, the ADC 3'c is the ADC 3 '
c ₁ , DAC 3'c ₂ , differential amplifier circuit 3'c ₃ and A
Form a conventional subranging structure of two-stage configuration consisting of DC3'c ₄ is A-D converter circuit of the "forward" connection. As described above, the entire A-D conversion circuit shown in FIG.
The stage and the second stage converters 1 and 2 have a "nested" structure. It should be noted that the figure shows an example of a mixture of the “nested” structure and the “forward feed” structure, and it goes without saying that the positional relationship between “nested” and “forward feed” can be changed. The A-D conversion circuit of FIG. 3 can also achieve the same effects as the A-D conversion circuit shown in FIG. 1, and like the A-D conversion circuit shown in FIG. Thus, a digital output can be obtained from an appropriate stage.

[0035]

Since the present invention is constructed as described above, the following effects can be obtained. (1) The conversion unit having a smaller number of stages can reduce the accuracy of the analog system circuit such as the DAC and the difference calculation circuit, and the high speed can be emphasized. Therefore, it is possible to provide a subranging A / D conversion circuit with a simpler and simpler circuit. Moreover, the accuracy of the entire A-D conversion circuit is not impaired. (2) Further, by appropriately taking out the output from each stage, an application that does not require high accuracy but high speed is required, and conversely, high accuracy is required although high speed is not so required. Since it can be appropriately used for various purposes, it can be preferably used for purposes such as general-purpose measuring instruments where the measurement accuracy is not specified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an AD conversion circuit of the present invention.

FIG. 2 is a block diagram showing a case where a low-precision signal is taken out from each stage of the circuit of FIG.

FIG. 3 is a diagram showing another embodiment of the present invention including a conversion unit in which a “nested” structure and a “sequential feed” structure are mixed.

FIG. 4 is a graph showing a relationship between conversion speed and accuracy of an AD conversion circuit used in a commercially available electronic device.

FIG. 5 is a conventional sub-ranging A / D conversion circuit (4
FIG.

FIG. 6A is a block diagram showing a conventional sub-ranging A / D conversion circuit (two stages), and FIG. 6B is an explanatory diagram of overrange.

[Explanation of symbols]

 1 1st stage conversion part 2 2nd stage conversion part 3 3rd stage conversion part 4 4th stage conversion part 2a, 3a, 4a DAC 2b, 3b, 4b Difference amplifier 1c, 2c, 3c, 4c ADC 2d, 3d, 4d Digital correction circuit

Claims (4)

[Claims] 1. An analog-to-digital conversion circuit comprising three or more stages of conversion units, wherein at least the second and subsequent stages have a digital-to-analog converter which receives the output of the immediately preceding stage conversion unit as input. A differential amplifier that inputs the output of the converter and the converted analog signal and amplifies the difference signal between them, an analog-digital converter that inputs the output of the differential amplifier, and an output of the analog-digital converter An analog-to-digital conversion circuit comprising one or more conversion units each of which comprises a digital circuit which outputs a predetermined digital signal with two inputs of the output of the immediately preceding conversion unit. 2. The analog-digital conversion circuit according to claim 1, wherein the digital circuit is a digital correction circuit that performs an overrange operation on two inputs. 3. The analog-digital conversion circuit according to claim 1, wherein the output of the digital circuit of at least one stage other than the final stage can be appropriately extracted as the output of the conversion circuit. 4. An analog-to-digital conversion method comprising first to M-th (M ≧ 3) conversion steps, wherein in the first conversion step, an analog signal to be converted is converted to n.
Converted to a _1- bit digital signal, and in the k-th (where k = 2, 3, ..., M) conversion step, n converted by the conversion step of the immediately preceding stage
_{Convert the k-1} bit digital signal back to an analog signal,
After the analog signal and said amplifies a difference between the converted analog signal obtains a difference signal, and converting the said difference signal into a digital signal of n _'k bits, and the digital signal,
Digital conversion process - an analog of the the digital signal of the n _k-1 bits, and obtains the digital signal of n _k bits.