JPH06232407A - Double gate mosfet and manufacture thereof - Google Patents
Double gate mosfet and manufacture thereofInfo
- Publication number
- JPH06232407A JPH06232407A JP1551493A JP1551493A JPH06232407A JP H06232407 A JPH06232407 A JP H06232407A JP 1551493 A JP1551493 A JP 1551493A JP 1551493 A JP1551493 A JP 1551493A JP H06232407 A JPH06232407 A JP H06232407A
- Authority
- JP
- Japan
- Prior art keywords
- gates
- gate
- diffusion layer
- gate mosfet
- impurity diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000012535 impurity Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 2
- 239000000470 constituent Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体装置の中でも
特にシリコン（Ｓｉ）基板上に形成されたダブルゲート
ＭＯＳＦＥＴ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏ
ｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎ
ｓｉｓｔｏｒ）の微細化と接合容量の低減化に関するも
のである。BACKGROUND OF THE INVENTION The present invention relates to a double gate MOSFET (Metal Oxide Semiconductor) formed on a silicon (Si) substrate among semiconductor devices.
nductor Field Effect Tran
The present invention relates to the miniaturization of the system and the reduction of the junction capacitance.
【０００２】[0002]
【従来の技術】従来のこの種の半導体装置の主要部の断
面図を図２に示し、以下に説明する。周知のように、ダ
ブルゲートのＭＯＳＦＥＴの構造は、同図に示すよう
に、半導体基板（Ｐ型シリコン基板、以下単に基板と称
す）１上にＰ型ウェル２が形成されており、その上に素
子分離絶縁膜３で分離された能動素子形成領域上にゲー
ト絶縁膜５が形成され、その上に２個の平行するゲート
６が形成されており（そのゲート６の側壁には一般にサ
イドウォール８が設けられている）、そのゲート６の間
及び両側の前記Ｐウェル２中にソース、ドレインとして
の不純物拡散層９が形成されている。2. Description of the Related Art A sectional view of a main portion of a conventional semiconductor device of this type is shown in FIG. 2 and will be described below. As is well known, in the structure of a double-gate MOSFET, a P-type well 2 is formed on a semiconductor substrate (P-type silicon substrate, hereinafter simply referred to as a substrate) 1 as shown in FIG. A gate insulating film 5 is formed on the active element formation region separated by the element isolation insulating film 3, and two parallel gates 6 are formed on the gate insulating film 5 (side walls of the gate 6 are generally sidewalls 8). Is provided), and an impurity diffusion layer 9 as a source and a drain is formed between the gates 6 and in the P well 2 on both sides thereof.
【０００３】この拡散層９は最近のこの種の構造では、
図２に示すように高濃度不純物層（ｎ+ 層）と低濃度不
純物層（ｎ- 層）とから形成されている。いわゆるＬＤ
Ｄ（Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒａｉｎ）構造で
ある。また、この２個のゲート６は図示してないが電気
的に接続されている。つまり、２個のＬＤＤ型ＭＯＳＦ
ＥＴをいわば直列に接続して一つのＭＯＳＦＥＴの機能
をもたせたものである。そこからダブルゲートＭＯＳＦ
ＥＴと称されている。This diffusion layer 9 has the following structure in recent years.
As shown in FIG. 2, it is formed of a high concentration impurity layer (n + layer) and a low concentration impurity layer (n − layer). So-called LD
It is a D (Lightly Doped Drain) structure. Although not shown, the two gates 6 are electrically connected. That is, two LDD type MOSF
The ETs are connected in series, so to speak, to have the function of one MOSFET. From there double gate MOSF
It is called ET.
【０００４】このような構造とした理由は、周知のよう
にホットキャリア効果を緩和するためであり、ホットキ
ャリアの生成が少ないほど寿命を長くできる。The reason for adopting such a structure is to alleviate the hot carrier effect, as is well known, and the shorter the generation of hot carriers, the longer the life.
【０００５】従来のこの構造においては、前述したよう
に２個のゲート６の間にも高濃度の不純物拡散層
（ｎ+ ）９が存在している。In this conventional structure, as described above, the high-concentration impurity diffusion layer (n + ) 9 also exists between the two gates 6.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、前述し
た構造では、２個のゲートの間にも不純物濃度の濃い領
域（ｎ+ ）が存在するために、基板との接合容量が増加
するという問題点があった。However, in the above-mentioned structure, since the region (n + ) having a high impurity concentration exists between the two gates, the junction capacitance with the substrate increases. was there.
【０００７】また、この領域の存在のために、微細化す
る点においても不利であるという問題点があった。Further, due to the existence of this region, there is a problem that it is disadvantageous in terms of miniaturization.
【０００８】この発明は、以上述べたゲート間に高濃度
不純物拡散層（ｎ+ ）が存在することにより接合容量が
増加する点と微細化に不利である点とを除去するため、
２個のゲートをより接近させて形成し、そのゲート間で
サイドウォールを接触させるようにして、ゲート間の高
濃度不純物層をなくすようにすることにより、接合容量
を低減し、合わせて微細化をし易くすることを目的とす
る。The present invention eliminates the point that the junction capacitance increases due to the presence of the high-concentration impurity diffusion layer (n + ) between the gates and the point that is disadvantageous in miniaturization as described above.
By forming two gates closer to each other and contacting the sidewalls between the gates to eliminate the high-concentration impurity layer between the gates, the junction capacitance is reduced, and the miniaturization is also performed. The purpose is to facilitate.
【０００９】[0009]
【課題を解決するための手段】この発明は、前述した目
的達成のため、２個のゲートをより接近させて、両ゲー
トのサイドウォールを接触させて（というよりつなげ
て）、２個のゲート間から基板（Ｐウェル層、ゲート酸
化膜を含めて）が露出しないようにして、それによりゲ
ート間の高濃度不純物の拡散を抑えるようにして、ゲー
ト間は低濃度不純物層のみとしたものである。SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention provides two gates by bringing two gates closer to each other and contacting (or rather connecting) the sidewalls of both gates. The substrate (including the P well layer and the gate oxide film) is not exposed from the space, thereby suppressing the diffusion of high-concentration impurities between the gates, and only the low-concentration impurity layer is provided between the gates. is there.
【００１０】[0010]
【作用】この発明は、前述したように、２個のゲートを
より接近させて、両ゲートのサイドウォールをつなげ
て、ゲート間から基板が露出しないようにすることによ
り、ゲート間の基板に高濃度の不純物層が形成されない
ようにしたので、基板との接合容量が少なくなり、か
つ、微細化にも有利となる。As described above, according to the present invention, the two gates are brought closer to each other and the sidewalls of both gates are connected to each other so that the substrate is not exposed from between the gates. Since the impurity layer having a high concentration is not formed, the junction capacitance with the substrate is reduced and it is advantageous for miniaturization.
【００１１】[0011]
【実施例】図１に本発明の実施例の製造工程を示し、以
下に説明する。EXAMPLE A manufacturing process of an example of the present invention is shown in FIG. 1 and will be described below.
【００１２】まず、図１ (ａ）に示すように、Ｐ型シリ
コン基板（以下単に基板と称す）１に、Ｐ型不純物濃度
が基板１より濃いＰウェル２を形成し、例えばＬＯＣＯ
Ｓ（Ｌｏｃａｌ Ｏｘｉｄａｔｉｏｎ ｏｆ Ｓｉｌｉ
ｃｏｎ）法により素子分離領域（酸化膜）３を形成し、
能動素子領域４を絶縁分離する。その能動素子領域４上
にゲート酸化膜５を形成する。ここまでは従来の製造工
程と同様である。First, as shown in FIG. 1A, a P-well 2 having a P-type impurity concentration higher than that of the substrate 1 is formed on a P-type silicon substrate (hereinafter simply referred to as a substrate) 1.
S (Local Oxidation of Sili)
element isolation region (oxide film) 3 is formed by the
The active element region 4 is isolated. A gate oxide film 5 is formed on the active element region 4. The process up to this point is the same as the conventional manufacturing process.
【００１３】次に、図１ (ｂ）に示すように、２個のゲ
ート６を、例えばゲート長が０．５μｍであれば、それ
に対して０．２μｍ程度の狭い間隔で形成して、両ゲー
ト６をマスクにして、ｎ型の不純物を低ドーズ量でイン
プラ（イオン注入）して低濃度不純物拡散層（ｎ- ）７
を形成する（いわゆるＬＤＤである）。Next, as shown in FIG. 1B, two gates 6 are formed at a narrow interval of about 0.2 μm, for example, if the gate length is 0.5 μm. Using the gate 6 as a mask, n-type impurities are implanted (ion-implanted) at a low dose to form a low-concentration impurity diffusion layer (n − ) 7
Are formed (so-called LDD).
【００１４】次いで、図１（ｃ）のように、全面にサイ
ドウォール形成のための絶縁膜ＮＳＧ（Ｎｏｎ Ｄｏｐ
ｅｄ Ｓｉｌｉｃａｔｅ Ｇｌａｓｓ）８を堆積させ、
図１(ｄ）に示すように、２個のゲート６の間にある前
記ＮＳＧ８がすべてエッチングされない程度に、ドライ
エッチングにより異方性エッチングしてサイドウォール
（ＮＳＧ）８を形成する。このとき、ゲート６間のＮＳ
Ｇ８はゲート酸化膜５までエッチングされずに残る。こ
のためには、２個のゲート６の間隔をＬとすれば、ゲー
ト６間のＮＳＧ８の膜厚はＬ／２以上となるようにすれ
ばよい。Next, as shown in FIG. 1C, an insulating film NSG (Non Dop) for forming sidewalls is formed on the entire surface.
ed Silicate Glass) 8 is deposited,
As shown in FIG. 1D, the sidewalls (NSG) 8 are formed by anisotropic etching by dry etching to the extent that the NSGs 8 between the two gates 6 are not all etched. At this time, NS between the gates 6
G8 remains without being etched up to the gate oxide film 5. For this purpose, if the distance between the two gates 6 is L, the film thickness of the NSG 8 between the gates 6 may be L / 2 or more.
【００１５】その後、図１ (ｅ）に示すように、前記ゲ
ート６およびサイドウォール８をマスクにして、高ドー
ズ量でｎ型不純物層（ｎ+ ）９を形成する。このとき、
ゲート６間には前述したようにＮＳＧ膜８があるので、
そこでは高濃度不純物のインプラは抑えられてｎ+ 拡散
層は形成されない。Thereafter, as shown in FIG. 1E, an n-type impurity layer (n + ) 9 is formed with a high dose using the gate 6 and the sidewall 8 as a mask. At this time,
Since the NSG film 8 is provided between the gates 6 as described above,
There, implantation of high-concentration impurities is suppressed and the n + diffusion layer is not formed.
【００１６】なお、この高濃度不純物のインプラは、２
個のゲート６上をレジストで覆ってそれをマスクにして
行なってもよい。Incidentally, this high-impurity impurity implantation is 2
Alternatively, the gates 6 may be covered with a resist and used as a mask.
【００１７】即ち、ゲート６間には高濃度不純物層（ｎ
+ ）がなく、低濃度不純物層のみのダブルゲートＭＯＳ
ＦＥＴができあがるのである。That is, a high concentration impurity layer (n
Double gate MOS without + ) and only low concentration impurity layer
The FET is completed.
【００１８】[0018]
【発明の効果】以上説明したように、本発明によれば、
ダブルゲートＭＯＳＦＥＴにおいて、２個のゲート間の
間隔をより狭くし、かつ、そのゲート間に絶縁膜を存在
させるようにして、その部分に高濃度不純物拡散層（ｎ
+ ）を形成しないようにしたので、その部分における基
板との接合容量が低減され、また、ゲート間隔が従来よ
り短い分、微細化に有利となる。As described above, according to the present invention,
In a double-gate MOSFET, the distance between two gates is made narrower, and an insulating film is present between the gates, and a high-concentration impurity diffusion layer (n
Since the + ) is not formed, the junction capacitance with the substrate in that portion is reduced, and since the gate interval is shorter than in the conventional case, it is advantageous for miniaturization.
【図１】本発明の実施例FIG. 1 Example of the present invention
【図２】従来例FIG. 2 Conventional example
１ Ｐ型シリコン基板 ２ Ｐウェル ３ 素子分離領域 ４ 能動素子領域 ５ ゲート酸化膜 ６ ゲート ７ 低濃度不純物層 ８ ＮＳＧ ９ 高濃度不純物層 1 P-type silicon substrate 2 P well 3 Element isolation region 4 Active element region 5 Gate oxide film 6 Gate 7 Low concentration impurity layer 8 NSG 9 High concentration impurity layer
Claims (3)
に、ダブルゲートＭＯＳＦＥＴとしての２個のゲートを
形成する工程、 （ｂ）前記２個のゲートをマスクにして、不純物拡散層
を形成する工程、 （ｃ）前記ゲートのサイドウォールを形成するための絶
縁膜を形成し、前記２個のゲート間において下地が露出
しないよう該絶縁膜が所定の厚さで残るようにサイドウ
ォールを形成する工程、 （ｄ）前記ゲートおよびサイドウォールをマスクにし
て、前記不純物拡散層より高濃度の不純物拡散層を形成
する工程、 以上の工程を含むことを特徴とするダブルゲートＭＯＳ
ＦＥＴの製造方法。1. (a) A step of forming two gates as a double gate MOSFET in one active element region on a semiconductor substrate, (b) An impurity diffusion layer is formed by using the two gates as a mask. And (c) forming an insulating film for forming the side wall of the gate, and forming a side wall so that the insulating film remains with a predetermined thickness so that the base is not exposed between the two gates. And (d) a step of forming an impurity diffusion layer having a higher concentration than the impurity diffusion layer by using the gate and the sidewall as a mask, the double gate MOS including the above steps.
Method of manufacturing FET.
記２個のゲートの間隔の長さの１／２以上であることを
特徴とする請求項１記載のダブルゲートＭＯＳＦＥＴの
製造方法。2. The method for manufacturing a double-gate MOSFET according to claim 1, wherein the thickness of the insulating film left between the gates is ½ or more of the length of the distance between the two gates. .
て、その構成要素である２個のゲート間の不純物拡散層
が、該ゲートの両側に形成されている所定の不純物拡散
層より低濃度の不純物拡散層のみであることを特徴とす
るダブルゲートＭＯＳＦＥＴ。3. As a structure of a double gate MOSFET, an impurity diffusion layer between two gates, which is a constituent element of the double gate MOSFET, is only an impurity diffusion layer having a lower concentration than a predetermined impurity diffusion layer formed on both sides of the gate. A double-gate MOSFET characterized in that
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01551493A JP3320476B2 (en) | 1993-02-02 | 1993-02-02 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01551493A JP3320476B2 (en) | 1993-02-02 | 1993-02-02 | Method for manufacturing semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001190605A Division JP2002057221A (en) | 2001-06-25 | 2001-06-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06232407A true JPH06232407A (en) | 1994-08-19 |
| JP3320476B2 JP3320476B2 (en) | 2002-09-03 |
Family
ID=11890933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01551493A Expired - Fee Related JP3320476B2 (en) | 1993-02-02 | 1993-02-02 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3320476B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127224A (en) * | 1997-12-31 | 2000-10-03 | Stmicroelectronics, S.R.L. | Process for forming a non-volatile memory cell with silicided contacts |
| US6392279B1 (en) * | 1997-06-11 | 2002-05-21 | Fujitsu Limited | Semiconductor device having LDD structure adapted to lower parasitic capacitance and parasitic resistance |
| JP2009152559A (en) * | 2007-11-27 | 2009-07-09 | Toshiba Corp | Semiconductor device |
-
1993
- 1993-02-02 JP JP01551493A patent/JP3320476B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6392279B1 (en) * | 1997-06-11 | 2002-05-21 | Fujitsu Limited | Semiconductor device having LDD structure adapted to lower parasitic capacitance and parasitic resistance |
| US6127224A (en) * | 1997-12-31 | 2000-10-03 | Stmicroelectronics, S.R.L. | Process for forming a non-volatile memory cell with silicided contacts |
| US6437393B1 (en) | 1997-12-31 | 2002-08-20 | Stmicroelectronics S.R.L. | Non-volatile memory cell with silicided contacts |
| JP2009152559A (en) * | 2007-11-27 | 2009-07-09 | Toshiba Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3320476B2 (en) | 2002-09-03 |
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