JPH06232375A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a semiconductor storage device which is constituted by using a TFT, and can reduce the size of a memory cell and the whole size of a chip. CONSTITUTION:As shown in the Figure (a), a plurality of stripe type diffusion layers SL stretching in the transversal direction are arranged on the surface of a semiconductor substrate. A plurality of stripe type TFT bodies TB stretching in the longitudinal direction are arranged. At the portions of the TFT bodies TB intersecting the diffusion layers SL, sources and drains are alternately formed. An island type contact pad CP is formed on the drain D. As shown. in the Figure (b), bit lines BL are arranged in a stripe type along the TFT bodies TB. The bit lines BL are connected with contact pads CP arranged in the longitudinal direction, via third contact holes C2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, it relates to a flash memory, an EPROM, etc. which are constructed by using a TFT (thin film transistor).

[0002]

2. Description of the Related Art Conventionally, there are semiconductor memory devices constructed by using TFTs as shown in FIGS. 5 (a), 5 (b), 6 and 7. 5 (a) and 5 (b) are pattern layouts
(Actually, the pattern of FIG. 6 (a) overlaps the pattern of FIG. 6 (a)), and FIGS. 6 and 7 are cross-sectional views taken along line VI-VI in FIG. 5 (patterns overlapping). , VII-VII line cross section is shown. As shown in FIG. 6, this semiconductor memory device includes an insulating film (provided on a semiconductor substrate (not shown)).
A TFT body TB formed of a stripe-shaped polycrystalline silicon film 102 is provided on 101. TFT body T
A source S and a drain D are formed on B. Also,
A control gate CG extending in a stripe shape in a direction orthogonal to the TFT body TB, a floating gate FG existing between TB and CG at the intersection of TB-CG, and a stripe shape between the control gates CG and CG. To a source S through a contact hole C1. A contact pad CP having an island pattern (see FIG. 5A) is provided on the drain D. The bit line BL is
The TFT body TB is overlapped and extends in a stripe shape, and is connected to the contact pad CP through a contact hole C2 provided in the interlayer insulating film 109.

As shown in FIG. 5A, the source S and drain D of each TFT (which constitutes a memory cell) are arranged side by side in a row, and as a result, the contact pad CP is also provided. They are arranged in a row in the horizontal direction. Also, the same figure
As shown in (b), a portion of the bit line BL covering the contact pad CP is wider in the lateral direction (in FIG. 5) than other portions. As a result, an alignment margin of Ma is set for the contact hole C2. Wc is the minimum contact diameter, and Sm is the minimum space between the bit lines BL.

This semiconductor memory device is manufactured as follows. First, as shown in FIG. 6, a polycrystalline silicon film 102 having a thickness of 1000 Å and a gate oxide film 103 having a thickness of 100 Å are formed on an oxide film (a thickness of 4000 Å) 101.
Then, a polycrystalline silicon film 104 having a thickness of 1000 Å is sequentially deposited, and these films 104, 103 and 102 are patterned into stripes to form a TFT body TB. Next, on the entire surface, an ONO film (HTO (high tempera- ture oxide) with a thickness of 100Å, SiN with a thickness of 200Å, and a thickness of 1)
105 made of HTO of 00Å and conductive film (thickness 100)
A 0Å polycrystalline silicon film and a 1000Å-thick WSi film 106) and a 1000Å-thick oxide film 107 are sequentially deposited. Then, these films 107, 106, 105 and the polycrystalline silicon film 104 are patterned into a stripe shape to form a control gate CG with the conductive film 106 in a stripe shape, and the polycrystalline silicon film having a rectangular shape is formed. The film 104 constitutes the floating gate FG. The floating gate FG is formed in a self-alignment manner with respect to the TFT body TB in the horizontal direction and the control gate CG in the vertical direction in FIG. Next, as shown in FIG. 6, the control gate C
As ions are implanted using G as a mask to form a source S and a drain D in the polycrystalline silicon film 102 (TFT body TB). Next, after forming the contact hole C1 on the source S and the drain D, a polycrystalline silicon film having a thickness of 2000 Å is deposited on the entire surface, and the polycrystalline silicon film is patterned to form the source line SL 'and the contact pad CP. To form. Next, an interlayer insulating film (made of SiO _{2 having} a thickness of 1000 Å and BPSG (boron phosphorus silicate glass) having a thickness of 5000 Å) 109 is deposited. Next, after forming a contact hole C2 on the contact pad CP, an AlSi film having a thickness of 5000Å is provided on the entire surface.
Patterning the lSi film to form bit lines BL
(Completed).

[0005]

In the above conventional semiconductor memory device, since the adjacent TFT bodies TB are separated by patterning, unlike the case where elements are directly formed on the semiconductor substrate surface, LOCOS
It is not necessary to provide an element isolation region such as a (local oxidation of silicon) region. Therefore, the size of the memory cell can be made relatively small.

However, in the conventional semiconductor memory device described above, as shown in FIGS.
One P is arranged in one row in the horizontal direction for each memory cell. As a result, as shown in FIG. 5 (b), the cell size Wcell in the lateral direction is Wcell = Wc + 2Ma + Sm (1). As described above, Wc is the minimum contact diameter, Ma is the alignment margin between the contact hole C2 and the bit line BL, and Sm is the bit line B.
The minimum space between L is shown. In this way, a double alignment margin 2Ma is taken per cell in the horizontal direction. Therefore, it is considered that this semiconductor memory device has room for further reducing the size of the memory cell.

Therefore, an object of the present invention is to provide a semiconductor memory device constituted by using a TFT, which can reduce the size of a memory cell and therefore the entire chip size. is there.

[0008]

To achieve the above object, a semiconductor memory device of the present invention is provided with a plurality of stripe-shaped diffusion layers formed on the surface of a semiconductor substrate and extending in a first direction, and a first insulating layer. Provided on the surface of the substrate through a film,
A plurality of stripe-shaped TFT bodies extending in a second direction perpendicular to the first direction, and a plurality of stripe-shaped TFT bodies are formed at every other location in the TFT body intersecting with the diffusion layer. A source connected to the diffusion layer through a provided first contact hole and the source are alternately formed at a portion of the TFT body that intersects the diffusion layer, and are insulated from the diffusion layer by the first insulating film. And an island-shaped floating gate provided via a second insulating film on a channel region between the drain and the source and drain of the TFT body which are adjacent to each other in the second direction. A capacitor provided in a stripe shape along the diffusion layer on a region between the diffusion layers and covering the floating gates arranged in the first direction through a third insulating film. A roll gate, a contact pad that is provided in an island shape on each of the drains via a fourth insulating film and is connected to the drain through a second contact hole provided in the fourth insulating film, and the TFT body The control gate and the contact pad are provided in stripes along the TFT body via the fifth insulating film, and through the third contact hole provided in the fifth insulating film, the second insulating film is formed. It is characterized in that it is provided with a bit line connected to each of the contact pads arranged in the direction of.

[0009]

In the semiconductor memory device of the present invention, every other source and drain are alternately formed at the intersection of the diffusion body extending in the first direction in the TFT body extending in the second direction in a stripe shape. Has been done. As a result, the island-shaped contact pads on the drain are
The layout is such that one memory cell is arranged for every two memory cells in the first direction (one memory cell is conventionally provided for each memory cell). Therefore, the alignment margin required between the second contact hole and the bit line per cell is half that of the conventional one (details will be described later).
The cell size in the first direction is reduced by that amount.
Therefore, the chip size of the entire semiconductor memory device is also reduced.

[0010]

Embodiments of the semiconductor memory device of the present invention will be described in detail below.

FIGS. 1A and 1B show a pattern layout of a semiconductor memory device of one embodiment (actually, the pattern of FIG. 1B overlaps the pattern of FIG. 1A). , Fig. 1 and Fig. 2 are II-II in Fig. 1 (those with overlapping patterns).
A line section and a III-III line section are shown.

As shown in FIG. 2, this semiconductor memory device has a plurality of diffusion layers SL formed on the surface of a semiconductor substrate 30.
Is equipped with. The diffusion layer SL, as shown in FIG.
It extends in a stripe shape in a first direction (hereinafter referred to as “lateral direction”). Further, as shown in FIG. 2, a plurality of T's are formed on the surface of the substrate 30 with the oxide film 1 as the first insulating film interposed therebetween.
An FT body TB is provided. As shown in FIG. 1A, the TFT body TB extends in the second direction (hereinafter referred to as “vertical direction”). Diffusion layer S of TFT body TB
Sources S are formed at every other location where L intersects, and drains D are formed alternately with the sources S. Figure 2
As shown in, the source S is connected to the diffusion layer SL through the first contact hole C0 provided in the oxide film 1, while the drain D is insulated from the diffusion layer SL by the oxide film 1. An island-shaped floating gate FG is provided on the channel region between the source S and the drain D, which are vertically adjacent to each other in the TFT body TB, with the gate oxide film 3 as the second insulating film interposed therebetween. . A control gate CG is provided so as to cover the floating gate FG via an ONO film (three-layer film made of HTO, SiN, HTO) 5 as a third insulating film. Figure 1
As shown in (a), the control gate CG is provided in a stripe shape along the diffusion layer SL on the region between the adjacent diffusion layers SL. As shown in FIG. 2, contact pads CP are provided in an island shape on each drain D via the SiO ₂ film 7 as the fourth insulating film. The contact pad CP is connected to the drain D immediately below through the second contact hole C1 provided in the SiO ₂ film 7. TFT body TB, control gate CG
And on the contact pad CP, a fifth insulating film (Si
A bit line BL is provided via an interlayer insulating film 9 made of O ₂ and BPSG. Bit line BL is TF
Stripes are provided along the T body TB, and are connected to the contact pads CP arranged in the vertical direction through the third contact holes C2 provided in the interlayer insulating film 9. As shown in FIG. 1B, the portion of the bit line BL which covers the contact pad CP is wider in the lateral direction than the other portions. As a result, an alignment margin of Ma is set for the contact hole C2. Wc is the minimum contact diameter, Sm is the bit line B
The minimum space between L is shown.

In this semiconductor memory device, the layout is such that one contact pad CP is arranged in the horizontal direction for every two memory cells (one contact pad CP was conventionally provided for each memory cell). As a result, the horizontal cell size Wcel
l is Wcell = Wc + Ma + Sm (2). In other words, the alignment margin required between the second contact hole C1 and the bit line BL per cell is Ma, which is half that in the conventional case. Therefore, the cell size in the horizontal direction can be reduced accordingly. As a result, the chip size of the entire semiconductor memory device can be reduced.

This semiconductor memory device is manufactured as follows.

First, as shown in FIG. 4A, a resist pattern for the diffusion layer SL is formed on the surface of the P-type silicon substrate 30 by photolithography (a pattern in which the resist is removed only in the region where the diffusion layer SL is to be provided). (Not shown)
Then, using the resist pattern as a mask, As ions are implanted under the conditions of an acceleration energy of 50 keV and a dose amount of 1 × 10 ¹⁵ ions / cm ² to form a diffusion layer SL.

Next, the oxide film 1 having a thickness of 500Å is formed on the surface of the substrate 30 by thermal oxidation. Photolithography and etching are performed to form a first contact hole C0 at a predetermined portion (see FIG. 1A) on the diffusion layer 1 in the oxide film 1.

Next, as shown in FIG. 4 (b),
A 500 Å thick polycrystalline silicon film 2, a 100 Å thick gate oxide film 3, and a 500 Å thick polycrystalline silicon film 4
Are sequentially deposited, and these films 4, 3 and 2 are patterned in the lateral direction (first direction) in a stripe shape. The striped polycrystalline silicon film 2 constitutes the TFT body TB.

Next, as shown in FIG. 4 (c),
ONO film (100 Å thick HTO, 100 Å thick SiN,
5 made of HTO with a thickness of 100Å and conductive film (thickness of 10)
A polycrystalline silicon film of 00Å and a WSi film of 1000Å in thickness 6) and a SiO ₂ film 7 of 1000Å in thickness are sequentially deposited. Then, these films 7, 6 and 5 and the polycrystalline silicon film 4 are patterned in a stripe shape in the vertical direction (second direction). The stripe-shaped conductive film 6 constitutes the control gate CG, and the rectangular polycrystalline silicon film 4 constitutes the floating gate FG. The floating gate FG is T in the horizontal direction in FIG.
The FT body TB and the control gate CG are formed vertically in a self-aligned manner.

Next, as shown in FIG. 4 (c), using the control gate CG as a mask, As ions are implanted under the conditions of an acceleration energy of 50 keV and a dose amount of 1 × 10 ¹⁵ ions / cm ² to form polycrystalline silicon. A source S and a drain D are formed in the film 2 (TFT body TB).

Next, as shown in FIG. 4D, the thickness 50
A 0Å SiO ₂ film (illustrated integrally with the SiO ₂ film 7) is deposited, and a contact hole C1 is formed in a portion of the SiO ₂ film 7 on the drain D. After this, the entire thickness is 200
A 0Å polycrystal silicon film is deposited, and the polycrystal silicon film is patterned to form a contact pad CP on the drain D.

Next, as shown in FIG.
9 (made of SiO _{2 having} a thickness of 1000 Å and BPSG having a thickness of 5000 Å) 9 is deposited, and a contact hole C 2 is formed in a portion of the interlayer insulating film 9 on the contact pad CP.
Then, a 5000Å thick AlSi film is provided on the entire surface, and the AlSi film is patterned to form the bit line BL (manufacturing is completed).

[0022]

As is apparent from the above, in the semiconductor memory device of the present invention, a plurality of stripe-shaped diffusion layers extending in the first direction are provided on the surface of the semiconductor substrate, and
A plurality of stripe-shaped TFT bodies extending in a second direction perpendicular to the first direction through the insulating film, and a source and a drain are respectively formed at the portions of the TFT body intersecting the diffusion layer. Since the contact pads are alternately formed and the island-shaped contact pads are provided on the drain, it is possible to arrange the contact pads in the first direction such that one memory cell is arranged every two memory cells. One was provided for each memory cell.). Therefore, the alignment margin required between the second contact hole and the bit line per cell can be halved as compared with the conventional case, and the cell size in the first direction can be reduced accordingly. be able to. Therefore,
The chip size of the entire semiconductor memory device can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a pattern layout of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a view showing a cross section taken along the line II-II in FIG.

3 is a view showing a cross section taken along the line III-III in FIG.

FIG. 4 is a diagram illustrating a manufacturing process of the semiconductor memory device.

FIG. 5 is a diagram showing a pattern layout of a conventional semiconductor memory device.

6 is a diagram showing a cross section taken along line VI-VI in FIG.

7 is a diagram showing a cross section taken along line VI-VI in FIG.

[Explanation of symbols]

 C0 First contact hole C1 Second contact hole C3 Third contact hole CG Control gate CP Contact pad D Drain FG Floating gate S Source SL Diffusion layer TB TFT body

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 29/792 H01L 29/78 371

Claims (1)

[Claims] 1. A plurality of stripe-shaped diffusion layers formed on a surface of a semiconductor substrate and extending in a first direction; and a diffusion layer provided on the surface of the substrate with a first insulating film interposed therebetween and being perpendicular to the first direction. A plurality of stripe-shaped TFT bodies extending in the second direction, and 1 at a portion of the TFT body that intersects the diffusion layer.
The first insulating film formed on every other side and provided on the first insulating film.
A source connected to the diffusion layer through the contact hole, and a drain alternately formed with the source at a portion of the TFT body that intersects the diffusion layer and insulated from the diffusion layer by the first insulating film. Between the island-shaped floating gate provided via the second insulating film on the channel region between the source and the drain adjacent to each other in the second direction of the TFT body, and between the adjacent diffusion layers. Through a third insulating film, the control gates covering the floating gates arranged in the first direction, and the fourth insulating film. A contact pad provided in an island shape on each of the drains and connected to the drain through a second contact hole provided in the fourth insulating film; On the TFT body, the control gate and the contact pad, provided in a stripe shape along the TFT body via the fifth insulating film, and through the third contact hole provided in the fifth insulating film, A semiconductor memory device comprising: bit lines connected to the contact pads arranged in the second direction.