JPH06231595A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the lowering of bit line potential VBL due to a failure in a memory cell section at the time of pre-charge even when there is such a failure. CONSTITUTION:A MOSFET T4 is connected at one end sides of each bit-line pair BL,-BL of a memory cell section A. MOSFET T5, T6 are connected on the other end sides of said each bit-line pair BL,-BL. A control circuit is bonded with the gates of said MOSFETs T4-T6. The control circuit electrically interrupt the bit-line pair, in which there is a defective memory cell, from other bit-line pairs at the time of the pre-charge of bit lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to means for preventing a decrease in bit line potential due to a defective memory cell in a semiconductor memory such as a large scale integrated circuit.

[0002]

2. Description of the Related Art Conventionally, in the field of semiconductor memory, particularly in a dynamic RAM (hereinafter referred to as DRAM), at the time of precharging a bit line, the potential of the bit line is half the power supply potential Vcc, that is, Vcc / 2. Has been charged (equalized).

FIG. 4 shows a circuit configuration near a conventional memory cell portion. In this circuit, the memory cell section
A bit line precharge portion B is arranged at one end side of the pair of bit lines BL and / BL in A, and a sense amplifier portion C is arranged at the other end side. In addition,
In the memory cell portion A, although not shown, the memory cell is connected to the bit lines BL and / BL.

In the circuit of FIG. 4, the potential VBL is a potential given from a bit line potential generation circuit (generally called an intermediate potential generation circuit) inside the chip.
The configuration of the bit line potential generation circuit is, for example, U.
S. P. Since it is known as disclosed in US Pat. No. 4,663,584, it will not be described in detail here.

The operation of the bit line precharge section B of FIG. 4 will be briefly described. When a signal that changes / RAS from "L" to "H" is given from the external terminal, the internal signal / E
QL changes from "L" to "H". As a result, the transistors T1 to T3 are turned on, and the bit line B
The potentials of L and / BL are equalized to Vcc / 2.

However, the circuit shown in FIG. 4 has the following drawbacks. That is, as shown in FIG. 5, due to some cause, a leak path is generated in the bit lines BL, / BL, for example, a minute leak current is generated between the word line WL and the bit lines BL, / BL. Then, the memory cell may cause a malfunction. Such a defect can be relieved by a redundant circuit, and if relieved, there will be no functional (AC) problem. However, in terms of DC, even if the defect is remedied by a redundant circuit, the leak path of the defective portion still exists.

As a result, there is a drawback that the actual standby current in the memory cell section becomes larger than the designed value. Also, because the potential VBL becomes lower than the design value, VBL
Margin is significantly reduced. This decrease in VBL margin has become a more serious problem with the increase in memory capacity in recent years.

That is, due to the increase in the capacity of the memory, the power supply voltage is lowered (for example, 5V) from the viewpoint of ensuring reliability.
This is because the 3.3V) is closed up. If there is a leak path in lowering the power supply voltage, the problem is that the lowering of the VBL margin due to the lowering of the voltage is a problem from the beginning, and the lowering of VBL due to the leaking path further causes the VBL margin. Is reduced.

[0009]

As described above, the prior art is as follows.
Due to the leak path in the memory cell section and the recent decrease in the power supply voltage, the VBL margin is remarkably reduced, which causes malfunction of the semiconductor memory.

The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a memory cell portion having a defect.
Bit line potential V during precharge due to the defect
It is to provide a semiconductor memory capable of preventing a decrease in BL.

[0011]

To achieve the above object, a semiconductor memory according to the present invention comprises a first switch circuit connected to one end side of each bit line pair in a memory cell section,
A second switch circuit connected to the other end of each of the bit line pairs and the first and second switch circuits are connected to control the first and second switch circuits. It is provided with a control circuit capable of electrically disconnecting a bit line pair having a defective memory cell from another bit line pair during line precharge.

[0012]

According to the above construction, during the bit line precharge, the control circuit controls the first and second switch circuits to electrically connect the bit line pair having the defective memory cell from the other bit line pair. Can be shut off. That is, since the portion where the leak path occurs is isolated, it is possible to prevent the potential VBL of the other bit lines from decreasing.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a semiconductor memory according to an embodiment of the present invention. In addition, FIG. 2 shows an example of a circuit for generating the signal / RPL in FIG.

In FIG. 1, A is a memory cell section, and B is
Is a bit line precharge section, and C is a sense amplifier section. The memory cell portion A, the bit line precharge portion B, and the sense amplifier portion C have the same configurations as in the conventional case.

First, a transistor T is provided between the bit line precharge section B and the bit line potential generating circuit (not shown).
4 is connected. The REPLACE signal / RPL is input to the gate of the transistor T4. On / off of the transistor T4 is controlled by this REPLACE signal / RPL. On the other hand, transistors T5 and T6 are connected between the memory cell section A and the sense amplifier section C. The gate of the transistors T5 and T6 is the same as the signal input to the gate of the transistor T4.
REPLACE signal / RPL is input. The transistors T5 and T6 are on / off controlled by the REPLACE signal / RPL.

The REPLACE signal / RPL is provided by the COLUMN KILL DECODER circuit shown in FIG. In FIG. 2, 11 is P
Channel MOSFET, 12 is a fuse, 13 is a resistor, 14 and 15 are inverters, and 16 and 17 are N
AND gates 18 to 20 are inverters. A column kill decoder circuit is provided corresponding to each address of the semiconductor memory, and by cutting the fuse 12 of the circuit, the address Aik is activated.

The operation of the semiconductor memory of FIG. 2 will be briefly described. REPLACE on the gate of transistors T4 to T6
When the signal / RPL is applied, the transistor T4
~ T6 is turned off. As a result, the memory cell section A and the bit line potential generation circuit (potential VBL) are in a non-connection relationship, and the memory cell section A and the sense amplifier section C are in a non-connection relationship. As a result, the bit line pair BL, / BL in which the defective memory cell exists is brought into a floating state and electrically isolated from the other bit line pair BL, / BL.

As a result, for example, as shown in FIG. 3, even if the memory cell portion A has a defect, the switch circuit S1 is turned off in the bit line (for example, BL1) in which the defective memory cell exists. Other bit lines BL2, B
Separated from L3 ... Therefore, at the time of bit line precharge, another bit line BL due to the defect is
It is possible to prevent a decrease in the potential VBL of 2, BL3 ... and to secure VBL margin.

[0019]

As described above, the semiconductor memory of the present invention has the following effects. A switch element is connected between each bit line pair of the bit line precharge section B and the bit line potential generation circuit (VBL potential). By controlling this switch element, the bit line pair in which the defective memory cell exists can be isolated from other bit line pairs. Therefore, even if the memory cell portion has a defect, it is possible to prevent the potential VBL of the bit line pair BL, / BL having a normal memory cell from being lowered at the time of precharge due to the defect. The present invention can be effectively applied to the case where the memory cell array is divided into blocks and the repair unit by the redundancy circuit is performed for each block.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory according to an embodiment of the present invention.

FIG. 2 is a column kill decorator that provides the signal / RPL of FIG.
The circuit diagram which shows a da circuit.

FIG. 3 is a circuit diagram showing an application example of the semiconductor memory of FIG.

FIG. 4 is a circuit diagram showing a conventional semiconductor memory.

FIG. 5 is a circuit diagram showing a conventional semiconductor memory.

[Explanation of symbols]

 11 ... P-channel MOSFET, 12 ... Fuses, 13 ... Resistors, 14, 15, 18-20 ... Inverter, 16, 17 ... NAND gate, A ... Memory cell part, B ... Bit line precharge Section, C ... Sense amplifier section, T1 to T6 ... MOSFET (switch element)

Claims (1)

[Claims] 1. A first switch circuit connected to one end side of each bit line pair of the memory cell section, a second switch circuit connected to the other end side of each bit line pair, and By connecting the first and second switch circuits and controlling the first and second switch circuits, a bit line pair in which a defective memory cell exists at the time of precharging a bit line is changed from another bit line pair. A semiconductor memory comprising: a control circuit that can be electrically cut off.