JPH06230752A - Driving method for display device - Google Patents

Abstract

PURPOSE:To provide a driving method for the applied voltage of a display panel which displays multi-level expression with low crosstalk in a display device of STN system. CONSTITUTION:One horizontal period is divided uniformly by bit length (n) of gradation display in the display device of STN system provided with a display panel of simple matrix type and in which display luminance depends on the effective value of the applied voltage. The difference of voltage effective values on divided sections is set so as to become to density difference meant by a display bit by correlating the divided sections to the display bit and adjusting the impressed voltage value of the display panel in each divided section. In the figure, the size of the display panel is set at 4X4, and the driving pulse waveform of the voltage supplied to each electrode of the display panel is shown when four-gradation display is performed. A time is shown on the obscissa, and the voltage value of each electrode is shown on the ordinate in the figure. Therefore, since time division required for the display of gradation is performed by division into equal parts, the minimum time interval generated by such division can be extended, and since only small number of frequency band areas are used, the crosstalk is reduced, and a virtual image and flickering on a display screen are suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive system of a display device, and more particularly to a drive method for realizing multi-gradation display in a simple matrix type display device.

[0002]

2. Description of the Related Art A conventional liquid crystal display device having a simple matrix type liquid crystal display panel is described in "Liquid Crystal Device Handbook", 6th edition, 142nd Committee, Japan Society for the Promotion of Science.
There is a voltage averaging drive system as described in Chapter 2
In addition, as a more generalized drive system, society,
Page 228 to 231 of the 1992 digest of fore, infomation, and display (Soci
ety for InformationDisplay 92 digest ； ”Active A
ddressing Method for High-Contrast Video-Rate STN
Displays ”; pp.228-231) .A pulse width modulation gradation display method (hereinafter referred to as a pulse width modulation method) is known as a method for adding display gradation.

A conventional pulse width modulation method is disclosed in Japanese Patent Laid-Open No. 59-59.
As disclosed in Japanese Patent No. 149393, a uniform pulse width modulation method in which one horizontal period is time-divided evenly to perform gradation display, and one horizontal period as described in Japanese Unexamined Patent Publication No. 52-76897 have time intervals. There is a weighted pulse width modulation method in which weighting is performed and division is performed. Also, US Pat. No. 4709
As described in No. 995, there is a pulse width modulation method in which one frame period is divided to obtain the same effect as that obtained by time division of one horizontal period.

The uniform pulse width modulation method and the weighted pulse width modulation method will be described below with reference to the drawings.

First, the structure of a simple matrix type liquid crystal display device will be described. FIG. 4 is a block diagram of a conventional liquid crystal display device, which includes a liquid crystal panel 100, an X drive circuit 101,
Y drive circuit 102, voltage generation circuit 103, timing signal generation circuit 104, display data control circuit 105, vertical synchronization signal input terminal 201, horizontal synchronization signal input terminal 20
2. A data clock input terminal 203 and a display data input terminal 204.

There are four types of input signals that the liquid crystal display device fetches from the outside: a vertical synchronizing signal, a horizontal synchronizing signal, a data clock, and display data. The vertical sync signal is a signal that signals the start of one screen, and the horizontal sync signal is a signal that signals the start of horizontal data transfer. The data clock is a clock synchronized with the display data sent,
The liquid crystal display device can take in the display data sent based on the data clock. The time from the horizontal sync signal to the next horizontal sync signal is called one horizontal period, and the time for transferring the information of one entire screen is called one frame period. When transferring one screen of data between the vertical synchronizing signal and the next vertical synchronizing signal, the time interval of the vertical synchronizing signal is 1
It becomes a frame period.

Now, the signal of the display data coming from the outside is 1
50 screens per second, the display screen matrix is N × M,
Consider a case where black and white grayscale data having M horizontal lines and n display grayscales are transferred in parallel for d bits. At this time, 1 frame period is 1/50 second, 1 horizontal period is 1 / (50 × M) second, and the data clock is d /
A synchronization signal will be generated in (50 × M × n) seconds.
The symbols N, M, n, and d used here will be used in the same definition hereinafter.

In the above-described specific example, a case has been described in which data for one screen is sent between the vertical synchronizing signal and the next vertical synchronizing signal. However, in the case of a television or the like, the interleave system is adopted and the vertical synchronizing signal is used. Only half screen information is sent from one signal to the next vertical sync signal. Therefore, the time from the vertical sync signal to the next vertical sync signal is 1
It becomes a frame period. In the above specific example, the information for 50 screens is sent per second. Therefore, the case of transmitting information for 50 screens per second in the above-described specific example corresponds to the case of transmitting information for half a screen 100 times per second in the interleave method.

Next, the function of each component of the liquid crystal display device and the flow of signals until display is performed will be described with reference to the block diagram of FIG. In the following, the Y direction is the horizontal direction,
The X direction will be described as a vertical direction.

The vertical synchronizing signal, the horizontal synchronizing signal, and the data clock are sent to the timing signal control circuit 104. The timing signal generation circuit 104 generates various synchronization signals that move each circuit based on the above signals. It also generates a basic pulse waveform driven by the Y drive circuit 102. Each circuit operates based on various synchronization signals sent from the timing signal generation circuit. The display data control circuit 105 takes in the display data based on the data clock sent from the timing signal generation circuit 104, and based on the taken display data and the basic pulse waveform sent from the timing signal control circuit 104, the X drive circuit. The pulse waveform driven by 102 is generated. The X drive circuit 102, based on the synchronization signal sent from the timing signal generation circuit 104,
The waveform data from the display data control circuit 105 is read and a voltage based on the waveform data is applied to the X electrodes of the display panel 100. The Y drive circuit 102, based on the synchronization signal sent from the timing signal generation circuit 104,
The basic waveform data is received from the timing signal generation circuit 104, and a voltage based on the basic waveform data is applied to the Y electrodes of the display panel 100. The voltage generation circuit 103
A desired plurality of voltages are supplied to the X drive circuit 101 and the Y drive circuit 102. The X drive circuit 101 and the Y drive circuit 102 are
A plurality of voltages sent from the voltage generation circuit 103 are switch-selected based on the respective waveform data, and a desired voltage can be applied to the liquid crystal panel 100 at a desired timing. The liquid crystal panel 100 forms a matrix of electric wires with electrodes in the X direction and electrodes in the Y direction, and includes a thin transparent glass plate in which electrodes in the X direction are arranged and a thin transparent glass plate in which electrodes in the Y direction are arranged. It has a structure with a thin liquid crystal layer in between. When there is a potential difference between the X-direction electrode and the Y-direction electrode, the potential difference is applied to the liquid crystal on the matrix intersection,
Luminance can be displayed from the change in light transmittance depending on the effective voltage value. FIG. 3 is a graph showing the relationship between the effective value of the voltage applied to the liquid crystal and the display brightness of the liquid crystal. V in FIG.
Between off and Von, a substantially linear luminance display is shown with respect to the voltage execution, and gradation is displayed with a difference in the voltage effective value in this section.

When the pulse waveforms generated by the X drive circuit and the Y drive circuit are appropriately selected, the effective voltage value on each matrix is
By averaging during one frame period, the effective voltage value according to the display brightness of each matrix is obtained. The difference between the various pulse width modulation methods for expressing gradation is in how to determine this pulse waveform.

The X drive circuit 101 and the Y drive circuit 10
The clock that determines the time interval of the pulse waveform driven by 2 will be referred to as a data latch clock.
In the case of 2-gradation display, the data latch clock has the same period as one horizontal period, but in the case of multi-gradation display, each characteristic time division depending on the pulse width modulation method causes a time shorter than 1 horizontal period. Issue interval data latch clock.

In addition to the above structure, in the liquid crystal display device, there may be a case where a mechanism is adopted in which the voltage applied to the liquid crystal is AC. The simplest method is to invert the positive and negative voltage polarities every frame. As a mechanism therefor, a mechanism for generating a command signal in the timing signal generation circuit 104 and inverting the voltage generated by the voltage generation circuit 103 for each frame is provided. The pulse waveform with positive and negative inversion can be easily estimated from the basic pulse waveform without positive and negative inversion. Therefore, in the following description, a pulse waveform that does not consider positive / negative inversion is used.

What is most important when performing gradation display by each conventional pulse width modulation method is what the drive pulse waveform looks like. The pulse waveform is illustrated with reference to FIGS. 5 to 9. In this case, it is assumed that the number of matrices on the display screen is 4 × 4 and 4 gradation display. That is, in the above symbol, N = M = 4 and gradation m = 4, and when the bit length expressing the gradation is n, then n = 2.

FIG. 5 is a display example in which the value of the display brightness of the image to be displayed is noted. 1 and 6 to 12
Using the drive pulse waveforms shown up to all, the image showing the density gradation of FIG. 5 can be obtained. 1 and 6 to 12, the horizontal axis represents time and the vertical axis represents the voltage value of each electrode of the liquid crystal panel 100. 6 to 9 relate to the prior art, and FIGS. 1 and 10 to 12 relate to the present invention.

6 and 7 show examples of conventional uniform pulse width modulation. In FIG. 6, one horizontal period is divided into three equal parts, and the time corresponding to the gradation is selected and applied according to each display gradation.
On the other hand, in the case of FIG. 7, one frame period is divided into three equal parts and divided into three fields, and the number of field periods to be applied is determined according to each display gradation. In either method, the voltage effective value at each point on the matrix has a value corresponding to the density gradation as an average within one horizontal period. It should be noted that FIGS. 6 and 7 become exactly the same when the temporal replacement is performed during one frame period. The characteristic of the uniform pulse width modulation is that when the gradation is m, time division is performed in m-1 equal parts.

8 and 9 are examples of conventional weighted pulse width modulation. In FIG. 8, one horizontal period is time-divided at a ratio of 1: 2. Since the time is divided into 1 to 2 according to the density level of the display bit, the bit of the display data corresponds to the divided time. It directly depends on the data of the display bit to decide whether or not to apply at the corresponding time. In FIG. 9, one frame period is divided into 1 to 2. 9 and 8 are the same when the time is replaced. 6 and FIG. 7, FIG. 8, and FIG. 9 are the same when the temporal replacement is performed, and the uniform pulse width modulation and the weighted pulse width modulation are the same for the temporal replacement, and the display bit is the same. The only difference is whether or not time division is made to depend directly on. Therefore, also in the case of the weighted pulse width modulation, the minimum division time is the same as that in the uniform pulse width modulation, which is a time obtained by equally dividing one frame period by m−1, and the frequency band to be used is also the same.

In order to describe the pulse waveform more generally, it will be described below using mathematical expressions.

First, in the case of uniform pulse width modulation,

[0020]

[Equation 1] Y (j, p, t) = a · φ (j, t) (Equation 1)

[0021]

[Equation 2] However, i and j mean the i-th row and the j-th column in the order of the matrix of the liquid crystal panel 100. The value of i is 1 to N
An integer up to. The value of j is an integer from 1 to M.

P is a number given to an interval divided into m-1 equal parts in order to express the density gradation of the display data. 1 to m
Takes an integer value up to -1.

T represents the time counted for each section divided into m-1 equal parts.

Y (j, p, t) means a voltage waveform generated by the j-th Y driving circuit at time t in the p-th divided section, and is a voltage waveform applied to the j-th row of the above matrix. .

X (i, p, t) means a voltage waveform generated by the i-th X driving circuit at time t in the p-th divided section, and is a voltage waveform applied to the i-th row of the matrix. .

A and b are constants.

I (i, j, p) is a value based on the display data,
It depends on the density level g (i, j) in the i-th row and j-th column of the matrix and the section number p. Concentration level g (i, j) from 0 to m-
When defined by an integer of 1, the value of I (i, j, p) is as follows.

[0028]

## EQU00003 ## I (i, j, p) =-1 (when p.ltoreq.g (i, j)) ... (Equation 3)

[0029]

## EQU00004 ## I (i, j, p) = 1 (when p> g (i, j)). (Equation 4) φ (j, t) is a basic pulse waveform. In the case of the uniform pulse width modulation method of FIGS. 6 and 7, since the voltage averaging driving method is used as the driving method, φ (j, t) is the following function.

[0030]

Φ (j, t) = 0 (when t <j−1, or t ≧ j) (Equation 5)

[0031]

## EQU00006 ## .phi. (J, t) = 1 (when j-1.ltoreq.t <j) (Equation 6) where t is a time interval based on a time interval obtained by equally dividing one horizontal period into m-1. Take 1 and count from 0, m-1
Defined as ending just before.

As the function system of φ (j, t), an orthogonal function with a constant norm can be used. A method using an orthogonal function with a constant norm is called an active drive method. That is, in the active drive system,

[0033]

[Equation 7] ∫dt φ (i, t) φ (j, t) = 0 (when i ≠ j)… (Equation 7)

[0034]

∫dt φ (i, t) φ (j, t) = const (constant) (when i = j) (Equation 8) However, the integration range is m− within one frame period.
It covers the entire one of the sections divided into equal parts.

The difference between FIG. 6 and FIG. 7 is only the difference in the order of application of X (i, p, t) and Y (j, p, t). It is easy to see that there are combinations.

Next, a pulse waveform is shown by a mathematical expression in the case of weighted pulse width modulation.

[0037]

[Equation 9] Y (j, k, t) = a · φ (j, t / (2 ** (n-k))) (Equation 9)

[0038]

[Equation 10] However, k is a bit order for expressing the density gradation of the display data, and means the k-th of the density gradation expression bits of n bits in total. At the lowest k = n, the density difference is smallest, and as k becomes smaller, the density difference widens by two.

The time division is such that at the lowest k = n, one horizontal period is divided into m-1 time intervals, and thereafter, each time k is decreased by 1, the time interval is doubled. To To express this change in time scale, φ
Notated as (j, t / (2 ** (nk))). However, 2 ** (nk) is 2
Of the time scale is t / (2 ** (nk)),
It means that the image is enlarged by 2 ** (nk) times.

Definitions of other symbols are the same as those in the equations 1 and 2.

The weighted pulse width modulation is different from the uniform pulse width modulation in that the waveform φ (j, t / (2 ** (nk))) with a changed time scale is used. t / (2 ** (n-
k))) can be made by arranging 2 ** (nk) pieces of φ (j, t), and if the temporal replacement is appropriately performed, the uniform pulse width modulation and the weighted pulse width modulation are the same. Will be the one.

The parameters a and b can be set to arbitrary values, but normally, a ratio is selected so that the difference in the effective voltage value due to the luminance becomes the largest. Depending on the number M of lines in the horizontal direction of the matrix, a: b = √M: 1.

Although the conventional pulse width modulation method has been described above, the point to be particularly noted is that in the conventional pulse width modulation method, the parameters a and b are constant without depending on p and k. , The minimum time interval to drive the pulse waveform is
The point is that one horizontal period is divided by m-1.

[0044]

In the simple matrix type display device, when the uniform pulse width modulation or the weighted pulse width modulation is performed as in the above conventional method, the minimum time interval for driving the pulse waveform is one horizontal period. It will be divided by m-1. Therefore, when the density gradation m becomes large, the minimum time interval of pulse driving becomes short in inverse proportion to it, and the frequency band used becomes large. As the band increases, a lot of crosstalk appears in the simple matrix type device in a high frequency region, and a false image and flicker occur in a display image. Therefore, an object of the present invention is to provide a display device with less crosstalk and a driving method thereof.

[0045]

In a simple matrix type display device, in order to add a display gradation, time of one horizontal period is divided, and a desired voltage effective value is obtained in each time division section. The applied voltage value of at least one of the electrode and the Y electrode was controlled.

In order to reduce crosstalk, in the present invention, the method of time division for gradation is changed and the applied voltage is adjusted accordingly. In the first and second embodiments, one horizontal period is time-divided into equal parts by the number n of grayscale expression bits or q by a value larger than n and sufficiently close to n. In the first embodiment, the voltage applied to the Y electrode is adjusted to obtain a desired voltage effective value in each time division section. In the second embodiment, the voltage applied to the X electrode and the Y electrode is adjusted to obtain a desired voltage effective value.
In the third embodiment, the time division is not equal, but is almost equal, and the applied voltage value is adjusted to obtain a desired voltage effective value.

[0047]

[Operation] The effective value of the voltage on the intersection of the matrix is the application time,
It is determined by three values, that is, the voltage value of the X electrode and the voltage value of the Y electrode.
In the X electrode, there is a positive / negative inverted voltage value in the time division section of interest, and one of them is selected according to the display gradation. In the Y electrode, there is a binary voltage of 0 or a predetermined value.
The repetitive voltage is applied according to a predetermined rule. The difference in the effective voltage value depending on whether the voltage value of the X electrode is positive or negative is
It is the product of three terms consisting of the application time, the absolute value of the voltage of the X electrode, and the voltage value of the Y electrode. Therefore, even if the application time is changed, it is possible not to change the difference in effective voltage value by adjusting the applied voltage accordingly.

According to the time division of the present invention, the minimum time interval for driving the pulse waveform is n equal to one horizontal period or n.
It was close enough to the equal value. Conventionally, m- in one horizontal period
Although it was divided into 1 equal parts, considering that m can be up to the n-th power of 2, in the present invention, the minimum time interval of the pulse waveform can be made significantly longer than before, and a high frequency band can be used. It was possible to reduce the crosstalk due to. For example, when dividing one horizontal period into n equal parts, if n = 6,
Since m is 64, the high frequency crosstalk was large in the conventional 64-division, but since the present invention only requires 6 equal divisions,
The frequency band becomes 1/10, and the crosstalk is significantly reduced.

[0049]

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2, 5, 5, 10 to 12, and Tables 1 to 6.

FIG. 2 is a block diagram of a liquid crystal display device to which the present invention is applied. Although it is almost the same as the conventional configuration diagram of FIG. 4, only one place is different. Since the description of the same parts has been given in the section of the prior art, only different parts will be described below.

According to the present invention, one horizontal period is equally divided by the bit length n of gray scale display, and a voltage value corresponding to the density difference of the divided sections is applied to the liquid crystal panel 100. As a mechanism therefor, in the configuration diagram of FIG. 2, a command signal C for changing the voltage generated by the voltage generation circuit 103 in each of the divided sections is used as the timing signal generation circuit 10.
It occurs in 4. The voltage generation circuit 103 receives the command signal C from the timing signal generation circuit 103, and the X drive circuit 10
1 and each voltage value supplied to the Y drive circuit 102 are changed. In addition to the device configuration based on FIG. 2 described above, a device configuration for carrying out the present invention can be considered. For example, even in the case of FIG. 4 which is the conventional configuration, the voltage generation circuit 103 generates all the voltage values required in the present invention, and the X drive circuit 1 outputs the plurality of voltages.
The present invention can also be implemented by supplying 01 and Y drive circuits 102, and each drive circuit switches the required voltage and applies it to the liquid crystal display panel 100.

Next, the drive pulse waveform of the voltage applied to the liquid crystal display panel 100, which is the core of the present invention, is shown in FIG.
And illustrated in FIGS. 1 and 10
The pulse waveform shown in FIG. 12 is obtained when the matrix of the display screen is 4 × 4 and 4 gradation display, as in the case of the above-mentioned related art, and the display image shown in FIG. 5 is obtained. That is, in the symbol, N = M = 4, gradation m = 4, and bit length n = 2 expressing the gradation.

Drive pulse waveforms according to the first embodiment of the present invention will be described below with reference to FIGS. 10 and 11.

In FIG. 10, one horizontal period is divided into two equal parts, each section is made to correspond to a display bit, and the voltage value of the Y electrode is adjusted so that a desired density difference of the display bit appears. The first section obtained by bisecting one horizontal period was made to correspond to the lower display bit (k = 2), and the latter section was made to correspond to the upper display bit (k = 1).

In FIG. 11, one field period is divided into two equal parts, and each section is similarly made to correspond to a display bit. Note that FIG. 10 and FIG. 11 are equivalent when the temporal replacement is performed within one field period. Besides,
There are many combinations that are equivalent in terms of temporal replacement.

A drive pulse waveform based on the second embodiment of the present invention will be described below with reference to FIGS. 1 and 12.

In FIG. 1, one horizontal period is divided into two equal parts, each section is made to correspond to a display bit, and the voltage value of the X electrode and the voltage value of the Y electrode are set so that the desired density difference of the display bit appears. It has been adjusted. Similarly, the first section obtained by equally dividing one horizontal period is associated with the lower display bit (k = 2), and the later section is associated with the upper display bit (k = 1).

In FIG. 12, one field period is divided into two equal parts and each section is associated with a display bit. Similarly, FIGS. 1 and 12 are equivalent in terms of temporal replacement within one field period, and there are many other combinations that are equivalent in terms of temporal replacement.

As described above, in the first embodiment of the present invention, the difference in the effective voltage value corresponding to the display bit is given by adjusting the voltage value of the Y drive circuit. Further, in the second embodiment of the present invention, the difference in the effective voltage value corresponding to the display bit is given by adjusting the voltage values of the X drive circuit and the Y drive circuit.

Next, a general description of the drive pulse waveform of the present invention will be given based on mathematical expressions.

[0061]

[Expression 11] Y (j, k, t) = a (k) · φ (j, k, t) (Expression 11)

[0062]

[Equation 12] However, the definition of the symbols is defined by (Equation 1) to (Equation 10) in the related art.
Same as above, but will be described below.

I and j mean the i-th row and the j-th column in the order of the matrix of the liquid crystal panel 100. The value of i is an integer from 1 to N. The value of j is an integer from 1 to M.

K is the order of the bits expressing the density gradation of the display data and means the k-th of the density gradation expression bits of n bits in total.

T represents the time counted for each section divided into n equal parts.

Y (j, k, t) means a voltage waveform generated by the j-th Y driving circuit at time t in the k-th divided section, and is a voltage waveform applied to the j-th row of the above matrix. .

X (i, k, t) means a voltage waveform generated by the i-th X driving circuit at time t in the k-th divided section, and is a voltage waveform applied to the i-th row of the above matrix. .

A (k) and b (k) are constants that depend on the bit order k representing the gradation, and they are not dependent on k in the prior art.

I (i, j, k) is a value based on the display data,
It is set to −1 when the i-th row and the j-th column of the above matrix have the density of the k-th bit, and set to 1 when they do not have the density.

Φ (j, k, t) is the basic pulse waveform. In the case of FIG. 1 and FIGS. 10 to 12, the voltage averaging drive system is used as the drive system, and φ (j, k, t) is defined as the following function.

[0071]

Φ (j, k, t) = 0 (when t <j−1 or t ≧ j ... (Equation 13)

[0072]

Φ (j, k, t) = 1 (in the case of j−1 ≦ t <j) ... (Equation 14) where t is a time interval based on a time interval obtained by equally dividing one horizontal period into n. It was defined as taking 1 and counting from 0, ending just before n.

As a function system of φ (j, k, t), an orthogonal function with a constant norm can be used. Equation 13 and Equation 14
The functional system represented by is also a kind of orthogonal function with a constant norm, but in the general active drive method using an orthogonal function system with a constant norm,

[0074]

∫dtφ (i, k, t) φ (j, k, t) = 0 (when i ≠ j) (Equation 15)

[0075]

∫dt φ (i, k, t) φ (j, k, t) = const (constant) (when i = j) (Equation 16) However, the integration range is n within one frame period. It covers the entire one of the equally divided sections.

The orthogonal function system φ (j, k, t) used in the equations 11 to 16 is used during one frame period, but in the next frame period, a function system different from the previous orthogonal function system is used. It is also possible to use or change the order of the functional system. Also, the orthogonal function system φ (j, k,
In one example of t), the function system is the same regardless of k, but it is also possible to change or replace the function system depending on k.

The value of I (i, j, k) is -1 when the i-th row and the j-th column of the matrix have the kth bit density, and 1 when the density does not have the kth bit. did. However, that is the case where the coefficients a (k) and b (k) are adjusted so that the voltage effective value in the divided section divided into n equal parts is the difference between the effective values corresponding to the display bits. When the non-linear response is strong in the relationship between the effective voltage value and the display brightness, it is necessary to change the step of the effective voltage value so that the display brightness becomes linear.
At that time, the magnitude relationship of the 2 ** n voltage rms values that can be expressed by the combination of the voltage rms values in the equally divided n sections is not necessarily the magnitude relationship when the original drive bits mean as numbers. It doesn't have to be the same. At this time, the display data is converted into a driving bit string in order to correctly associate the value based on the display data with the density gradation after driving. Along with that, the meaning of k appearing in the equations 11 to 16 is also determined from the order of the bit string representing the display data.
It is redefined as the order of the driving bit string. That is, a section obtained by dividing one horizontal period into n equal parts corresponds to driving bits, and the coefficients a (k) and b (k) are set so that the difference in voltage effective value desired by each driving bit appears in the section in charge. ) Value. Also, from the relationship between the voltage effective value and the display brightness, the value of the voltage effective value for obtaining the desired display brightness has a non-linear step, and at least 1 of these voltage effective values is obtained.
If one cannot be created only from the combination of the n voltage effective values given in the n equally divided sections, 1
The horizontal period is divided into q equal parts larger than n so that all desired voltage effective values can be made from combinations of voltage effective values in the q equal parts. In this case, number 11
To n in the equations appearing in Equations 16 to 16 are replaced with q, and the meaning of k is replaced with the order of driving bits.
The optimum value of q is as close to n as possible, but there is a suboptimal value of q that is slightly larger than the optimum value.

Next, in the case where the relationship between the effective voltage value and the display brightness is linear, how to determine the parameter values a (k) and b (k) appearing in equations 11 and 12 will be described using Tables 1 to 6. .

The values of the parameter values a (k) and b (k) are described below the table frames of Tables 1 to 6, and when the voltage averaging drive system is used as the drive system in the table frames, That is,
The voltage value of each electrode of the liquid crystal display device 100 is shown for the case where the basic pulse waveform φ (j, t) is set to the functions expressed by the equations 13 and 14. In the table frame, the voltage values applied to the X electrode and the Y electrode are distinguished by on and off states, but in the state of the Y electrode on, the basic pulse waveform is φ (j, t) =
When it is 1, the state of the Y electrode off is
When φ (j, t) = 0 as shown in, the state of the X electrode on is the voltage value X (i, k, t) given to the X electrode shown in Formula 12.
When the value of is -b (k), the state of X electrode off is
This is a case where the value of X (i, k, t) becomes b (k).

Table 1 shows the parameter values a (k) and b (k) in the case of displaying four gradations in the first embodiment of the present invention.
And the voltage value given to each electrode.

[0081]

[Table 1]

Table 2 shows the case of 4-gradation display according to the second embodiment of the present invention.

[0083]

[Table 2]

Table 3 shows the case where the first embodiment of the present invention is applied to 16 gradation display.

[0085]

[Table 3]

Further, Tables 4 to 6 show three types of examples in which the second embodiment of the present invention is applied to 16 gradation display.

[0087]

[Table 4]

[0088]

[Table 5]

[0089]

[Table 6]

Tables 1 and 3 show that the first embodiment of the present invention changes only the voltage value of the Y electrode.
It can be seen from Tables 4 to 6 that the second embodiment of the present invention changes the voltage values of the X electrode and the Y electrode. Also,
From Table 1 to Table 6, in the present invention, a (k) × b (k)
It can be seen that all values of have the same value.

In Tables 1 to 6, the ratio of a (k) and b (k) is not specified, but a (k) should be set so that the difference between the effective values of the voltages becomes the largest according to the display gradation. The ratio of k) and b (k) can be determined. If the maximum RMS contrast difference δC is defined as (1-minimum RMS value / maximum RMS value), the following ratio gives the maximum RMS contrast difference δC.

In the first embodiment of the present invention, in the case of 4-gradation display, if the symbols in Table 1 are used,

[0093]

[Expression 17] Va: Vb = √ (2M) / √5: 1 (Expression 17) At this time,

[0094]

[Equation 18] δC = 1 / (1+ (√ (10M)) / 3) (Equation 18) In the case of 16-gradation display, if the symbols in Table 3 are used,

[0095]

[Formula 19] Va: Vb = 2√M / √85: 1 (Formula 19)

[0096]

[Equation 20] δC = 1 / (1+ (2√ (85M)) / 15) (Equation 20) In the second embodiment of the present invention, in the case of 4-gradation display, when the symbols in Table 2 are used, Like the prior art,

[0097]

A (k): b (k) = Va: Vb = √M: 1 (Equation 21)

[0098]

[Expression 22] δC = 1 / (1 + √M) (Expression 22) In the case of 16-gradation display, three types are listed in Table 4 to Table 6,
In the case of Table 4, similar to the conventional technology

[0099]

A (k): b (k) = Va: Vb = √M: 1 (Equation 23)

[0100]

[Equation 24] δC = 1 / (1 + √M) (Equation 24) In the case of Table 5 and Table 6,

[0101]

[Equation 25] Va: Vb = √ (2M) / √5: 1 (Equation 25)

[0102]

[Equation 26] δC = 1 / (1+ (√ (10M)) / 3) (Equation 26) In the case of the second embodiment of the present invention, the parameter a as shown in Table 4 is used.
If (k) and b (k) are determined, even if the number of gradation displays increases, the parameter ratio √M: 1 remains the same as in the conventional technique, and the effective value contrast difference becomes the same as in the conventional technique. If the parameters a (k) and b (k) are decided as shown in Table 5 and Table 6, the parameter ratio is √ (2M) / √ even if the gradation display is increased.
At 5: 1, the RMS contrast difference is also 1 / (1+ (√ (1
It becomes 0M)) / 3), and the difference in RMS contrast is only slightly smaller than in the past.

On the other hand, in the case of the first embodiment of the present invention, the voltage value contrast difference becomes smaller as the display gradation increases. Generally, if the display bit is n, in the first embodiment of the present invention,

[0104]

[Expression 27] Va: Vb = √ (3n · M / (2 ** (2n) -1)): 1 (Expression 27)

[0105]

[Equation 28] δC = 1 / (1 + n · M · Vb / Va · (2 ** n−1)) (Equation 28) Note that √ (2M) represents the square root of √ (2M),
M represents the number of horizontal lines of the liquid crystal display panel 101.

When the number M of lines in the horizontal direction is 240, the numerical values will be concretely shown below.

In the second embodiment of the present invention, when the determination in Table 4 is made, the effective value contrast difference δC is the display bit length n.
It becomes 0.0606 regardless of. Even if the determination of Table 5 and Table 6 is made, it is 0.0577 regardless of the display bit length n.
Therefore, it can be reduced by 5%. On the other hand, in the first embodiment of the present invention, depending on the display bit length n, in the case of 16 gradation display of n = 4, the effective value contrast difference δC is 0.0499,
18% decrease, and 0.0429 in 64 gradations of n = 6
Will decrease by 29%. As the voltage effective value contrast difference δC is larger, the dynamic range of the voltage effective value is larger, and it is possible to improve the contrast of the displayed image.

As described above, in the second embodiment of the present invention, using the method of Table 4 has the effect of not lowering the dynamic range of the effective voltage value, and using the methods of Tables 5 and 6, the applied voltage value step Use a simple one that does not include irrational numbers in
This has the effect of not significantly lowering the dynamic range of the effective voltage value.

Even when the above embodiment is used, when the frequency is still high and crosstalk appears, a part of the information transmitted from outside is not used in order to reduce the frequency. Can be used in. For example, the time to send information for two screens from the outside
The information corresponding to one screen can be selected and the information for one screen can be displayed on the display device side while the information for two screens is being sent externally. There are various ways to select information. After acquiring one screen of data, the next data is discarded, or interleaving is used to alternately acquire and discard data, or alternately acquire and discard data for each pixel. It is conceivable to repeat the above, or to use the average value of the data for two screens.

Here, one frame period and one horizontal period are redefined. One frame period is a time required to display one screen of information on the display device side, and one horizontal period is a time of a basic unit of a drive pulse for display when two-gradation display is performed. . The one frame period and one horizontal period used in the above claims are redefined here. By redefining in this way, it is possible to include the case where the above display information is selected and the case where the time of the basic unit of the drive pulse is made different from the time interval of the external horizontal synchronizing signal in the active drive method. it can. That is, in the case of the active drive system, the basic unit of the drive pulse does not necessarily have to be the time obtained by dividing one frame period by the number M of lines in the horizontal direction (equal to the time interval of the horizontal synchronization signal). = 240, one frame period is 2
256 easy to create orthogonal basis instead of splitting by 40
This is because it is possible to divide by, or switch the horizontal direction and the vertical direction.

Next, a third embodiment of the present invention will be described with reference to FIGS. 13 to 15. In the third embodiment, when the voltage value applied to each electrode of the liquid crystal panel 100 needs to be applied with a voltage higher than the withstand voltage of the circuit, the applied time is extended to make the applied voltage equal to or lower than the withstand voltage. It was devised.

In FIG. 13, the Y electrode of the liquid crystal panel 100 is
The case where a problem occurs that the withstand voltage value Vlimit of the circuit or more occurs is shown. In FIG. 13, only one horizontal period is extracted, and the voltage value when the voltage of the Y electrode is on,
An example of the voltage value of the X electrode is shown. As is clear from the figure,
In FIG. 13, as in the first embodiment of the present invention, in the case of 8-gradation display, one horizontal period is divided into three equal parts, and gradation expression is performed by changing the voltage value of the Y electrode. It became necessary to give the electrodes a withstand voltage value Vlimit or more of the circuit. That is, here, the voltage applied to the Y electrode is set to Vs: 2Vs: 4Vs, and the difference in the effective value of the voltage is set to 1: 2: 4. The voltage is needed.

14 and 15 show that the withstand voltage value V is increased by extending the application time for the voltage value of the large amplitude value shown in FIG.
The voltage was set smaller than the limit. In FIG. 14, one horizontal period is divided into 1: 1: 4/3 and the applied voltage is Vs: 2V.
s: 3 Vs, and a voltage lower than the withstand voltage was sufficient. In FIG. 15, one horizontal period is divided into 1: 1: 2 and the applied voltage is Vs: 2Vs: 2Vs.

In addition to the above, there are many combinations in which the product of the voltage value of the Y electrode and the applied voltage value is the same. In addition to the case of applying the weight of the gray scale display only by the applied voltage of the Y electrode as in the first embodiment of the present invention, the application of the X electrode as in the second embodiment of the present invention is performed. Even when the voltage is also changed, it is possible to avoid the large-amplitude applied voltage by similarly performing the deformation in which the product of the applied voltage of the X electrode, the applied voltage of the Y electrode, and the application time is the same.

In the examples of FIGS. 14 and 15 described above, it is described that the time interval of one horizontal period is extended, but when the time of one horizontal period cannot be extended, the ratio is kept the same,
The time can be shortened uniformly and the time intervals of one horizontal period can be made the same. That is, in FIG. 14, one horizontal period is
Since it is divided into 1: 1: 4/3, when expressed on the time scale that was the original 1: 1: 1, it is 9/10: 9/10: 1.
By dividing by 2/10, the time of one horizontal period can be made the same as the original.

The three embodiments of the present invention have been described above, but they will be summarized below.

In the present invention, since gradation display is performed based on n-bit display data, the time in one frame period is set to n.
Dividing by the above number r, the applied voltage applied to each electrode of the liquid crystal panel 100 is given by the following formula.

[0118]

[Formula 29] Y (j, g, t) = a (g) · φ (j, g, t) (Formula 29)

[0119]

[Equation 30] However, i and j represent the order of the matrix of the liquid crystal panel 100.

G is an integer of 1 or more and r or less in the order in which time is divided into r intervals.

[0121] t represents the time to be counted for each divided section of interest.

Y (j, g, t) is a voltage waveform generated by the j-th Y drive circuit at the g-th time t, and is a voltage waveform applied to the j-th row of the liquid crystal panel 100.

X (i, g, t) is a voltage waveform generated by the i-th X drive circuit at the g-th time t, and is a voltage waveform applied to the i-th row of the liquid crystal panel 100.

At least one of a (g) and b (g) is
Parameter value depending on g.

J (i, j, g) is a value based on the display data in the i-th row and the j-th column of the matrix of the liquid crystal panel 100, and is high on the matrix intersection of the i-th row and the j-th column in the g-th time division section. The value is set to -1 when the effective voltage value is provided, and is set to 1 when the low effective voltage value is provided.

Φ (j, g, t) is an orthogonal function with a constant norm. That is, ∫dtφ (i, g, t) φ (j, g, t) = 0 i ≠ j ∫dtφ (i, g, t) φ (j, g, t) = const (constant) i = j The integration range covers the entire g time division section of interest within one frame period.

When the applied voltage described by the above equations 29 and 30 is applied to each electrode of the liquid crystal panel 100, the value of J (i, j, g) is -1 or 1 for each section divided by r. It is possible to realize two states in which the effective value of the voltage is different depending on whether there is one. Two
If the difference between the two voltage effective values is different for each divided section, a combination of them can generally create 2 ** r different voltage effective value states. However, if there are sections where the difference in voltage rms values is the same, or when the voltage rms difference in a section can be expressed as a combination of voltage rms differences in other sections, the number of combinations that can be expressed as a whole is that much. decrease.

In the conventional uniform pulse width modulation, the number of divisions r is m−1, and the time division is performed uniformly. However, m is a display gradation. Then, a (g) and b (g) were made constant regardless of the divided section g, and the voltage effective value differences were made the same in each divided section. Therefore, although the number of divisions is m-1, the number of combinations that can be displayed is m. Display gradation m is 2 *
* N, the number of divisions (m-1) becomes enormous when n becomes large. Therefore, the minimum time-divided time becomes short, and the frequency band used becomes large.

In the conventional weighted pulse width modulation, the number of divisions is n, but the time interval is 1: 2: 4: ...: 2 ** (n-
1), and the voltage effective value difference of each divided section is set to 1: 2: 4: ...: 2 ** (n-1) in the same manner, 2 ** n.
Allowed for individual combinations. However, since the minimum time interval is the same as in the case of the conventional uniform pulse width modulation, the frequency band used becomes large.

The present invention is characterized in that the number of time divisions is set to n or a value close to n, which is larger than n, and the time intervals of the divided sections are made as uniform as possible to suppress the frequency band to be used. At this time, the voltage effective value difference in each divided section was determined, and the values of a (g) and b (g) and the division time were adjusted so that all desired gradations could be expressed. If the time interval of each divided section is expressed as t (g), the voltage effective value difference of each divided section is a (g) * b (g)
* Proportional to the value of t (g). Using this relationship, it is possible to determine the values of a (g), b (g), and t (g) that match the situation.
In the first embodiment of the present invention, the time division is divided into n equal parts,
The case where a desired voltage effective value is obtained by adjusting the value of a (g) is illustrated. In the second embodiment, the case where the value of a (g) and the value of b (g) are adjusted in the same manner by dividing into n equally is illustrated. In the third embodiment, when the value of a (g) is equal to or higher than the withstand voltage of the circuit,
An example is shown in which the value of a (g) is made equal to or lower than the withstand voltage by adjusting the value of t (g). In addition, there are various specific adjustment values that utilize the fact that the difference in effective voltage value is proportional to a (g) * b (g) * t (g). The adjustment of a (g), b (g), and t (g) was performed in advance and fixed, but it is also possible to determine the conditions and adjust each time based on the conditions. In the case of adjusting each time, not only the difference between the voltage effective values but also the voltage effective value itself needs to be corrected by a constant amount in order to make the voltage effective value a predetermined value.

In the present invention, when the relationship between the voltage effective value and the display brightness is linear, the number of divisions is set to n, each divided section is made to correspond to the display bit, and the voltage effective value difference in each divided section is set to the display bit. I tried to make it the weight I meant. When the relationship between the effective voltage value and the display brightness is non-linear, the number of divisions may not be enough to be n, and in that case, the number of divisions needs to be increased somewhat. In addition, in some cases, the divided section and the display bit cannot be associated with each other, and a driving bit string for each divided section was created, the display bit string was converted into a driving bit string, and the driving was performed based on the driving bit string. When the bit string is expressed by the method of writing a set, the display bit string on the matrix i, j is {I (i, j, k) | k = 1, n}, and the driving bit string is {J
(i, j, g) | g = 1, r}. The association of I (i, j, k) to J (i, j, g) can be performed by referring to the relationship obtained in advance from the memory table, or the relationship can be given and calculated each time. Further, it is also possible to obtain and use a value every time for each divided section without specifically creating a driving bit string. Although the case where the voltage effective value corresponding to the display luminance is provided in one frame period is described here, the voltage effective value corresponding to the display luminance can be similarly set in the several frame periods. In that case, the same thing can be said by summarizing several frame periods and redefining them as a new one frame period.

In the above, the drive pulse waveform of the voltage applied to the liquid crystal panel 100 has been mainly described in order to explain the driving method for giving the gradation expression to the simple matrix type liquid crystal display device. Hereinafter, a liquid crystal display device for carrying out the method of the present invention will be described in detail with reference to the accompanying drawings of embodiments of the configuration and operation. In the following description, the case where the drive waveform shown in FIG. 1 is applied to the liquid crystal panel 100 based on the block configuration of the display device shown in FIG.

FIG. 2 is a block diagram of the liquid crystal display device of the present invention. The outline of the operation will be described below with reference to FIG. The timing signal generation circuit 104 inputs a vertical synchronization signal, a horizontal synchronization signal, and a data clock, and generates various timing signals for operating the display data control circuit 105, the X drive circuit 101, the Y drive circuit 102, and the voltage generation circuit 103. . 301 is a voltage generation circuit timing bus, and 30
Reference numeral 2 is a Y drive circuit timing bus, 303 is an X drive circuit timing bus, and 304 is a display data timing bus. Reference numeral 305 denotes X data, which is 4-dot parallel data, and the display data control circuit 105 takes in the display data for one line, separates it for each bit indicating a gradation, and supplies it as X data 305 to the X drive circuit 101. . Reference numeral 306 is an X voltage, and 307 is a Y voltage, each of which has a plurality of voltage values through a necessary number of parallel buses. The voltage generation circuit 103 generates desired plural voltages from the reference voltage by the voltage dividing circuit and supplies the desired plural voltages to the X drive circuit 101 and the Y drive circuit 102 as the X voltage 306 and the Y voltage 307. X drive circuit 101, Y drive circuit 102
Then, a desired voltage is selected based on the X data 305 sent from the display data control circuit 105 and various timing signals sent from the timing signal control circuit 104,
A desired voltage is applied to each matrix of the liquid crystal panel 100.

The reference voltage is a power supply voltage input to the liquid crystal display device, which is not shown here.
Further, the timing signal generation circuit 104 understands the operations of the display data control circuit 105, the X drive circuit 101, the Y drive circuit 102, and the voltage generation circuit 103, which will be described later, and thus the general-purpose logic used in the TTL circuit. It can be easily realized by using a circuit.

FIG. 16 is a timing chart showing timings of a vertical synchronizing signal, a horizontal synchronizing signal, a data clock and display data which are input to the liquid crystal display device. Display N columns, M
Assuming that the line is a line and the vertical blanking period, which is a non-display line, is absent, the horizontal synchronizing signal becomes M periods in one period of the vertical synchronizing signal in one frame period. Data for one line is input in one cycle of the horizontal synchronizing signal in synchronization with the data clock. Here, the horizontal blanking period which is not displayed is 4 dots, and is represented by S1 to S4 in the figure, and the data for N columns to be displayed is represented by 1 to N. The display data is 2-bit data indicating four gradations and is serially input.

FIG. 17 is a block diagram of an embodiment of the display data control circuit 105. 308 is serial / parallel means, 309 is parallel display data, 321 is an SP clock bus, and the input serial display data is SP.
It is converted into 4-dot parallel parallel display data 309 by the clock bus. Here, the data to be converted in parallel is the data to be converted starting from "1" of the data to be displayed indicated by "1" to "N" in FIG. The serial-parallel conversion means 308 latches the parallel display data by the clock synchronized with the serial display data for the number of parallels, here 4 dots, and generates the parallel display data 309 from the latched data. To latch. Therefore, the SP clock bus 321 is composed of a serial clock and a parallel clock synchronized with the serial display data.
The parallel clock is generated by dividing the serial clock, and is generated at a timing of handling the data indicated by "1" in FIG. 16 as the leading data in the 4-dot cycle here.

Reference numeral 310 is memory means A, and 311 is memory A.
a, 312 are memories Ab, 313 are memory means B, 31
Reference numeral 4 is a memory Ba, and 315 is a memory Bb. Reference numerals 316 to 319 denote memories Aa311 and Ab3, respectively.
12, read data of memory Ba314, memory Bb315, that is, data Aa, data Ab, data B
a and data Bb. Parallel display data 309 is 1
The lines are written alternately in the memory means A and the memory means B. Then, the X data 305 is generated by reading from the memory means in which the writing is not performed. 320
Is a data selector, 322 is a bit signal indicating whether the upper bits or lower bits of the read data are valid, and 323 is an AB read signal indicating whether to read from the memory means A310 or the memory means B313. Yes, the data selector 320 uses the bit signal 32
2, data Aa316, data Ab317, data Ba318, data Bb319 according to the AB read signal 323
One of them is selected and output as X data 305.
324 is a memory control signal generation means, 325 is a memory read / write signal bus, and the memory control signal generation means is S
A memory read / write signal bus 325 is generated from the P clock bus 321, the bit signal 322, and the AB read signal 323. Although details are not described here, they are obvious from the read operation and the write operation of the memory. SP clock bus 32
1, the bit signal 322, and the AB read signal 323 are generated by the timing signal generation circuit 104 as the display data timing bus 304 and given to the display data control circuit 105.

FIG. 18 is a timing chart for explaining the read timing of the memory, and Table 7 is a table for explaining the operation of the data selector 320. The timing and operation of each are clear from the figures and tables.

[0139]

[Table 7]

FIG. 19 is a block diagram of one embodiment of the X drive circuit 101. Reference numeral 326 is a data latch means for sequentially latching the X data 305 at the X clock, which is reset at the X horizontal clock and then the X data from the beginning in order. One line of 305 is fetched and the fetched data D1 to DN are output. Reference numeral 327 denotes an X horizontal clock which is a horizontal data latch means for simultaneously fetching the fetched data D1 to DN for one line fetched in the data latch means 326, and outputs the fetched data as horizontal data HD1 to HDN. Reference numeral 328 is a level shift means and 329 is a voltage selection means. The level shift means 328 converts the horizontal data HD1 output from the horizontal data latch means 327, which is a TTL level voltage, to the data of HDN to a voltage level handled by the voltage selection means. For example, 5V T
Convert the TL level to a high breakdown voltage level of 28V. The converted data for one line is output as shift data H1 to HN. The voltage selection means 329 shifts data H
Data for 1 line from 1 to HN and bit signal 3
22. One voltage is selected from the X voltage 306 according to the AC signal and output. In addition, the voltage selection means 329 uses the bit signal 3
22, shift the voltage level of the AC signal from the shift data H1 to H
It shifts and uses like N. Where X clock,
The X horizontal clock, the bit signal 322, and the AC signal are generated by the timing signal generation circuit 104 as the X drive circuit timing bus 303 and given to the X drive circuit 101.
Table 8 is a table for explaining the operation of the voltage selection means 324.
How to select the voltage is clear from the table.

[0141]

[Table 8]

FIG. 20 is a timing chart for explaining the timing until the input display data is given to the liquid crystal panel 100, and FIG. 21 is a timing chart for explaining the operation of the Y drive circuit 102. From the figure, each operation and timing are clear.

FIG. 22 is a block diagram of one embodiment of the Y drive circuit 102. 330 is a shift circuit means, 331 is a Y level shift means, 332 is a Y voltage selection means, and the shift circuit means 330 outputs a head signal to Y. The line data L1 which is the data of the first line taken in by the horizontal clock is set to "1", and then this "1" is shifted to the line data L2, L3, ... LM according to the Y horizontal clock. The Y level shift means 331 shifts the voltage level of the TTL level line data L1 to LM to the voltage level of the Y voltage selection means 332, and the shifted data is output as shift line data S1 to SM. Y voltage selection means 3
32 is shift line data S1 to SM, bit signal 3
22. Select one voltage from the Y voltage 307 according to the AC signal. Table 9 is a table for explaining the operation of the Y voltage selection unit 332. In the table, * indicates that the data may be "1" or "0".

The operation of the embodiment of the present invention will be described below with reference to the drawings.

In the liquid crystal display device of FIG. 15, display data is input at the timing shown in FIG. 16, and 2-bit grayscale data is serially sent for one screen in one frame period. This display data is displayed by the display data control circuit 10.
Input to 5. The display data control circuit 105 shown in FIG.
As shown in FIG. 7, the display data is converted into 4-bit parallel parallel display data 309. The parallel display data 309 is written in the memory means A310. Here, the lower bit of the 2-bit gradation bit is set to the memory Aa3.
11, the upper bits are written in the memory Ab 312. 1
When the line data is written in the memory means A310,
The data for the next one line is written in the memory means B313. Note that the memory means B is the same as the memory means A310.
In the writing to 313 as well, the lower bits of the gradation bits are written to the memory Ba314 and the upper bits are written to the memory Bb315. For writing, this operation is alternately repeated. Reading from the memory means is twice as fast as writing, and the display data for one line is read twice from the memory means that is not writing. In the present embodiment, this can be realized by setting the reading to be the period of the clock synchronized with the 2-dot parallel with respect to the period of the clock synchronized with the 4-dot parallel data. Therefore, if the display data of the second line is written in the memory means B313, the display data of the first line is read from the memory means A310. This reading operation is shown in FIG.
As shown in FIG. 7, the bit signal 322 is performed twice in one horizontal period, and the bit signal 322 becomes “1” at the first time and becomes “0” at the second time. Note that the AB read signal 323 is "1" and the memory A3
A read of 10 indicates a read of the memory B313 by "0". Therefore, the read data are as shown in Table 7:
It is selected by the data selector 320 and becomes the X data 305.

Therefore, the display data control circuit 10 of FIG.
In 5, the display data is divided into each bit of the gradation bits and is output as X data 305 for each horizontal. This X data 305 is given to the X drive circuit 101.

Next, an example of the X drive circuit 101 and its operation will be described.

The X drive circuit 101 can be realized by the configuration shown in FIG. 19. The X data 305 is fetched by the data latch means 326 at the X clock, and when the display data for one horizontal is fetched, the horizontal data latch is performed at the X horizontal clock. Means 32
It is taken in by 7 and becomes horizontal data HD1 to HDN.
The voltage selecting means shifts the voltage level of the horizontal data HD1 to HDN according to the shift data H1 to HN, the bit signal 322, and the AC signal, and as shown in Table 8, the X voltage 30
One voltage is selected from 6 and output to the X electrodes X1 to XN. In Table 8, the bit signal 322 indicates the lower bit when the bit signal 322 is "0" and the upper bit when the bit signal 322 is "1", contrary to the reading from the memory means. this is,
This is because the display data is delayed by one horizontal period of the X horizontal clock in the X drive circuit. Further, in Table 8, when the voltage level is compared with Table 2, Vb1 is Vb / √2,
Vb2 is -Vb / √2, Vb3 is Vb, Vb4 is -V
b, Vb5 is -Vb / √2, Vb6 is Vb / √2, Vb
7 becomes -Vb and Vb8 becomes Vb. When compared with Table 1, Vb1 is Vb, Vb2 is -Vb, and Vb3 is Vb.
b, Vb4 is -Vb, Vb5 is -Vb, Vb6 is Vb,
Vb7 becomes -Vb and Vb8 becomes Vb. Therefore, in the present embodiment, the voltage selection means selects one voltage from eight voltages, but as shown in the above voltage example, the different voltage required in comparison with Table 2 is four voltages. In comparison, the different voltages are 2 voltages, so the voltage selection is 4
Voltage, 2 voltage to 1 voltage, shift data H1 to H
It is possible to realize the selection operation of Table 8 by decoding N and the AC signal and the bit signal 322 into a selection signal. This can reduce the number of selected voltages, and is effective in reducing the cost of the X drive circuit 101.

Next, an example of the Y drive circuit 102 and its operation will be described.

As described above, the input display data is the display data of the first line indicated by the horizontal synchronizing signal after the vertical synchronizing signal is output, as shown in FIG. It is once written in A310 and read in the next horizontal period. Then, the read display data is separated into one horizontal part of the lower bits and one horizontal part of the upper bits at the cycle of the X horizontal clock that is 1/2 times the horizontal period, and becomes the X data 305. . Then, the X drive circuit 101 delays by one cycle of the X horizontal clock and outputs it to the liquid crystal panel 100 as the voltage of the X electrode. From the above, the Y horizontal clock and the start signal are as shown in FIG.
The timing is as shown in 1. This is because the voltage of Y1 which is the Y electrode of the first line is determined by the X drive circuit 101 according to the display data of the first line.
a) This is because the voltages Va2 and Va1 are output during the period in which the first line (Ab)) is output. Therefore, in this embodiment, the Y horizontal clocks are 1.1, 2.1, 3.1, ... The timing of outputting the clock is 1 and the start signal is "1" at the timing of the Y horizontal signal shown by Y1 in FIG.
Is a timing signal for latching. Y drive circuit 1
02 is Va according to the Y horizontal clock as shown in FIG.
2, the voltage output of Va1 is sequentially shifted to Y1, Y2, ... YM. When the voltages Va2 and Va1 are not output, the voltage Va0 is output. An example of the Y drive circuit 102 will be described below with reference to FIG. The shift circuit means 330 fetches "1" of the head signal at the Y horizontal clock, sets the line data L1 to "1", and then Y
According to the horizontal clock, "1" is set to line data L2, L3
..., shift with LM. The head signal is once per frame "
Since it is "1", it becomes "0" except for the line data which is "1". The voltage level of the line data L1 to LM is shifted by the Y level shift means to become shift line data S1 to SM. The Y voltage selection means selects and outputs one voltage from the Y voltage 307 as shown in Table 9 according to the shift line data S1 to SM, the bit signal 322, and the AC signal.

[0151]

[Table 9]

In Table 9, the voltage levels are compared with those in Tables 1 and 2, where Va1 is Va, Va2 is Va / √2 and Va.
0 becomes "0".

As described above, the operation of the display data control circuit 105, the X drive circuit 101, and the Y drive circuit 102 makes it possible to realize a liquid crystal drive circuit which divides one horizontal period into two and performs four gradation display. Further, in this embodiment, the gradation bit of the display data is divided for each horizontal, but the present invention is not limited to this, and it is also possible to perform it for each arbitrary horizontal line, and further for each frame. It is also possible to do so. It can be easily inferred that this can be realized by increasing the storage capacity of the memory means of the display data control circuit 105 to the control unit.

Further, when increasing the number of gradations to be displayed, it is sufficient to increase the memory capacity to be stored by an increased number of bits and process the read-out cycle of the memory means by multiplying by the number of write bits. Can be analogized. Further, when the number of gradation display increases, as shown in Table 3 to Table 6,
The number of voltages output from the X drive circuit 101 and the Y drive circuit 102 increases, but this can be easily inferred from this embodiment by increasing the number of selection voltages of the respective voltage selection means. When the number of gray scales displayed increases, the read cycle of the memory means is multiplied by the number of written bits, so that the data amount of the bit signal 322 also increases (in this embodiment, "1" for double reading). , "0"), it is possible to select an increased voltage number by using this.

In the above description, the voltage generation circuit 103 merely generates a plurality of desired voltages, and has a role of selecting a desired voltage value to be applied to each matrix of the liquid crystal panel 100.
This is performed only within the X drive circuit 101 and the Y drive circuit 102. However, other voltage selecting means can be considered. For example, there is a method in which the voltage generation circuit 103 also bears a part of the voltage selection means by utilizing the fact that the number of voltages applied to the matrix is limited within a predetermined time. That is, the timing signal generation circuit 104 generates a timing signal, sends necessary timing information to the voltage generation circuit 103 through the voltage generation circuit timing bus 301, and the voltage generation circuit 103 outputs the desired voltage for the number of times required for the time timing. There is a method in which a desired applied voltage is selected from the voltage values of only the number necessary for the time timing in the X drive circuit 101 and the Y drive circuit 102, which are produced or switched and output. In addition, a circuit having a voltage selection function may be arranged in the middle of the voltage generation circuit 103 and the X drive circuit 101 and the Y drive circuit 102 to realize the same function. As described above, in a method in which a part of the voltage selection means is also burdened to the voltage generation circuit 103, which is the voltage supply side, etc., the number of buses supplying a plurality of voltages of the X voltage 306 and the Y voltage 307 is reduced, and the X drive is performed. This has the effect of reducing the bit length of data that provides information that determines the applied voltage value of the circuit 101 and the Y drive circuit 102.

Although the embodiments of the present invention have been described with respect to the liquid crystal display device, the material is not necessarily liquid crystal, and the light transmittance or the reflectance or the light Any substance can be used as long as it is a substance that changes the degree of polarization or the transmittance, reflectance, spectral distribution of the degree of polarization including the spectrum of light.

[0157]

In the simple matrix type display device,
When the driving method for gradation display of the present invention is used, the minimum time interval of the drive pulse waveform becomes shorter, the frequency band used is reduced, crosstalk is reduced, and false images and flicker on the display screen are reduced. Can be suppressed.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a drive pulse waveform for performing 4-gradation display according to a second embodiment of the present invention.

FIG. 2 is a block configuration diagram of a liquid crystal display device of the present invention.

FIG. 3 is a diagram showing an effective value of a voltage applied to a liquid crystal display panel and obtained display brightness.

FIG. 4 is a block configuration diagram of a conventional liquid crystal display device.

FIG. 5 is a diagram showing a display example of four gradations in a 4 × 4 display matrix.

FIG. 6 is a diagram showing an example of a drive pulse waveform for performing 4-gradation display of a conventional uniform pulse width modulation method.

FIG. 7 is a diagram showing another example of drive pulse waveforms for performing 4-gradation display of a conventional uniform pulse width modulation method.

FIG. 8 is a diagram showing an example of a drive pulse waveform for performing a four-gradation display of a conventional weighted pulse width modulation method.

FIG. 9 is a diagram showing another example of drive pulse waveforms for performing 4-gradation display in the conventional weighted pulse width modulation method.

FIG. 10 is a diagram showing an example of drive pulse waveforms for performing 4-gradation display in the first embodiment of the present invention.

FIG. 11 is a diagram showing another example of drive pulse waveforms for performing 4-gradation display in the first embodiment of the present invention.

FIG. 12 is a diagram showing another example of drive pulse waveforms for performing 4-gradation display according to the second embodiment of the present invention.

FIG. 13 is a diagram showing an example in which a large amplitude value voltage of the present invention causes a problem.

FIG. 14 is a diagram showing an example of a countermeasure against a large amplitude value voltage according to the present invention.

FIG. 15 is a diagram showing another example of the countermeasure for the large amplitude value voltage according to the present invention.

FIG. 16 is a timing chart of signals input to a liquid crystal display device.

FIG. 17 is a block diagram of an embodiment of a display data control circuit.

FIG. 18 is a timing diagram of memory read timing.

FIG. 19 is a block diagram of an embodiment of an X drive circuit.

FIG. 20 is a timing chart showing the flow of display data.

FIG. 21 is a timing chart of the operation of the Y drive circuit.

FIG. 22 is a block diagram of an embodiment of a Y drive circuit.

[Explanation of symbols]

100 ... Liquid crystal panel, 101 ... X drive circuit, 102 ... Y
Drive circuit, 103 ... Voltage generation circuit, 104 ... Timing signal generation circuit, 105 ... Display data control circuit, 201 ...
Vertical sync signal input terminal, 202 ... Horizontal sync signal input terminal, 203 ... Data signal input terminal, 204 ... Display data input terminal, 301 ... Voltage generation circuit timing bus, 302 ... Y drive circuit timing bus, 303 ... X drive circuit timing bus, 304 ... Display data timing bus, 305 ... X data, 306 ... X voltage, 307 ... Y
Voltage, 308 ... Serial / parallel means, 309 ... Parallel display data, 310 ... Memory means A, 311 ... Memory Aa, 312 ... Memory Ab, 313 ... Memory means B,
314 ... Memory Ba, 315 ... Memory Bb, 316 ... Data Aa, 317 ... Data Ab, 318 ... Data Ba,
319 ... Data Bb, 320 ... Data selector, 321
... SP clock bus, 322 ... Bit signal, 323 ... A
B read signal, 324 ... Memory control signal generating means, 32
5 ... Memory read / write signal bus, 326 ... Data latch means, 327 ... Horizontal data latch means, 328 ... Level shift means, 329 ... Voltage selection means, 330 ... Shift circuit means, 331 ... Y level shift means, 332 ... Y
Voltage selection means.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeyuki Nishitani 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Hitachi, Ltd. Microelectronics Equipment Development Laboratory (72) Inventor Norio Tanaka Totsuka-ku, Yokohama-shi, Kanagawa 292 Yoshida-cho, Hitachi, Ltd., Microelectronics Equipment Development Laboratory (72) Inventor, Koichi Sano, 1099, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Hitachi, Ltd. System Development Laboratory

Claims (19)

[Claims] 1. A matrix is formed by arranging electric wires vertically and horizontally. 2) A voltage is applied to each of the electric wires vertically and horizontally to form a potential difference at a matrix intersection, and 3) according to an effective value of an applied voltage. 3-1) transmittance of light, 3-2) reflectance of light, 3-3) degree of deflection of light, 3-4) spectral distribution of transmittance including reflectance of light, reflectance, degree of deflection, 4) at least one of the four sets of substances whose physical constants change is used, 4) the potential difference at the matrix intersection is applied to the substance, and the physical constant of the substance changes according to the potential difference at the matrix intersection. In the display device, 5) the gradation to be displayed is given based on n-bit display data, and 6) corresponding to the gradation display bit number n, 6-1) one frame period is divided into n equal parts. , Or 6-2) divide one horizontal period into n equal parts Or 6-3) performing time division that is equivalent to the above-described n equal divisions when the time is replaced within one frame period, and 7) based on the display data of each display bit, in the matrix described above. A method for driving a display device, which is characterized by controlling an applied voltage. 2. The method for driving a display device according to claim 1, wherein in 7), a specific voltage waveform of the voltage applied to the matrix is determined based on the following equation. However, i and j are the order of the above matrix, k is the order of the bits expressing the density gradation of the display data, t is the time to count for each display bit of interest, and Y (j, k, t) is the j-th When the Y drive circuit is at the time t of the kth bit
Is a voltage waveform applied to the j-th row of the above matrix, X (i, k, t) is the voltage waveform at the k-th time t of the i-th X drive circuit.
Is a voltage waveform applied to the i-th row of the above matrix, a (k), b (k) are parameters according to the k-th bit, and I (i, j, k) is based on the display data. When the density of the k-th bit is given to the i-th row and the j-th column of the above matrix,
1, when no density is given, φ (j, k, t) is an orthogonal function with a constant norm, that is, ∫dt φ (i, k, t) φ (j, k, t) = 0 i ≠ j ∫dt φ (i, k, t) φ (j, k, t) = const (constant) i = j However, the integration range covers the entire time allocated to the bit of interest within one frame period. 3. The values of the parameters a (k) and b (k) in the above equation are a
3. The method for driving a display device according to claim 2, wherein the value of the product of (k) and b (k) is set to a desired value. 4. The method for driving a display device according to claim 3, wherein the product of the parameters a (k) and b (k) in the above equation is set to the following value. Record. a (k) * b (k) = const2 / 2 ** (k-1) where const2 is an arbitrary constant and 2 ** (k-1) means 2 to the power of (k-1). , K means the k-th bit expressing the density gradation. 5. A ratio of the values of the parameters a (k) and b (k) that maximizes the dynamic range of the effective voltage value in one frame period, or in practice gives the maximum dynamic range. 5. The method for driving a display device according to claim 3, wherein the ratio is close to that of the display device. 6. A matrix is formed by arranging electric wires vertically and horizontally. 2) A voltage is applied to the electric wires vertically and horizontally to form a potential difference at a matrix intersection, and 3) according to an effective value of the applied voltage. 3-1) transmittance of light, 3-2) reflectance of light, 3-3) degree of deflection of light, 3-4) spectral distribution of transmittance including reflectance of light, reflectance, degree of deflection, 4) at least one of the four sets of substances whose physical constants change is used, 4) the potential difference at the matrix intersection is applied to the substance, and the physical constant of the substance changes according to the potential difference at the matrix intersection. In the display device, 5) gives a gradation to be displayed based on n-bit display data, and 6) divides one time period into n equal parts in order to divide the time to provide independent sections. , Or 6-2) Divide one horizontal period into n equal parts Or 6-3) performs time division that is equivalent to the above n equal divisions when the time is replaced within one frame period, and 6-4) sets the above n time division sections. 6-5) A voltage value to be applied to the matrix is determined for each of the n time division intervals, and each of the n bit intervals is associated with a driving bit string used when driving the interval. 6-6) The applied voltage value is selected so that the combination of the voltage effective values created by the n sections can realize the desired display brightness based on the display data. 7) From the order of the value of the combined voltage effective value,
The display data and the driving bit string are associated with each other, 6-8) the driving bit string is created from the display data based on the association, and 7) the matrix is based on the driving bit string. A method for driving a display device, comprising controlling a voltage applied to the display device. 7. A matrix is formed by arranging electric wires vertically and horizontally. 2) A voltage is applied to each of the electric wires vertically and horizontally to form a potential difference at a matrix intersection, and 3) according to an effective value of the applied voltage. 3-1) transmittance of light, 3-2) reflectance of light, 3-3) degree of deflection of light, 3-4) spectral distribution of transmittance including reflectance of light, reflectance, degree of deflection, Using at least one of the four sets of substances whose physical constants change, 4) applying a potential difference at the matrix intersection to the substance, and changing the physical constant of the substance according to the potential difference at the matrix intersection. In a display device to be awakened, 5) a gradation to be displayed is given based on n-bit display data, and 6) a time period is divided to provide an independent section. 6-1) One frame period is larger than n. Divide into several equal parts, or 6- ) 1 horizontal period is divided into q equal parts, or 6-3) When the time is replaced within one frame period, the time division becomes equal to the q equal parts mentioned above, 6-4 ) Corresponding the q number of time division sections with a driving bit string used when driving the section, 6-5) deciding a voltage value to be applied to the matrix for each of the q number of time division sections, Each of the n sections has its own voltage effective value, and 6-6) so that the combination of the voltage effective values made by the q sections realizes a desired display brightness based on the display data. 6-7) From the order of the value of the combined voltage effective value,
The display data and the driving bit string are associated with each other, 6-8) the driving bit string is created from the display data based on the association, and 7) the matrix is based on the driving bit string. A method for driving a display device, comprising controlling a voltage applied to the display device. 8. The method for driving a display device according to claim 7, wherein the value of q is set to a value closest to n or a suboptimal value close to n. 9. A matrix is formed by arranging electric wires vertically and horizontally. 2) A voltage is applied to each of the electric wires vertically and horizontally to form a potential difference at a matrix intersection, and 3) according to an effective value of the applied voltage. 3-1) transmittance of light, 3-2) reflectance of light, 3-3) degree of deflection of light, 3-4) spectral distribution of transmittance including reflectance of light, reflectance, degree of deflection, Using at least one of the four sets of substances whose physical constants change, 4) applying a potential difference at the matrix intersection to the substance, and changing the physical constant of the substance according to the potential difference at the matrix intersection. In the display device to be raised, 5) the gradation to be displayed is given based on n-bit display data, and 6) corresponding to the gradation display bit n, 6-1) one frame period is divided into n sections. Or 6-2) One horizontal period is divided into n sections Or 6-3) perform time division that is equivalent to division into the above n sections when the time is replaced within one frame period, and 7) display data of each display bit. A method for driving a display device, characterized in that the voltage applied to the matrix is determined based on the following equation. However, i and j are the order of the above matrix, k is the order of the bits expressing the density gradation of the display data, t is the time to count for each display bit of interest, and Y (j, k, t) is the j-th When the Y drive circuit is at the time t of the kth bit
Is a voltage waveform applied to the j-th row of the above matrix, and X (i, k, t) is a voltage waveform generated at the k-th time t by the i-th X drive circuit. The voltage waveform applied to the i-th row of the matrix, a (k) and b (k) are at least one of the parameter values depending on k, and I (i, j, k) is a value based on the display data. , −1 when the i-th row and the j-th column of the above matrix have the density of the k-th bit, 1 when they do not have the density, φ (j, k, t) is an orthogonal function with a constant norm, that is, , ∫dtφ (i, k, t) φ (j, k, t) = 0 i ≠ j ∫dtφ (i, k, t) φ (j, k, t) = const (constant) i = j The integration range covers the entire time assigned to the bit of interest within one frame period. 10. When the applied voltage cannot be applied beyond the allowable range, the time interval of the time division and the applied voltage value are set so that the application time is extended by the amount of the applied voltage value. A method for driving a display device according to claim 9. 11. A matrix is formed by arranging electric wires vertically and horizontally. 2) A voltage is applied to each of the electric wires vertically and horizontally to form a potential difference at a matrix intersection, and 3) according to an effective value of the applied voltage. 3-1) transmittance of light, 3-2) reflectance of light, 3-3) degree of deflection of light, 3-4) spectral distribution of transmittance including reflectance of light, reflectance, degree of deflection, Using at least one of the four sets of substances whose physical constants change, 4) applying a potential difference at the matrix intersection to the substance, and changing the physical constant of the substance according to the potential difference at the matrix intersection. In a display device to be awakened, 5) a gradation to be displayed is given based on n-bit display data, and 6) a time period is divided to provide an independent section. 6-1) One frame period is a number of n or more. Divide by r, or 6-2) 1 horizontal Or 6-3) perform time division that is equivalent to the division performed in r above when 6-3) temporal replacement is performed within one frame period, and 7) based on the display data, A method for driving a display device, wherein the voltage applied to the matrix is as follows. Where i and j are the order of the above matrix, g is the order of time division into r divisions, and is an integer from 1 to r, t is the time to be counted for each division division of interest, and Y (j, g, t ) Is a voltage waveform generated by the j-th Y drive circuit at the g-th time t, and is a voltage waveform applied to the j-th row of the above matrix, and X (i, g, t) is a voltage waveform generated by the i-th X drive circuit. In the voltage waveform generated at the th time t, the voltage waveform applied to the i-th row of the matrix, a (g), b (g) is at least one of the parameter values depending on g, J (i, j, g) is a value based on the display data of the i-th row and the j-th column of the above matrix, and when a high voltage effective value is given to the matrix intersection of the i-th row and the j-th column in the g-th time division section,
1. When giving a low voltage effective value, 1. φ (j, g, t) is an orthogonal function with a constant norm. That is, ∫dtφ (i, g, t) φ (j, g, t) = 0 i ≠ j ∫dtφ (i, g, t) φ (j, g, t) = const (constant) i = j , The integration range covers the entire g-th time division section of interest within one frame period. 12. The method of driving a display device according to claim 11, wherein the time interval and the applied voltage value are set so that the time division is as evenly divided as possible. 13. When the applied voltage cannot be applied beyond an allowable range, the time division of the time division and the applied voltage value are set so that the application time is extended as much as the applied voltage value is suppressed. A method of driving a display device according to claim 11. 14. A liquid crystal is used as the substance.
Driving method of the display device of paragraph. 15. A matrix panel comprising N row electrodes and M column electrodes, a column driver for applying a voltage to the column electrodes according to display information, and a row for applying a scanning voltage to the row electrodes. And a dot at the intersection of the row electrode and the column electrode for controlling the display state of the dot based on the effective value of the voltage difference between the voltage waveforms applied to the row electrode and the column electrode. In a matrix display device, display information including gradation information is divided for each gradation information and given to the column driver, and at least one of the column driver and the row driver is divided for each divided period. A method of driving a display device, wherein the output voltage levels are different. 16. The method for driving a display device according to claim 15, wherein the row driver is the only target of which the output voltage level is changed for each divided period. 17. The method of driving a display device according to claim 15, wherein the display information is stored in a memory, data is read from the memory for each gradation information, and the read data is given to the column driver. 18. The method according to claim 15, wherein the display information is stored in a memory, the display information is read from the memory, data to be given to the column driver is calculated, and the data after the calculation is given to the column driver. Driving method of display device. 19. A method for driving a display device in which substances whose optical characteristics change in accordance with an effective value of an applied voltage are arranged in a matrix, the method corresponding to n-bit data indicating a gray scale of the display device. Almost 1 / n of the scanning unit time of the display device
The driving method of the display device, wherein the applied pressure is controlled according to the brightness indicated by each bit of the n-bit data every time period corresponding to.