JPH08160392A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: To suppress the cross talk of a liquid crystal display device which can perform gradation display using a pulse width modulation system. CONSTITUTION: This device is provided with a gradation counting means 101 counting gradation data of a digitized data signal, a correction quantity deciding means 102 deciding correction quantity of voltage applied to liquid crystal elements from the counted result in the gradation counting means 101, and an applied voltage correcting means 103 correcting voltage applied to liquid crystal elements in accordance with correction quantity decided by the correction quantity deciding means 102, each gradation numbers included in each scanning signal is counted, and a pulse width of a data signal is varied in accordance with the counted result.

Description

Detailed Description of the Invention

[0001]

[Industrial applications]

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have been widely used in liquid crystal televisions, personal word processors, personal computers and the like as low power consumption and lightweight display devices. In order to display more image information in the future, it is expected that the number of pixels and the number of gradations will increase.
Such an increase in the number of pixels and the number of gradations means an increase in the capacity of display image information. As a result, the scanning period of one line of the liquid crystal display device is gradually shortened, and gradations have been controlled more finely. .

As a method for controlling the gradation of such a liquid crystal display device, a frame modulation method for controlling the gradation between a plurality of frames and a control of the pulse height and the pulse width of the data signal within the selection period are performed. A pulse height modulation method and a pulse width modulation method have been conventionally used.

Among them, the pulse width modulation method divides the horizontal selection period into a plurality of periods according to the number of gradations, and changes the period for adding the ON component to the data line in the horizontal selection period, that is, the write pulse width. In this way, gradation display is performed. FIG. 15 shows changes in the voltage waveform output to the data lines when 3-bit digital data is used as gradation data and the number of gradations is 8 (all ON, all OFF, and 6 halftones). .

When the alternating signal FR is High, the digital gradation data (D2.D1.D0.) Is (0.0.
0. ), The selection period (Th)
The OFF voltage Vx1 is always output, and the ON voltage Vx2 period is output longer as the grayscale data value increases. Digital gradation data (D2.D
1. D0. ) Is (1.1.1.) In the all ON state, the ON voltage is always output during the selection period (Th).

When the alternating signal (FR) is LOW,
The ON voltage is Vx1 and the OFF voltage is Vx2. Similarly, the larger the value of the gradation data, the longer the period for outputting the ON voltage. Th in the figure is a period in which one scanning line is selected, and corresponds to one horizontal scanning period in a normal liquid crystal display device.

FIG. 16 is a diagram showing ideal driving voltage waveforms (scan signal, data signal, difference signal thereof) when the pulse width modulation method is applied to a simple matrix.
FR in the figure is the alternating signal shown in FIG. Three levels of scanning signal (COM) (Vy1, Vy2, Vy
3) to the data signal (SEG) with a binary voltage level (V
x1, Vx2) are used.

When halftone gradation information is given as digital gradation data, a corresponding voltage waveform (SEG) is output to the signal electrode. The SEG rises and falls slightly later than the rising and falling timings of the alternating signal (FR). FIG.
In the above, as the SEG, a waveform that gives the same gradation display on all lines has been illustrated, but in general, a unique rising / falling timing is given to each line.

During the selection period (Ts), the alternating signal (F
When R) is HIGH, the voltage level of Vy3 is output as the scanning signal, and when it is LOW, the voltage level of Vy2 is output as the scanning signal. Further, Vy1 is output as a scanning signal during the non-selection period (Tns). In FIG. 16, the m-th scan electrode is selected during the Ts period and outputs the voltage waveform of COMm shown in the figure. Thus, when the scanning signal and the data signal are given, the difference signal (SEG-C
OMm) is the voltage applied to the liquid crystal element. As a result, the longer the time (Ton) applied with the ON voltage, the higher the effective voltage applied to the liquid crystal element,
Becomes shorter, the effective voltage applied to the liquid crystal element becomes lower. In this case, in a normally white type liquid crystal display device (a type in which the transmissivity is reduced as the voltage is applied to the liquid crystal layer is increased), the transmissivity of the liquid crystal display device increases as the grayscale data value increases. Get lower.

FIG. 16 shows wiring resistances of scanning lines and data lines,
It is an ideal voltage waveform on the assumption that there is no output impedance of the drive IC. In an actual liquid crystal display device, capacitive coupling occurs via a liquid crystal element due to switching of a data voltage on a data line, which causes voltage distortion (hereinafter referred to as crosstalk noise) of a scanning signal.

FIG. 17 shows a scanning signal (CO) by capacitive coupling of the data signal (SEGn) and the data signal (SEG1).
It is the figure which showed the mode that the crosstalk noise was mixed in (Mm). Due to the mixing of the crosstalk noise, the effective value of the voltage waveform (SEGn-COMm) applied to the liquid crystal layer becomes lower than the ideal waveform shown in FIG. 16, and as a result, the transmittance of the liquid crystal display device varies. Resulting in. This change in transmittance is called crosstalk. The crosstalk is further increased due to an increase in driving voltage due to an increase in the number of gradations and an increase in the number of display dots in one line, which hinders good image display.

A technique for correcting such crosstalk noise to improve the display quality of a liquid crystal display device has already been proposed in the past, and its specific configuration is disclosed in Japanese Patent Laid-Open No. 3-300.
No. 260621. FIG. 18 is a diagram for explaining the operation of the conventional method. The effective voltage of the scanning line is
It decreases due to the switching of the voltage level of the data line (scan voltage before correction). In the above-mentioned conventional technique, in order to correct this decrease in effective voltage, the number of gradation data that is not all ON and not all OFF is counted, and the correction voltage ΔV is set to the voltage level of the scanning electrode based on the counted value. Was added to improve crosstalk.

[0013]

However, in the above-mentioned prior art, when the correction voltage generated by the crosstalk noise is added to the scanning signal, it is necessary to set the correction voltage value very finely, so that the resolution is very high. There was a problem that an expensive DA converter had to be used.

Further, the above-mentioned prior art cannot be applied to a liquid crystal display device using a non-linear element capable of displaying image information of higher definition and higher quality than the simple matrix type liquid crystal display device. There was a point.

The problems of the prior art will be described in detail below.

Non-linear elements used in liquid crystal display devices include 3-terminal elements represented by amorphous silicon TFT elements and 2-terminal elements represented by MIM (conductor-insulator-conductor) elements. . In both cases, the switching function of the non-linear element is used to increase the number of drive lines and display a large amount of image information.

The two-terminal type element includes the MIM element described above, a back-to-back diode element, a diode ring element, a varistor element, etc., but each element has a non-linear current-voltage characteristic. are doing.

FIG. 19 is a diagram showing the current-voltage characteristics of the MIM element most widely used as a two-terminal type non-linear element. The horizontal axis represents the voltage applied to the MIM element and the vertical axis represents the current, and it can be seen that the current-voltage characteristics are non-linear.

FIG. 20 is a diagram showing an equivalent circuit of one pixel of the liquid crystal display device using the MIM element. Drive voltage is V
D, the voltage applied to the liquid crystal layer is VLC, and the voltage applied to the MIM element is VMIM. RLC and CLC are the resistance and capacitance of the liquid crystal layer, and RMIM and CMIM are
The resistance value and the capacitance value of the MIM element are shown. In an actual liquid crystal display device, the equivalent circuit shown in FIG. 20 is arranged in a matrix.

FIG. 21 shows an ideal waveform when driving a liquid crystal panel using a two-terminal type non-linear element. When pulse width modulation is performed using four voltage levels (VY1 to VY4) on the scanning side to suppress leakage during the non-selection period and two voltage levels (VX1 and VX2) on the data side It is an ideal waveform. The alternating method is an example in which frame inversion and one line inversion are performed.

The drive waveform of the data signal is similar to that of the simple matrix type liquid crystal display device shown in FIG. When an intermediate value is given to the drive system on the data line side as grayscale data, the SE in the figure is connected to the data line as in the case of FIG.
The voltage waveform indicated by G is output.

Here, during the selection period (Ts), the voltage level of VY4 is output as a scanning signal when the alternating signal (FR) is High, and the voltage level of VY2 is output when it is LOW. In the non-selection period (Tns),
VY1 or VY2 is output as a scanning signal. As a result, the voltage waveform indicated by COM shown in FIG. 21 is output.

When a voltage is applied to the scanning line and the data line in this way, the difference voltage between the scanning voltage and the signal voltage (SEG-CO
M) is the drive voltage (VD) applied between the liquid crystal element and the MIM element shown in FIGS. 20 and 21.

FIG. 22 shows the drive voltage (VD), the voltage applied to the liquid crystal layer (VLC) and the voltage applied to the MIM element (VMIM) when the gradation data is halftone data. When displaying the grayscale data, a period in which the voltage applied to the MIM element is high is a portion in which the data voltage is switched to the ON voltage level. In this portion, a current flows due to the non-linear characteristic of the MIM element, and the voltage rapidly increases in the liquid crystal element. Be charged.

Here, even when the non-linear element is used, as in the case of the simple matrix type liquid crystal display device shown in FIG. 17, the crosstalk noise due to the switching of the data line side is transferred from the data line to the scanning line side. And the MIM element and the liquid crystal layer through the capacitive portion. Therefore, the driving voltage (VD) actually applied to the liquid crystal layer and the MIM element is changed by the crosstalk noise, unlike the case of the ideal waveform. As a result, even when the same gradation data is given to a certain pixel, the transmittance varies depending on the display pattern of another pixel. The change in transmittance due to this display pattern will be described in detail with reference to FIGS. 23 and 24.

FIG. 23 is a diagram showing three types of data displayed on one line, and the pixel whose transmittance is observed is the Nth point. The pattern of (a) is the same halftone data for all the data of one line, and the pattern of (b) is the halftone data for only the observed pixels and all the on-data for the other part. In the pattern (a), the same halftone data is often present, and all the data signals change at the same timing, so that a large amount of crosstalk noise occurs. (B)
The pattern is a state in which crosstalk noise hardly occurs because it is only due to the observed pixels.

FIG. 24 shows a normally white type liquid crystal display device, which is shown in FIGS. 23 (a) and 23 (b).
Writing pulse width (TON
It is a figure which shows the relationship between (period) and transmittance. The horizontal axis represents the write pulse width of the observation pixel. When the write pulse width is 0, it corresponds to the all OFF state, and the write pulse width in one scanning period corresponds to the all ON state. The vertical axis represents the transmittance at each writing pulse width. The gradation characteristic (2401) of the pattern (a) in which the driving voltage decreases due to crosstalk noise has higher transmittance than the gradation characteristic (2402) of the observation point of the pattern (b) written with the same pulse width. It can be seen that crosstalk that deteriorates the image quality is occurring. This means that the voltage actually applied to the liquid crystal varies depending on the display pattern of one line.

Further, when a halftone different from the observation point is displayed on the data line other than the observation point N as in the pattern (c) shown in FIG. 23, crosstalk caused by the switching of the data signal other than the observation point N・ Noise is at observation point N
The higher the voltage applied to the MIM element, the greater the degree of influence. This difference in the degree of influence will be described with reference to FIG.

In FIG. 25, the voltage applied to the MIM element at the observation point N has the waveform shown by 2501 as in the VMIM shown in FIG. When the driving voltages of the data lines other than the observation point N are 2502 and 2503, the data signal 2502
Since the crosstalk noise generated by 1) is generated during the TE period when the voltage applied to the MIM element is at a high level, the crosstalk noise causes a large variation in the voltage applied to the liquid crystal as compared with the crosstalk noise generated by the data signal 2503. That is, the crosstalk noise of each gradation has a different influence depending on the gradation data to be displayed.

Therefore, the method of correcting the voltage on the scanning electrode side by obtaining the average value of crosstalk noise as in the prior art is effective for a simple matrix type liquid crystal display device, but uses a non-linear element. However, this is not effective for the liquid crystal display device, and gradations that are too large or small to be corrected are mixed, which further deteriorates the image quality.

As described above, in the conventional liquid crystal display device, the voltage of the scanning electrode due to the resistance of the driving electrode of the liquid crystal optical element, the output resistance of the driver IC, and the capacitance of the liquid crystal element causes the liquid crystal element on the same scanning line. There is a problem in that the effective voltage applied to the device fluctuates, the gradation corresponding to the display data cannot be displayed faithfully, and crosstalk occurs.

Further, in the conventional technique for improving this problem in the simple matrix type liquid crystal display device, there is a problem that a DA converter having a high resolution must be used. Further, such a conventional technique has a problem that not only the crosstalk of the liquid crystal display device having the non-linear element cannot be suppressed but also the display quality is further deteriorated.

Therefore, the present invention has been made for the purpose of providing a liquid crystal display device which solves such a problem.

[0034]

A liquid crystal display device of the present invention comprises: a) a plurality of scanning lines, a plurality of data lines, and a plurality of liquid crystal elements selected by the scanning lines and the data lines. A liquid crystal panel having: b) a scanning signal drive circuit for supplying a scanning signal to the plurality of scanning lines, and a data signal drive circuit for supplying a data signal to the plurality of data lines, A liquid crystal display device capable of performing gradation display by using a pulse width modulation method, and d) further digitized data. Gradation counting means for counting the gradation data of the signal; e) correction amount determining means for determining the correction amount of the voltage applied to the liquid crystal element from the counting result of the gradation counting means; and f) the correction amount determination. Correction determined by means It characterized by having a a applied voltage correction means for correcting a voltage applied to the liquid crystal element according to.

Further, in the liquid crystal display device of the present invention, in the liquid crystal display device, each of the liquid crystal elements is electrically connected to a non-linear element, and the non-linear element and the liquid crystal element are connected to the data line. It is characterized in that it is arranged electrically in series with the scanning line.

Further, in the liquid crystal display device of the present invention, in the liquid crystal display device, at least one gray scale data of a data signal applied to the liquid crystal element selected by the scanning line by the gray scale counting means. It is characterized in that counting is performed for each of the above gradations.

Further, the liquid crystal display device of the present invention is characterized in that, in such a liquid crystal display device, the correction amount determining means weights the count result of the gradation counting means to determine the correction amount. .

Furthermore, in the liquid crystal display device of the present invention, in such a liquid crystal display device, the applied voltage correction means applies the voltage to the data line according to the correction amount determined by the correction amount determination means. It is characterized in that the pulse width and / or the pulse height of the data signal is changed for correction.

[0039]

According to the invention of claim 1, d) a gray scale counting means for counting gray scale data of a digitized data signal, and e) a voltage applied to the liquid crystal element based on a count result of the gray scale counting means. A correction amount determining means for determining a correction amount; and f) an applied voltage correcting means for correcting the voltage applied to the liquid crystal element according to the correction amount determined by the correction amount determining means. Therefore, it is possible to count each gradation data included in the data signal and increase or decrease the voltage applied to the data line for each gradation according to the count result. As a result, it is possible to correct the fluctuation of the effective voltage applied to the liquid crystal element, which changes depending on the display pattern, and suppress crosstalk.

According to a second aspect of the present invention, each of the liquid crystal elements is electrically connected to the non-linear element, and the non-linear element and the liquid crystal element are electrically arranged in series between the data line and the scanning line. Therefore, it is possible to display a large-capacity liquid crystal panel as compared with a simple matrix type liquid crystal display device. Further, the crosstalk of a liquid crystal display device having a non-linear element is greatly affected by the period in which crosstalk noise is generated. Even in such a case, the fluctuation amount of the effective voltage applied to the liquid crystal element which changes depending on the display pattern. Can be corrected more effectively than the conventional one, and as a result, crosstalk can be effectively suppressed.

Further, the invention of claim 3 is characterized in that the gradation counting means counts the gradation data of the data signal applied to the selected liquid crystal element for each of at least one gradation. , It is possible to correct the display of all gradations, and when a plurality of gradations requires the same correction, the circuit for counting the correction amount becomes unnecessary, and the circuit scale can be reduced. .

Further, the invention of claim 4 is characterized in that the correction amount determining means weights the counting result of the gradation counting means to determine the correction amount, so that the liquid crystal using a non-linear element as a switching element. Even when gradation display is performed by the pulse width modulation method in the display device, it is possible to correct the fluctuation of the effective voltage due to the change of the voltage applied to the data line of the liquid crystal element to which the selection voltage is simultaneously applied by the scanning line.

Further, the invention of claim 5 is characterized in that the applied voltage correcting means performs the correction by changing the pulse width of the data signal according to the correction amount determined by the correction amount determining means. The voltage level for driving the panel does not have to be increased, the circuit for correction can be realized by a simple logic circuit, and the cost can be reduced because it can be easily integrated into an IC.

Further, the invention of claim 6 is characterized in that the applied voltage correcting means corrects by changing the pulse height of the data signal according to the correction amount determined by the correction amount determining means. A circuit for correcting the pulse width of the voltage applied to the data line is unnecessary, and the scale of the logic circuit can be reduced.

Further, the invention of claim 7 is characterized in that the applied voltage correcting means corrects by changing both the pulse width and the height of the data signal in accordance with the correction amount determined by the correction amount determining means. Therefore, fine correction can be performed, and crosstalk can be effectively removed even if the number of gradations increases.

[0046]

【Example】

 Example 1 The present invention will be described below with reference to FIG.

FIG. 1 is an overall block diagram of the liquid crystal display device of the present invention. The gradation counting means 101 uses the mask signal 10
7 and the data clock 109, the gradation data 10
8 is counted, and the counting result 111 is output to the correction amount determining means 102. Here, the mask signal 107 is the gradation data 1
08 is active during the period in which the gradation data to be actually displayed is sent.

The correction amount determining means 102 includes a data clock 109, a line clock 110, and the counting result 11
The correction amount data 112 is determined based on 1 and the result is output to the applied voltage correction means 103.

The applied voltage correction means 103 generates an applied voltage correction signal 113 based on the data clock 109 and the correction amount data 112, and the data signal drive circuit 1
Output to 04.

The data signal drive circuit 104 stores the gradation data 108 counted by the gradation counting means 101 in the shift register. Grayscale data 1 held in the shift register
08 is the data line X based on the line clock 110.
Each data signal is output to 1 to Xm.

The scanning signal drive circuit 105 sequentially outputs selection voltages from Y1 to the scanning lines Y1 to Yn, and the liquid crystal panel 1
No. 06 liquid crystal element is driven in a time division manner.

One embodiment of the present invention will be described in more detail with reference to FIGS.

FIG. 2 is a diagram in which the present invention is applied to a 640 dot × 480 dot MIM liquid crystal display device which performs gradation display of 8 gradations by a pulse width modulation method.

The gray scale counting circuit 201 is provided with gray scale data 209.
Then, the counting result 212 is generated based on the mask signal 208 and the data clock 210. The operation of the gradation counting circuit 201 will be described in more detail with reference to FIGS. 3 and 6.

FIG. 3 is a block diagram of the gradation counting circuit, and FIG. 6 is a timing diagram thereof. The block 312 for counting the correction amount of gradation 7 in FIG. 3 includes a decoder 301, a weighting circuit 302, a logical sum 303, and a counter 304. The gradation data 305 expresses 8 gradations using 3-bit digital data, and since a gradation counting block is provided for each gradation data, the gradation counting circuit is composed of 8 blocks. To be done. The valid period of the gradation data is given by the mask signal 306. Gradation data is 7
In the block 312 corresponding to, the decoder 301 decodes the grayscale data 305 to 7 by the decoder 302. The decoded signal 308 is the weighting circuit 302.
Are weighted to 3 levels. The weighting circuit 302 is
The decode signal 308 whose gradation data is 7 is weighted to three levels and output at the timing shown in FIG. The weighting signal 309 includes a weighting signal 1, a weighting signal 2 and a weighting signal 3. The weighted signal 1 for the gradation data value 7 is the decoding result of the gradation data 7 being h
All periods that are high are high. The weighting signal 2 becomes high for 1 clock when the value of the gradation data is 7 for 2 clocks. That is, the period becomes high, which is a half of the period in which the gradation data is 7. Weighting signal 3
Becomes high for one clock when the value of the grayscale data is 7 for three clocks. In this way, a 3-level weighting signal is generated for each gradation data.

For the logical sum within the counting block of each gradation, the degree of influence due to the change of the gradation pulse of all the gradations is classified into four levels, and the weighting circuit of the block corresponding to the gradation having the large influence degree is used. Is input with the weighting signal 1 having the largest weight. The weighting signal 2 is input from the weighting circuit of the gradation classified into the next influence level, and further, the weighting signal 3 is input from the weighting circuit corresponding to the gradation having the next influence, and the weighting signal 3 is input most. The weighting signals of the gradations classified into the lesser degree of influence are not input. For example, if only the weighting signal 1 of the gradation 6 is input to the logical sum 303 of the block 312 corresponding to the gradation data value 7, the output of the logical sum 303 of the block 312 is the enable of the counter 304. Since the signal is input as the signal 310, the output of the counter 304 is incremented by 1 in synchronization with the data clock 307 while the output of the logical sum is active (active high). When inactive, the output value is held without adding. If the gradation data value displayed on all the liquid crystal elements to which the selection voltage is applied to the scanning line is 7, the number of liquid crystal elements per scanning line is 640. The value of the count result 311 of the counter corresponding to the block of 7 is 640. If the gradation information 7 is 320 and the gradation 6 is 320, the value of the count result 311 of the counter corresponding to the block of which the gradation data value is 7 is 480.

In this way, the counting result 212 (FIG. 2) counted by using the gradation counting circuit 201 is input to the correction amount determining circuit 202. The correction amount determination circuit 202 generates a load signal 213, correction amount data 214, and an enable signal 215 based on the counting result 212, the line clock 211, and the data clock 210. The operation of the correction amount determination circuit 202 of FIG. 2 will be described below with reference to FIGS. 4, 5 and 7.

FIG. 4 is a block diagram of the correction amount determining circuit, and FIG.
Is a block diagram of a gradation display basic clock generation circuit, and FIG. 7 is a timing diagram thereof. In FIG. 4, the controller 401 uses the correction amount table RO based on the line clock 407 that gives the beginning of one scanning period and the data clock 410 that gives the latch timing of the grayscale data.
A selection signal 405 for selecting the result of counting the gray scales given as the address of M403 is generated.

The selector 402, based on the value of the 3-bit selection signal 405 output from the controller 401,
One of the grayscale count results 404 is output to the correction amount table ROM 403 as an address. In the correction amount table ROM 403, correction amount data corresponding to the counting result of each gradation is written. The correction amount data ROM 403 stores the selected counting result 40
6 is input as the lower address, and the selection signal 405 is input as the upper address. Then, the correction amount data R
The OM 403 outputs the correction amount data 409 corresponding to the counting result of each gradation.

Next, the operation of the correction amount determining circuit will be described with reference to the timing chart of FIG.

First, the falling edge of the line clock 407 is detected and the selection signal 405 is set to 0. Selection signal 4
Reference numeral 05 is a 3-bit signal having a value of 0 to 7, and the selector 402 selects and outputs the counting result of gradations 0 to 7 corresponding to the value of the selection signal 405 of 0 to 7. That is, during the period when the selection signal 405 is 0, the value a which is the count result 0 is selected and output to the correction amount data ROM 403. Then, according to the output of the selection signal 405 which is counted up in synchronization with the data clock 410, the counting results 0, 1, 2, ...
.. Outputs values of 7, a, b, c, ... H. With this input, the correction amount data ROM 403 outputs A, B, C, ... H as the corresponding correction amount data 409. In addition, the controller 401 causes the counter 501 of FIG. 5, which will be described later, to load 0 to 0 as load signals 411 for latching the correction amount data output from the correction amount data ROM 403 in the gradation display basic clock generation circuit 203 of FIG. Load7 is output at the timing shown in FIG.

In this way, a load signal for each gradation is output at the timing when the correction amount data for each gradation is output from the correction amount data ROM 403, and the correction amount data is output to the gradation display basic clock generation circuit in FIG. Loaded.
Further, in order to stop the counter 501 while the correction amount data 409 is loaded on the counter 501 of FIG.
08 is given at the timing shown in FIG.

Next, the gradation display basic clock generation circuit 203 of FIG. 2 will be described. The gradation display basic clock generation circuit 203 uses the load signal 213 and the correction amount data 214.
Then, the gradation display basic clock 216 is generated based on the count enable signal 215. Here, the gradation display basic clock will be described with reference to FIG. As shown in FIG. 26, the gradation display basic clock applies the applied voltage of the data line to each liquid crystal element to which the selection voltage is applied by the scanning line according to the gradation to be displayed on each liquid crystal element. Is a signal for generating timing for. The data signal drive circuit 204 of FIG.
Clocks corresponding to the number of display gradations are applied during the scanning period, and the applied voltage to the data line is turned off at the falling edge of each clock.
Change from voltage to ON voltage. For example, when displaying a gradation 5 on a liquid crystal element, data is output from the trailing edge of the third gradation display basic clock during the scanning period in which the scanning line connected to the liquid crystal element is applied with the selection voltage. The ON voltage is applied to the line and changed to the OFF voltage at the end of the scanning period. As for the other gradations, as shown in FIG. 26, ON for displaying each gradation from the fall of the gradation display basic clock corresponding to each gradation.
The timing of the beginning of the voltage application period is obtained.

The operation of the gradation display basic clock generation circuit 203 will be described with reference to FIG.

FIG. 5 is a block diagram of the gradation display basic clock generation circuit.

The gradation display basic clock generation circuit of FIG.
As shown in FIG. 5, a counter 501 for each gradation,
The block 512 includes a decoder 502 that generates the output timing of the grayscale display basic clock, and the logical sum 503 of the signals that generate the timing of the grayscale display basic clock output from each block is used as the logical sum. The bird
The D flip-flop 510 removes the hazard and generates the gradation display basic clock 511 described above.

Next, the operation of the gradation display basic clock generation circuit will be described with reference to the timing chart of FIG.

From the upper block of FIG. 5, gradation 7, gradation 6,
If the gray level 7 corresponds to gray level 0, the gray level 7 counter 501 counts up when the counter enable signal 505 output from the controller 401 in FIG. 4 is active (active low). The correction amount data 504 is loaded by the load signals 513 to 515 into the counter provided for each gradation while the enable signal 505 is inactive, and the counter starts counting up from the value of the correction amount data 504. become. The output 506 of the counter corresponding to gradation 7 is decoded by the decoder 502. The decoder 502 generates a timing corresponding to gradation 7 of the gradation display basic clock. For example, the value to be decoded is r (that is, gradation 7
R clock +2 from the beginning of the scanning period to display
The ON voltage starts to be applied in the period of one-half clock. ), Since the counter 501 is counting up from H, as shown in FIG.
The signal 507 for generating the timing of the gray scale 7 of the gray scale display basic clock is changed to high during the period of r-H clocks after 05 becomes active. In this way, if there is no correction (that is, no correction is necessary and 0 is loaded as the correction amount data in the counter 501), the floor is output at the timing of the period of r clocks from the fall of the enable signal. The signal 507 for generating the basic adjustment display clock is changed to high, but in this example, it is changed to high by the amount of H clocks (correction amount according to the gradation of other liquid crystal elements on the same scanning line). I'm accelerating the timing.

As a result, the timing of applying the ON voltage to the data line can be advanced by the amount of H clocks, and the decrease of the effective voltage applied to the liquid crystal element can be corrected. Similarly, if s is to be decoded at gray level 6, the counter counts up from G, so from the fall of the enable signal to gray level 6 of the gray scale display basic clock in the period of s-G clocks. Corresponding timing is generated and the application period of the ON voltage of the data line is increased by the period of G clocks. Below gradation 5 to gradation 0
The same is true.

The timing signals corresponding to the respective gradations of the eight gradation display basic clocks are logically ORed by the logical OR 503, and the data clock 50 by the D flip-flop 510.
It is latched at the trailing edge of 8 and the hazard is removed by decoding to output it as the gradation display basic clock 511 to the data signal drive circuit 204 of FIG.

Next, the operations of the data signal drive circuit 204 and the scan signal drive circuit 205 will be described with reference to FIGS. 2 and 9. The data signal drive circuit 204 uses the data clock 21
The grayscale data 209 is fetched by 0, synchronized with the line clock 211, and the timing for applying the ON voltage is obtained by the grayscale display basic clock 216. Further, VDD and VEE input from the drive voltage generation circuit 206 are selected by the AC signal 217, and the ON voltage and OF are applied to the data line.
F voltage is applied. The scanning signal drive circuit 205 sequentially applies a selection voltage to each scanning line in synchronization with the line clock 211. MIM element and liquid crystal element,
A voltage as shown in FIG. 9 is applied.

The gray-colored portion of the data line Xi is the correction voltage. In the T1 scanning period, the write pulse width correction is performed in the ΔT period.

As described above, the ON is corrected in consideration of the variation (decrease in this embodiment) of the effective voltage due to the variation of the voltage applied to the data line of the liquid crystal element to which the selection voltage is simultaneously applied by the scanning line. By applying a voltage, it is possible to apply an effective voltage that is suitable for displaying gray scales to the liquid crystal element, and this eliminates fluctuations in the effective voltage for each scanning line, thus eliminating crosstalk caused by the display pattern. It is possible to effectively suppress, and as a result, it is possible to display a beautiful image without display unevenness.

In this embodiment, the correction is performed for each gradation, but between gradations where the application time of the on-voltage of the data line is close,
Since there is little difference between the gradations in the variation of the effective voltage due to the display pattern, it is possible to correct each of such gradations. In this case, the circuit scale can be reduced. The method of weighting the counting result can be handled by changing the number of weighting levels according to the desired display quality.

Further, not only the MIM element of this embodiment but also a liquid crystal panel using another non-linear element whose current-voltage characteristic is non-linear as a switching element can be similarly corrected.

Further, since the present invention corrects the voltage applied to the data line in one line, the same effect can be obtained not only in the one-line inversion drive of the present embodiment but also in the frame inversion or plural line inversion drive. .

Although the present embodiment is a liquid crystal display device for displaying 8 gradations, the number of display gradations is not limited to 8 gradations, and is 16, 32, and 6.
It can be applied even if the number is increased to 4. In such a case, the circuits provided for 8 gradations in this embodiment are replaced with 16, 32, 6
4 and the gradation may be provided.

Here, it is conceivable that if a circuit corresponding to all gradations is provided, the circuit scale becomes large. However, when the number of gradations increases, the timing of starting to apply the ON voltage to the data line becomes closer between the adjacent gradations, and therefore the influence of the crosstalk noise on the display hardly changes between the adjacent gradations. Come on. Therefore,
By configuring such a circuit by considering such a plurality of gradations as one block, an appropriate circuit scale can be maintained even if the number of gradations increases.

[Embodiment 2] Next, referring to FIG.
It demonstrates using 0-FIG. As in Example 1, 64
The present invention is applied to an MIM liquid crystal display device of 0 dot × 480 dot, 8-gradation display.

FIG. 10 is a block diagram of this embodiment, FIG. 11 is a block diagram of the gradation voltage correction circuit, and FIG. 12 is an applied voltage waveform diagram.

The gradation counting circuit 1001 and the correction amount determining circuit 1002 operate in the same manner as in the first embodiment. Gradation counting circuit 1
001 is gradation data 1008, data clock 100
9 and the mask signal 1011 to generate a gradation count result 1012. The correction amount determination circuit 1002 includes a data clock 1009, a line clock 1010, and a counting result 101.
2, the load signal 1013 and the correction amount data 10
14 is generated. The gradation voltage correction circuit 1003 generates a gradation voltage 1016 (a gradation voltage for 8 gradations) based on the data clock 1009, the load signal 1013, and the correction amount data 1014.

A gradation voltage correction circuit 1003 will be described with reference to FIG.
Will be described. The correction amount data 1104 is latched by the data clock 1105 in the latch circuit 1101 corresponding to gradation 0 when the load signal 1106 is active. Subsequently, the correction amount data 1104 corresponding to the gradation 1 is latched by the load signal 1107, and finally the correction amount data 1104 for the gradation 7 is latched by the load signal 1108. The latched correction amount data is loaded into the D flip-flop 1113 at the next stage by the line clock 1112, and the D / A converter 1102 outputs the grayscale voltage 1109 and the grayscale 1 corresponding to the grayscale 0 according to the value. The corresponding gray scale voltage 1110 and the gray scale voltage 1111 corresponding to the gray scale 7 are output.

The data signal drive circuit 1004 outputs the grayscale data 1008 to the mask signal 1011 and the data clock 10.
09, the line clock 1010 and the gradation display basic clock 1015 determine the application timing of the ON voltage of the data line, further select eight gradation voltages, and the application voltage level and the application timing of the ON voltage. To decide. As shown in the applied voltage waveform diagram of FIG. 12, in the period of T1, the height of the ON voltage applied to the data line is increased by ΔV of the gray-painted portion, and the write correction voltage is applied to the liquid crystal element. Correct the fluctuation of the effective voltage.
In this way, the correction voltage is changed according to the change of the effective voltage of each gradation, and the write voltage is corrected.

As described above, it is possible to apply an appropriate effective voltage to the liquid crystal element by correcting the decrease in the effective voltage depending on the ON voltage of the data line.
The fluctuation of the effective voltage is eliminated for each scanning line, and the crosstalk caused by the display pattern can be effectively suppressed, and as a result, a clear image without display unevenness can be displayed.

[Embodiment 3] Next, referring to FIG.
3 and FIG. 14. Similar to Example 1,
The present invention is applied to an MIM liquid crystal display device of 640 × 480 dots and 8-gradation display. FIG. 13 is a block diagram of the present embodiment, and FIG. 14 is an applied voltage waveform diagram.

A gradation counting circuit 1301, a correction amount determining circuit 1302, and a gradation display basic clock generating circuit 1303.
Then, the gradation voltage correction circuit 1303 operates similarly to the first embodiment, and the gradation voltage correction circuit 1304 and the data signal drive circuit 1305 operate similar to the second embodiment. The gradation counting circuit 1301 generates a gradation counting result 1312 based on the gradation data 1308, the data clock 1309, and the mask signal 1311. The correction amount determination circuit 1302 includes a data clock 1309, a line clock 1310,
A load signal 1313 and correction amount data 1314 are generated based on the counting result 1312. The gradation display basic clock generation circuit 1303 generates a gradation display basic clock 1315 based on the data clock 1309, the load signal 1313, and the correction amount data 1314, and the gradation voltage correction circuit 1304 arranged in parallel with the gradation display basic clock 1315. Is the data clock 1309, the load signal 1313, and the correction amount data 13
Based on No. 14, gradation voltages 1316 to 1318 (voltages for eight gradations) are generated. The data signal drive circuit 1305 is
Gradation data 1308 is fetched with a mask signal 1311 and a data clock 1309, the application timing of the ON voltage of the data line is determined by the line clock 1310 and the gradation display basic clock 1315, and eight gradation voltages are selected. Determine the applied voltage level. As shown in the applied voltage waveform in FIG. 14, in the period of T1, the pulse width is increased by ΔT and the pulse height is increased by ΔV only in the portion where the ON voltage applied to the data line is shaded in gray. Then, the write correction voltage is applied to correct the fluctuation of the effective voltage applied to the liquid crystal element.

In this way, the correction voltage is changed according to the change of the effective voltage of each gradation, and the write voltage is corrected.

As described above, by correcting the decrease of the effective voltage according to the width and height of the voltage applied to the data line, it is possible to apply the appropriate effective voltage to the liquid crystal element.
This eliminates fluctuations in effective voltage for each scan line,
Crosstalk caused by the display pattern can be effectively suppressed, and as a result, a clear image without display unevenness can be displayed.

Further, in the configuration of the present embodiment, both the width and the height of the ON voltage are changed and the correction is performed, so that it is possible to perform a finer correction. As a result, the embodiment 1 or 2
Crosstalk can be suppressed more effectively than in the case of the above configuration.

[0090]

The liquid crystal display device of the present invention can effectively suppress crosstalk caused by a display pattern, and as a result, can display a clear and even image.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a block diagram of the first embodiment.

FIG. 3 is a block diagram of a gradation counting circuit according to the first embodiment.

FIG. 4 is a block diagram of a correction amount determination circuit according to the first embodiment.

FIG. 5 is a block diagram of a gradation display basic clock generation circuit according to the first embodiment.

FIG. 6 is a timing chart of the gradation counting circuit according to the first embodiment.

FIG. 7 is a timing chart of the correction amount determination circuit according to the first embodiment.

FIG. 8 is a timing diagram of the gradation display basic clock generation circuit according to the first embodiment.

FIG. 9 is a liquid crystal drive voltage waveform diagram of the first embodiment.

FIG. 10 is a block diagram of a second embodiment.

FIG. 11 is a block diagram of a grayscale voltage correction circuit according to a second embodiment.

FIG. 12 is a liquid crystal drive voltage waveform chart of the second embodiment.

FIG. 13 is a block diagram of a third embodiment.

FIG. 14 is a liquid crystal drive voltage waveform diagram of the third embodiment.

FIG. 15 is an explanatory diagram of gradation display by a pulse width modulation method.

FIG. 16 is an ideal waveform diagram of pulse width modulation in a simple matrix.

FIG. 17 is a waveform diagram showing mixing of crosstalk noise in a simple matrix.

FIG. 18 is a diagram showing current-voltage characteristics of the MIM element.

FIG. 19 is an equivalent circuit diagram of one pixel of a liquid crystal display device using an MIM element.

FIG. 20 is an explanatory diagram of crosstalk of a conventional liquid crystal panel.

FIG. 21 is a waveform diagram of a voltage applied to a conventional liquid crystal panel.

FIG. 22 is an explanatory diagram of the influence of voltage distortion caused by halftone display.

FIG. 23 is a diagram showing data displayed on three types of one line.

FIG. 24 is a diagram showing gradation characteristics showing the relationship between the write pulse width and the transmittance.

FIG. 25: Crosstalk of voltage applied to MIM
The figure for demonstrating the influence degree with respect to noise.

FIG. 26 is a diagram showing a relationship between a gradation display basic clock and a voltage applied to a data line.

[Explanation of Codes] 101. Gradient counting means 102. Correction amount determining means 103. Applied voltage correction means 104. Data signal drive circuit 105. Scan signal drive circuit 106. Liquid crystal panel 107. Mask signal 108. Gradation data 109. Data clock 110. Line clock 111. Counting result 112. Correction amount data 113. Applied voltage correction signal 201. Gradation counting circuit 202. Correction amount determination circuit 203. Gradation display basic clock generation circuit 204. Data signal drive circuit 205. Scan signal drive circuit 206. Drive voltage generation circuit 207. MIM liquid crystal panel 208. Mask signal 209. Gradation data 210. Data clock 211. Line clock 212. Count result 213. Load signal 214. Correction amount data 215. Enable signal 216. Gradation display basic clock 217. AC signal 301. Decoder 302. Weighting circuit 303. Logical sum 304. Counter 305. Gradation data 306. Mask signal 307. Data clock 308. Decoding result 309. Weighted signals input to other gray level blocks 310. Enable signal of counter 304 311. Count result of each gradation 312. Gradation counting block 401. Controller 402. Selector 403. Correction amount table ROM 404. Counting result 405. Selection signal 406. Counting result selected by selection signal 405 407. Line clock 408. Enable signal for counter of gradation display basic clock 409. Correction amount data 410. Data clock 411. Load signal 501. Counter 502. Decoder 503. Logical sum 504. Correction amount data 505. Enable signal 506. Output of counter 507. Decode signal 508. Data clock 509. OR output 510. D flip-flop 511. Gradation display basic clock 513. Gradation 7 load signal 514. Gradation 6 load signal 515. Load signal of gradation 0 1001. Gradient counting circuit 1002. Correction amount determination circuit 1003. Gradation voltage correction circuit 1004. Data signal drive circuit 1005. Scan signal drive circuit 1006. Drive voltage generation circuit 1007. MIM liquid crystal panel 1008. Gradation data 1009. Data clock 1010. Line clock 1011. Mask signal 1012. Count result 1013. Load signal 1014. Correction amount data 1015. Gradation display basic clock 1016. Gradation voltage 1101. Latch circuit 1102. D / A converter 1103. Voltage correction block for gradation 0 1104. Correction amount data 1105. Data clock 1106. Load signal corresponding to gradation 0 1107. Load signal corresponding to gradation 1 1108. Load signal corresponding to gradation 7 1109. Correction voltage for gradation 0 1110. Correction voltage for gradation 1 1111. Correction voltage for gradation 7 1112. Line clock 1113. D flip-flop 1301. Gradient counting circuit 1302. Correction amount determination circuit 1303. Gradation display basic clock generation circuit 1304. Data signal drive circuit 1305. Scan signal drive circuit 1306. Drive voltage generation circuit 1307. MIM liquid crystal panel 1308. Gradation data 1309. Data clock 1310. Line clock 1311. Mask signal 1312. Counting result 1313. Load signal 1314. Correction amount data 1315. Gradation display basic clock 1316. Gradation voltage

Claims (7)

[Claims] 1. A) a plurality of scanning lines, a plurality of data lines,
A liquid crystal panel having a plurality of liquid crystal elements selected by the scanning lines and the data lines; b) a scanning signal drive circuit that supplies a scanning signal to the plurality of scanning lines; and data for the plurality of data lines. A data signal driving circuit for supplying a signal, and liquid crystal element driving means for driving the liquid crystal element using a time division driving method, and c) gradation display using a pulse width modulation method. In a liquid crystal display device capable of performing: d) a grayscale counting means for counting grayscale data of a digitized data signal; and e) applying to the liquid crystal element from the counting result of the grayscale counting means. A correction amount determining unit that determines a correction amount of the voltage; and f) an applied voltage correcting unit that corrects the voltage applied to the liquid crystal element according to the correction amount determined by the correction amount determining unit. To Crystal display device. 2. The liquid crystal element is electrically connected to a non-linear element, and the non-linear element and the liquid crystal element are electrically arranged in series between the data line and the scanning line. The liquid crystal display device according to claim 1, wherein: 3. The gray scale counting means counts gray scale data of a data signal applied to a liquid crystal element selected by the scanning line for each of at least one gray scale. The described liquid crystal display device. 4. The liquid crystal display device according to claim 3, wherein the correction amount determining means determines the correction amount by weighting the count result of the gradation counting means. 5. The applied voltage correction means corrects by changing the pulse width of a data signal applied to the data line according to the correction amount determined by the correction amount determination means. 4. The liquid crystal display device according to 4. 6. The applied voltage correcting means corrects by changing the height of a pulse of a data signal applied to the data line according to the correction amount determined by the correction amount determining means. The liquid crystal display device according to claim 4. 7. The applied voltage correction means corrects by changing both the pulse width and the height of the data signal applied to the data line according to the correction amount determined by the correction amount determination means. The liquid crystal display device according to claim 4.