JPH06230083A - Testing device - Google Patents

Abstract

PURPOSE:To inspect testing object circuits highly accurately at high speed by incorporating a pulse speed increasing testing circuit into a testing device. CONSTITUTION:A pulse speed increasing circuit 7 is arranged in the vicinity of a clock probe 5 in a passage to connect a pulse generating circuit 6 of a general testing device to the clock probe 5. In this constitution, a clock signal c2 generated from the pulse generating circuit 6 is inputted to the pulse speed increasing circuit 7, and a twofold speed pulse c3 is generated in this. This clock signal is supplied to an input pin, and data d2 is read in at the rise point. Thereby, according to this constitution, since the pulse speed increasing circuit is arranged in the vicinity of the clock probe 5, testing object circuits 1 and 2 can be inspected in the minimum vector cycle (t).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a tester for inspecting a board mounted with the semiconductor integrated circuit at high speed and with high accuracy.

[0002]

2. Description of the Related Art In recent years, information and communication systems, office automation (OA), factory automation (FA) and other information and intelligence have made remarkable progress. Higher reliability is required.

For example, in the field of electronic parts, semiconductor integrated circuits are highly integrated and highly functionalized, and passive parts such as resistors and capacitors are downsized, made into chips, and modularized. Has been planned. Also, in the mounting technology of the above electronic components, high integration and high density on the circuit board are required, and adoption of a multilayer circuit board is promoted due to demands for board multi-function, high frequency, and digitalization. Has been done.

Regarding the circuit test technique, when the circuit scale is relatively small and the circuit is mainly analog, it is possible to identify the failure point by monitoring the waveform of the signal line of the entire circuit during actual operation. Visual inspection was the mainstream, but in recent years, as digitization has progressed, surface mounting density has increased, and circuit scale has expanded, the above inspection methods have made it extremely difficult to identify the location of failure. It's getting harder. Therefore, the inspection method is also shifting from the method of inspecting the entire board to the method of inspecting individual electronic components mounted on the board. In addition, with the need for shortening the inspection time and the remarkable progress of automation, the current situation is that the automatic test equipment is being developed.

A conventional test apparatus will be described below.
FIG. 3 is a diagram showing a conventional example, and FIG. 3 (a) is an explanatory diagram of a conventional test apparatus, in which a path from a pulse generation circuit to an input pin of a semiconductor integrated circuit is simply shown. Further, (b) is an explanatory diagram of signal acquisition of the circuit under test.

In the figure, 1 is a semiconductor integrated circuit, 2 is a circuit board under test, 3 is a probe holding plate, 4 is a data probe, 5
Is a clock probe, and 6 is a pulse generation circuit.

The operation of the test apparatus configured as described above will be described below. First, the clock signal and the data signal generated by the pulse generation circuit 6 are supplied to the respective input pins of the semiconductor integrated circuit 1 via the clock probe 5 and the data probe 4. And
The signal appearing at the output pin of the semiconductor integrated circuit 1 is measured by a separately provided pulse measuring circuit. The circuit under test is passed or failed by comparing the measured data appearing at this output pin with the expected value obtained in advance.

FIG. 3B is a time chart for explaining the test pulse in the conventional test apparatus.
In the figure, c1 is a clock pulse, d1 is a data pulse, and t is the minimum pulse width that can be generated in the pulse generation circuit. Here, normally, in a semiconductor integrated circuit, input data is read at the rising edge of the clock, and therefore the data pulse width is limited to twice the minimum pulse width t or more in order to ensure the reliability of data input.

[0009]

However, in the above-mentioned conventional configuration, it is necessary to set the data pulse width sufficiently wide in order to ensure the reliability of data reading. When inspecting a semiconductor integrated circuit designed in 1), there is a defect that some items cannot be inspected. As a solution to these problems, a method of speeding up the pulse generation circuit itself can be considered, but in the case of a test device that tests the circuit board, the length of the wiring inside the circuit board and the wiring between the pulse generation circuit and the probe can It must be acknowledged, and considering the deterioration of the pulse waveform due to the inductance and stray capacitance of these wirings, there is a limit to the speedup of the pulse generation circuit itself.

The present invention solves the above-mentioned conventional problems, and its purpose is to inspect a circuit under test at a high speed and with high accuracy, and to provide an inspection item requiring speed. It also provides a test device that makes it feasible.

[0011]

In order to achieve this object, the test apparatus of the present invention comprises a pulse speed-up circuit composed of a monostable multivibrator or a buffer for a part of the pulse generated by the pulse generator. It is characterized by being equipped near the clock probe.

[0012]

With this configuration, since the pulse is supplied as a low-speed pulse to the vicinity of the clock probe, the path of the high-speed pulse generated via the pulse speed-up circuit can be very short, and the stray capacitance and inductance of the path are affected. It is possible to provide a good waveform to the clock input pin of the semiconductor integrated circuit. Then, the measurement time can be shortened while ensuring the reliability of the inspection.

Further, even in a relatively low-speed tester such as a board tester, by adding this configuration, it becomes possible to inspect the same as an LSI tester. For example, in a semiconductor integrated circuit designed for high frequency, It is possible to inspect frequency characteristics in a wide band, which was impossible to measure.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and FIG. 1 (a) is an explanatory view of a test apparatus according to an embodiment of the present invention. In the figure, 1 is a semiconductor integrated circuit, 2 is a circuit board under test, 3 is a probe holding plate, 4 is a data probe, 5 is a clock probe, 6 is a pulse generation circuit, and 7 is a pulse speed-up circuit.

The operation of the test apparatus configured as above will be described. First, the data pulse generated by the pulse generation circuit 6 is supplied to the circuit board under test 2 via the data probe 4 and given to the data input pin of the semiconductor integrated circuit 1. Similarly, the clock pulse generated by the pulse generation circuit 6 passes through the pulse speed-up circuit 7, is speeded up, and is then supplied to the circuit board 2 to be tested through the clock probe 5 to the clock input pin of the semiconductor integrated circuit 1. Given. FIG. 1B is a time chart showing the temporal change of each pulse at this time. In the figure, c2 is a clock pulse generated by the pulse generation circuit 6, c3 is a clock pulse that has passed through the pulse speed-up circuit 7, d2 is a data pulse generated by the pulse generation circuit 6, and t is a generation in the pulse generation circuit 6. This is the minimum pulse width possible. Although the clock pulse c3 has a pulse width smaller than the minimum pulse width, the speedup allows the data pulse 2 to be read by the semiconductor integrated circuit 1 even with the minimum pulse width t.

Here, the pulse speed-up circuit 7 will be briefly described. FIG. 2A is a circuit diagram of a pulse speed-up circuit used in the test apparatus of the embodiment of the present invention. In the figure, 8 is a buffer group, 9 is an inverter, and 10 is a NAND gate. In this circuit, the delay of the buffer group 8 is diverted to increase the pulse speed, and the process at that time is shown in the time chart of FIG.

As described above, according to this embodiment, since the pulse speed-up circuit is provided in the path of the clock pulse, the data pulse can be set to the minimum pulse width, and the test can be performed at high speed while maintaining reliability. It can be performed. Although the delay of the buffer is used in the pulse speed-up circuit in the embodiment, it has been confirmed that the same effect can be obtained by using the delay of the monostable multivibrator.

[0019]

As described above, the present invention has the following effects. (1) Since the clock signal is supplied to the vicinity of the probe with low-speed pulses, the high-speed pulse path is relatively short, and there is almost no distortion of the pulse generated by that path or electrical effects on other paths. A pulse with a good waveform can be supplied at high speed. As described above, the inspection required time can be shortened while ensuring the reliability of the inspection. (2) Even in relatively low speed equipment such as board tester, the same speed as LSI tester can be obtained, so it is possible to measure the frequency characteristics of semiconductor integrated circuits designed for high frequency, which could not be measured until now. Can also be inspected.

[Brief description of drawings]

FIG. 1A is an explanatory diagram of a test apparatus according to an embodiment of the present invention, and FIG. 1B is a test pulse time chart of a test apparatus according to an embodiment of the present invention.

FIG. 2A is a circuit diagram of a pulse speed-up circuit used in a test apparatus according to an embodiment of the present invention. FIG. 2B is a circuit diagram of a pulse speed-up circuit used in a test apparatus according to an embodiment of the present invention. Internal pulse time chart

FIG. 3A is an explanatory diagram of a conventional test apparatus. FIG. 3B is a test pulse time chart of the conventional test apparatus.

[Explanation of symbols]

 1 semiconductor integrated circuit 2 circuit board under test 3 probe holding plate 4 data probe 5 clock probe 6 pulse generation circuit 7 pulse speed-up circuit 8 buffer group 9 inverter 10 NAND gate

Claims (1)

[Claims] 1. A semiconductor test apparatus configured to supply a pulse to a circuit under test by a test pulse generation circuit for testing a circuit under test such as an integrated circuit and a board on which the integrated circuit is mounted. A semiconductor test apparatus characterized in that a part of the pulse generated by a pulse generation circuit is supplied to the circuit under test through a pulse speed-up circuit composed of a monostable multivibrator or a buffer.