JPH06225337A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To eliminate the adjacent track crosstalk of a reproduced color signal and make the frequency of a drum servo constant. CONSTITUTION:A reproduced color signal from which the crosstalk is eliminated is obtained by making the delay time of the delay circuit of a comb line filter 84 coincide with the horizontal cycle of a reproduced signal. By the memory 86 of a time base stabilizing means, a changed reproduced horizontal frequency is defined as a standard frequency. By making the reference signal of a drum servo 79 concide with the standard frequency of a television signal, the numbers of rotation of a drum motor at the time of a high speed reproduction and a normal reproduction are made constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording / reproducing apparatus incorporating a time axis correction circuit.

[0002]

2. Description of the Related Art Generally, a home-use VTR superimposes a luminance signal FM modulation and a low-frequency carrier on a magnetic tape to record and reproduce the magnetic tape. A time axis correction circuit (TBC) for stabilizing the time axis of the reproduced signal during normal reproduction, a noise reduction method when crossing a track during high speed reproduction, and a correction method such as a skew jump of the signal generated at that time are provided. Proposed.

For example, in JP-A-3-187068, TBC operation on / TBC operation off is controlled by a detection signal of special reproduction such as normal reproduction / high speed reproduction. Further, in this publication, the reference signal of the phase servo of the rotary drum is also controlled by this detection signal. Patent Publication Sho 62-146
098 and Japanese Patent Laid-Open No. 62-239683 show a method of correcting the time axis of the skew jump that occurs when the SP reproducing head pair and the EP reproducing head pair are used by switching during special reproduction. In addition, the patent publication Sho 64-6808
1 discloses a skew jump correction method using a field memory.

In the above-mentioned conventional example, although the high speed reproduction is possible, the speed ratio is limited as compared with the normal reproduction speed.

Problems in the case of obtaining high speed reproduction in the above conventional example will be described. FIG. 4 shows the configuration of the outline of the proposal in Japanese Patent Laid-Open No. 3-187068.

First, during normal reproduction, the luminance signal input (1) is converted into a digital signal by the analog-to-digital converter ADC (2), and the write / read clock is timed by the asynchronous memory buffer BUFFER (3). After the axis is stabilized and converted into an analog signal by the digital-analog converter DAC (4), the low-pass filter-LPF
The luminance signal output (6) is obtained through (5).

Further, a clock 1 (9) synchronized with the input signal is generated by a phase lock droop PLL (8) by a synchronizing signal separated from a luminance signal input (1) by a synchronizing separation circuit SYNC SEP (7). . At this clock 1 (9), the write reset signal RSTW (13) of the memory buffer BUFFER (3) and the memory
The clock WCK (12) of the buffer BUFFER (3) and the ADC (2) is generated. On the other hand, the fixed frequency oscillator (14) on the reading side generates the clock 2 (15) and supplies it to the reading control circuit (18), and the memory buffer BU
Read-out reset signal RSTR (1 of FFER (3)
6) and memory buffer BUFFER (3) and DA
The clock RCK (17) of C (4) is generated. At the same time, the clock 2 is divided by the frequency divider (19) into the drum servo (22).
Generates the reference signal ADV-V (20) of the drum motor.
Is controlled, that is, the rotational phase of the reproducing video head is controlled so that the signal phase of the reproducing luminance signal input (1) is within a certain range. As a result, the time axis can be stabilized during normal reproduction. Similarly, the reproduction color signal system also has an ADC, a memory buffer, and a DAC separately, but the description is omitted because the control is the same.

Next, at the time of recording, the changeover switch S in the figure
W1 and SW2 are switched, and the sync signal (24) of the recorded video signal is transferred to the vertical sync signal separation circuit VD SEP (25).
The vertical sync signal separated by is the reference phase of the drum servo, the ADC (2) and the memory buffer BUF.
The write clock WCK (12) of the FER (3) and the write reset RSTW (13) serve as the system of the clock 2 of the fixed frequency oscillator (14) on the read side, and the time axis correction operation is turned off.

During high speed reproduction, the clock changeover switch SW1 is set to the clock 2 (15) side to stop the operation of the time axis correction circuit TBC and the reference signal ADV-V (20) of the drum servo (22). Stop the output of. Drum motor (23) is drum servo (22)
Rotate within the standard. When changing from the high speed reproduction state to the normal reproduction state, the clock switch SW1 (1
0) is selected on the clock 1 (9) side, the TBC operation starts, and ADV-V (2) becomes the reference phase of the drum servo.
The initial phase of 0) is divided by the frequency divider (1
9) is controlled and output. As a result, the TBC operation is improved by shortening the transient time.

However, the rotation speed of the drum motor in the high speed reproduction state is different from the rotation speed of the normal reproduction, the response of the motor is slower than the response of the circuit system, and the speed ratio is large. The above-mentioned improvement is insufficient for the transient time from the normal regeneration state to the normal regeneration state. Therefore, when the drum motor is rotated at the same frequency as during normal playback even during high-speed playback, there is no need to stop the drum servo reference signal ADV-V (20) shown above, and the phase is also controlled. The transient state of time disappears.

However, the reason why the number of rotations of the drum motor cannot be set to the number of rotations during normal reproduction during high speed reproduction will be described below.

As disclosed in Japanese Patent Laid-Open No. 64-68081, at the time of high speed reproduction, the reproducing head traces diagonally across the tape track at the time of recording. At this time, the reproduction vertical synchronizing signal frequency and the reproducing horizontal synchronizing signal frequency differ from those of the standard ones. These frequency relational expressions are as follows: fH = (525 / 2− (m−1) × AlphH) × fV (1) Here, fH: horizontal horizontal sync frequency 525/2: horizontal / vertical frequency ratio in standard m: double speed playback normal playback m = 1 tape feed stopped m = 0 tape feed forward direction m> 0 Integer of tape feed backward direction Integer of m <0 AlphaH: H adjustment between adjacent tracks fV: Playback vertical sync signal frequency (drum motor)
Is equal to the number of rotations).

As is clear from the above equation, high-speed reproduction is carried out with a constant fV, that is, the drum motor rotation speed (m =
9-11) and fH differ from the standard. Playback signal T
Although it depends on the performance of the V monitor, the screen is disturbed on the TV monitor outside the pull-in frequency range of the horizontal scanning of the TV. On the contrary, if fH is kept constant, fV must be changed, but this also needs to be kept within the pull-in frequency range of vertical scanning of the TV monitor, which causes a restriction on the double speed number of high-speed reproduction.

Another reason why the rotation number of the drum motor at the time of high speed reproduction cannot be set to the rotation number at the time of normal reproduction is to remove the color crosstalk signal from the adjacent track of the reproduction color signal. Regarding this, the patent publication Sho 62-14609
8 will be described as a conventional example. FIG. 5 is a schematic diagram of a conventional example in which reproduction luminance signal processing and reproduction color signal processing are all digitized. The luminance FM modulated wave from the reproducing head (not shown) and the superimposed signal RF-IN (30) of the low frequency conversion color signal are
After being converted to a digital value by the analog-digital converter ADC (31), the luminance signal system is a high-pass filter-H.
After passing through the PF (32), the FM demodulation circuit FM-DEM (33), the de-emphasis DE-EMPH (34), the time axis correction circuit TBC (35) and the adder (36), the digital-analog converter DAC (37). At output end OUP (52)
Is output to. On the other hand, the low-pass converted color signal is converted into a low-pass filter-LPF (40) and a frequency converter CONV (4
1), band pass filter-BPF (42), comb filter-COMB (43), time axis correction circuit TBC (4
4), the frequency converter CONV (45), the adder (3
6), output to the output terminal OUT (52) via the digital-analog converter DAC (37). De-emphasis D
Synchronous separation circuit (38) from the output of E-EMPH (34)
Then, the horizontal synchronizing signal is obtained and the address control circuit of the TBC (35) (44) is reset to correct the skew distortion during high speed reproduction. Although not specifically shown in the text of the publication, the clock nfH (39) added to the ADC (31) and the DAC (37) is a stable clock such as a crystal oscillator. This is because the color stability of the TV monitor cannot be obtained unless the output color carrier signal is stable. ADC (31), TBC (35) (44),
CONV (45), VCO (47) and DAC (3
Except for 7), this is the same as the block configuration of analog signal processing. In the case of analog signal processing, APC (4
As the reference signal of 9), a frequency signal that is stable in a crystal oscillator is used. In the digital case, the clock driving the digital circuit can be the reference signal. The crosstalk removal filter-COMB (43) delay circuit uses a glass delay line or CCD delay line for 1H (1 horizontal period) delay in an analog circuit, and uses a 1H memory in a digital circuit.
The 1H uncorrelated component is removed from each.

Here, this filter--COMB (43)
Since the delay time of the delay circuit is constant, if the reproduction horizontal frequency changes from the reference frequency during high-speed reproduction, the crosstalk component of the non-correlation component cannot be removed.
Expressed in a simple equation, the carrier color signal frequency C, crossed-
The carrier color signal D is C1 = 1 × fH ± k × fH (2) D1 = (1 + 0.5) × fH ± (k + 0.5) × fH (3) High speed reproduction C2 = 1 × fH ± k × (fH + ΔfH) (4) D2 = (1 + 0.5) × fH ± (k + 0.5) × (fH + ΔfH) (5) 1: (227.5 in NTSC system) k: 1 to positive integer fH: standard Horizontal frequency ΔfH: It becomes a fluctuating frequency during high-speed reproduction. The first term on the right side of the equations (2) to (5) represents the carrier wave, and the second term represents the base band component. Since the 1H delay time is a constant 1 / fH, the first term and the second term of D1,
The first term of D2 can be removed, but the second term of D2 cannot be removed. The second term of C2, which is the signal desired by the filter, is deviated from the center of the filter and is attenuated.

[0016]

As described above, in the prior art, in order to remove the adjacent track crosstalk in the reproduced color signal, and due to the limitation of the pull-in range of the horizontal scanning circuit and the vertical scanning circuit of the TV monitor. Horizontal frequency of playback signal,
The vertical frequency cannot be changed significantly, that is, there is a restriction on the double speed number during high-speed reproduction.

An object of the present invention is to eliminate the restriction of the double speed number of high speed reproduction, which is seen in the conventional example, to enable ultra high speed reproduction, and to prevent the excessive state from ultra high speed reproduction to normal reproduction. It is to reduce the time and improve the response of state switching.

[0018]

A means for generating a first clock phase-synchronized with a horizontal synchronizing signal obtained by synchronously separating a reproduced luminance signal and a second clock for oscillating a stable frequency are generated. Means for adjusting the delay time of the delay circuit of the crosstalk component removal filter from the adjacent track during reproduction color signal processing to the time of the reproduction signal using the first clock; and the second clock. Frequency dividing means for generating a vertical synchronizing signal having a standard frequency of a television signal, and means for stabilizing a drum rotating phase by using the vertical synchronizing signal as a reference signal of a drum servo for controlling a rotating phase of a video head. Means for digitizing the reproduction luminance signal and the reproduction color signal by using the first clock; and a memo of the digitized reproduction luminance signal and the reproduction color signal. Means for writing by using the first clock to read the memory using the second clock, composed of a means for stabilizing the time axis.

[0019]

Since the delay time of the delay circuit of the crosstalk component removal filter is matched with the time of the reproduction signal, it is possible to remove the adjacent track crosstalk. Further, the changed reproduction horizontal frequency becomes the standard frequency by the time axis stabilizing means. The reference signal of the drum servo is adjusted to the standard frequency of the television signal, and there is no change in the rotation speed of the drum motor from high speed playback to normal playback, and the response is good.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an overall view of an embodiment of the present invention (only a reproducing system for explanation). Playback video head (not shown)
From the reproduction signal RF-IN (60) from, the high-pass filter-HPF (61) extracts only the luminance FM modulation component, and then the luminance is demodulated by the FM demodulation circuit FMDEM (62) and de-emphasis DE-EMPH (63). It is made into a signal and is stored in the memory (6
Generate a digital Y input signal (65) to 6). The digital Y signal (67) from the memory (66) is converted into an analog luminance signal by the digital-analog converter DAC (68), and then the composite sync SYNC (95).
Is output to the Y signal output terminal (71) through the switcher (69) for embedding time window switching of the window WINDOW (96) and the low pass filter LPF (70).

The reproduction signal RF-IN (60) is again low.
The low-pass conversion color signal (including the crosstalk component, the carrier wave is 40 × fH) is taken out by the pass filter-LPH (81) and converted into a digital amount by the analog-digital converter ADC (82). The color carrier frequency is set to 455/2 × fH and (455/2 +) by the digital AM modulator (83).
80) × fH, and then a bandpass filter
・ Comb filter-BPF / COMB filter- (8
In 4), the crosstalk-removed color signal having the color carrier frequency of 455/2 × fH is obtained. This carrier frequency is demodulated by the color demodulation circuit (85) and the digital memory (8
Input to 6). Time-stabilized memory (8
The output of 6) is output to the blanking window (98) section and the bar in the switch and AM modulation circuit 87.
It is embedded in the section of the stray signal BGR (97) and then AM-modulated. Digital-to-analog conversion DAC
It is converted to an analog quantity at (88) and output to the color signal output end (90) via the LPF (89).

The base band signal of the color demodulation circuit (85) is the phase detection of the burst and the loop filter PD.
Generate 40 × fH sine and cosine waves in the digital VCO (92) through the LPF (91). Also 910f
H clock 1/4 frequency divider (94) and AM modulator (9
At 3), the idler frequency (4
55/2 + 80) × fH. To return the phase shift when the phase shift is applied to the video head, this 4
The frequency divider (94) is controlled, but the description is omitted. Even if the time of one horizontal signal changes due to this color signal processing, a bandpass filter-comb filter-BPF-
Since the delay time of the delay circuit of the COMB filter (84) becomes one horizontal time of the reproduction signal, the crosstalk from the adjacent track is removed.

With the memory (66) and the memory (86) as a boundary, the left input side of the figure is a write clock system of 910 × fH phase-clocked to the reproduction horizontal synchronizing signal, and the right output side of the figure is a fixed frequency of 4 × fsc. (1 in the NTSC system
It is a reading clock system of 4.3 MHz). Next, the clock generation and memory control will be described.

Analog-to-digital converter ADC (64)
The output (65) is separated from the horizontal sync in the write control circuit (73), and the clock of the horizontal sync phase lock loop 910fH and the write horizontal window WIND which will be described later.
OW is generated. Further, the vertical synchronization is separated, and the write vertical window WINDOW is generated. On the reading side, a crystal oscillator XO of fixed frequency transmission and a frequency divider (76) provide 4 fsc.
Generates a clock (77) for the read control circuit (7
5), the composite sync signal SYNC (95),
Read horizontal / vertical windows WINDOW (96) (98), burst gate signal BGR (97), drum motor (8)
0) Reference signal ADV-V to the drum servo (79)
(78) is generated.

The widths of the write vertical window WINDOW and the read window WINDOW change according to data from the system control described below. As is clear from the above equation (1), during tape feed reverse reproduction, the horizontal frequency of the reproduction signal increases and the number of horizontal lines is the standard 52.
Since it is more than 5/2, the writing window WINDOW
Reduce W time. Since the horizontal frequency of the reproduction signal becomes smaller and the number of horizontal lines becomes smaller than the standard 525/2 during high speed reproduction in the tape feed forward direction,
Reduce the reading window WINDOW time.

The envelope detection circuit (72) in FIG.
Is a circuit that operates during special playback such as high-speed playback, and is a signal that can distinguish when the signal is played back (when there is a playback signal) and when the video head straddles the video track (when there is no playback signal). Is output. Patent Publication Sho 64-680
As described in 81, since a skew jump occurs when the video head crosses the video track, it is used for stopping the memory writing and changing the comparison phase of the horizontal phase lock droop PLL. .

FIG. 2 is a circuit block diagram of the memory write / read control unit of this embodiment. Only the luminance signal is described in the memory section, but the memory of the color signal section is also controlled in the same manner, so the description is omitted. A commercially available TMS4C1070 manufactured by Texas Instruments, Inc. was used, but the memory is not limited to this. The same name (number) is added to the same thing as FIG.

The digital luminance signal input (65) is input to the input D-IN of the memory (66) and also to the sync separation circuit SYNC SEPA (101), and the horizontal sync signal H (102) and the vertical sync signal are input. V (103) is separated. The horizontal synchronizing signal H (102) is supplied to the phase detector (10
In 4), the phase comparison error with the feedback signal HREF (105) is calculated. The error is loop filter-LOOP
After being integrated by FILTER (106), digital V
The CO (107) generates a signal phase-locked to the horizontal synchronizing frequency at a frequency of 1820 × fH. The output is converted into an analog signal by the digital-analog converter DAC (108). This VCO (107) and DAC (10
8) fixed frequency 12 fsc from crystal oscillator (76)
Operating at (42.95MHz) (123), 1820 × f
Since the analog signal of H becomes a beat component (folding component), a necessary component is taken out by the analog band pass filter-BPF (109). After that, slicer (110)
Convert to rectangular wave with and divide by 1/2 divider (111) to 910fH
Get the clock (74). This 910fH clock is used for horizontal counter-decoder H-COUNTER-DEC
The ODER (112) basically divides the frequency by 910 to generate the feedback signal HREF (105). In addition, the writing horizontal window HWW (114) and the vertical counter / decoder
2 to V-COUNTER / DECODER (115)
The fH clock (113) is generated. Vertical counter
Decoder V-COUNTER / DECODER (11
In 5), the basic operation is frequency division by 525, and the write vertical window VWW (116) is generated. Pulse generator (117)
Takes the logic of the horizontal window and the vertical window, gates the 910fH clock, and writes the clock WCK of the memory (66).
(119) and write reset RSTW (120) are generated.

To restate, the digital luminance signal input (65) input to the sync separation circuit (101) is separated into a horizontal sync signal H (102) and a vertical sync signal V (103). The horizontal counter / decoder (112) basically divides the first clock 910fH by 910 to generate a feedback signal HREF (105). Further, it generates a 2fH clock (113) to the writing horizontal window HWW (114) and the vertical counter / decoder (115). The basic operation of the vertical counter / decoder (115) is frequency division by 525, it is reset by the vertical synchronizing signal V (103), and the count value is decoded to generate the write vertical window VWW (116). To do. Pulse generator (117)
Takes the logic of the horizontal window and the vertical window to generate the first window on the writing side, and gates the 910 fH clock to the memory (6
6) Write clock WCK (119) and write reset RSTW (120) are generated. During high speed playback,
The control data from the system control (100) is received, the division ratio of the write vertical counter / decoder (115) is changed, and the position of the write vertical window VWW (116) from the reproduction vertical synchronizing signal is received. And change the window size.

The operation of the memory (66) will be briefly described. The writing of the digital signal from the digital input port D-IN to the internal memory cell is controlled by the input enable IE terminal. The write clock increments the internal write address counter one by one, and the increment on / off is controlled by the write enable WE. The control of the internal read address counter is similar, and their control terminals are read reset RS.
TR, read clock RCK, read enable R
E, output enable OE.

Next, the read control circuit (75) will be described. Crystal oscillator XO (124) and 1/3 frequency divider (125)
The 4 × fsc (14.318 MHz) read clock (77) is generated at. This read clock is used as a horizontal counter-decoder H-COUNTER DECO
The DER (126) and the logic circuit (135) divide the frequency by 910 and read out the burst gate pulse BGR (97),
Read horizontal window HWR (127), composite sync COMP SYNC (95) horizontal signal, read vertical counter-decoder V-COUNTER DECO
Generates a clock 2fH (128) to DER (129). Read-out vertical counter-decoder V-COU
The NTER / DECODER (129) and the logic circuit (135) divide the 2fH clock (128) by 525 to generate the composite sync COMPSYNC (95).
Vertical signal, reading window WINDOW (96) (9
8) and reading vertical window VWR (130), drum server
A reference signal ADV-V (78) for the frame is generated. Read reset RSTR which is a control pulse for memory read
(132), the read clock RCK (133) is read horizontal window HWR (127) and read vertical window VWR.
(130), receiving the read clock (77), the pulse generator (131) generates it.

To restate, the crystal oscillator (124) and the frequency divider (125) generate a 4 × fsc (14.318 MHz) read clock (77). This read clock is divided by a horizontal counter / decoder (126) and a logic circuit (135) by 910 and read out burst gate
Pulse BGR (97), read horizontal window HWR (12
7), the horizontal signal of the composite sync (95) and the clock 2fH (128) to the read vertical counter / decoder (129) are generated. Vertical counter for reading
-The decoder (129) uses this 2fH (128) for 52
The frequency is divided by 5, and the vertical signal of the composite sync (95), the reading windows (96) (98) and the reading vertical window V
Reference signal ADV-V for WR (130) and drum servo
(78) is generated. Horizontal window for reading HWR (127)
Read-out vertical window VWR (130) and read-out clock (77) are received, the pulse generator (131) takes those logics, a 2nd read-out window is generated, and a memory read-out control pulse. Read-out reset RSTR (1
32), the read clock RCK (133) is generated. During high-speed playback, system control allows vertical counter
Window change data (13) sent to the decoder (129)
4) is changed to change the position and width of the second reading window.

The control data from the system control (100) includes an offset value (121) for changing the oscillation frequency of the digital oscillator VCO (107), a frequency division value of the write vertical counter (115) and a write vertical window. VWW (11
Writing window change value (12) for changing the position and width of 6)
2), and the position of the vertical window VWR (130) that was read out.
There is a read window change value (134) for changing the width. The offset value (121) is to prevent mislocking and to reduce the phase error because the phase lock frequency greatly changes.

The frequency relational expression between the reproduction vertical synchronizing signal frequency and the reproduction horizontal synchronizing signal frequency is, as described above, M = (m-1) * AlphHfH = (525 / 2-M) * fV. Here, M is the number of increases (decreases) in the number of horizontal lines in one field. Apply the actual number.

AlphaH = 1.5 SP mode = 0.75 LP mode = 0.5 EP mode, but here. The SP mode will be described as an example. Since the LP and EP modes can be calculated in the same manner, they are omitted.

Normal reproduction with fV = 59.94 Hz m = 1, M = 0.0, fH =
15.734 Hz reverse direction high speed reproduction m = -20, M = -31.5, fH =
17.622 Hz forward direction high speed reproduction m = 20, M = 28.5, fH =
It becomes 14.25 Hz.

In the 20 × backward high speed reproduction, the number of reproduction horizontal lines is increased by 31.5 in one field period and becomes 294.
It will be a book. Therefore, at this time, the digital VCO in FIG.
Change the offset value (121) of (107) to 1
From the oscillation frequency of 5.734 × 1820 (28.636MHz) to 17.622 × 1820 (32.072MH)
z) to oscillate. At the same time, the division ratio of the write vertical counter / decoder (115) is changed from 525 to 58.
8, and the position of the write vertical window VWW (116) from the reproduction vertical sync signal is changed. The size of this window is the same as the number of 240 horizontal lines during normal reproduction.

In the 20 × normal direction high speed reproduction, the number of reproduction horizontal lines is reduced by 28.5 lines in one field period to 234.
It will be a book. Therefore, at this time, the digital VCO in FIG.
Change the offset value (121) of (107) to 1
From the oscillation frequency of 5.734 x 1820 (28.636 MHz) to 14.25 x 1820 (25.525 MH)
z) to oscillate. At the same time, the division ratio of the write vertical counter / decoder (115) is changed from 525 to 46.
8, and the position of the write vertical window VWW (116) for the reproduction vertical sync signal is changed. Further, the window size is changed from the 240 horizontal lines during normal reproduction to 211 lines. In this case, read out vertical window VWR (130)
Vertical counter-decoder (1
29) Change the window change data (134) sent to 29).

FIG. 3 shows the changing state of the window WINDOW. The left side shows the horizontal / vertical windows on the writing side, and the right side shows the horizontal / vertical windows on the reading side. 1 horizontal window
There are 728 pixels per line, which is constant regardless of the speed factor. 1 field 262.5 during normal playback of (a)
Of the horizontal lines, 240 horizontal lines are written to memory,
Also 240 horizontal lines are called. During reverse high speed playback of (b), 24 out of 294 horizontal lines in one field
Zero horizontal lines are written to memory and 240 horizontal lines are also recalled. 1 during high-speed playback in the forward direction of (c)
Of the 234 horizontal lines in the field, 211 horizontal lines are written to the memory and the 211 horizontal lines are also called. Since the number is less than 240 lines during normal reproduction, the read vertical window VWR (130) is reduced and the remaining 51.5 lines are processed as blanking.

An outline of the means for generating the first window will be described. A first counter for dividing a first clock initialized by a vertical synchronizing signal separated from a luminance signal to be written into a memory; It is composed of a variable comparator data and a first comparator / logic circuit for the count value. By changing the value of the variable comparator data, the number of horizontal signals in the separated vertical synchronizing signal section can be changed. The width of the first window and the time from the separated vertical synchronizing signal to the first window can be changed proportionally. The outline of the means for generating the second window will be described. A second counter that divides the second clock and a second comparator / logic circuit for variable comparison data and a count value. , This second counter-decor the value
And a circuit for generating a vertical synchronizing signal of the standard frequency by changing the value of the variable comparison data to obtain the width of the second window and the vertical synchronizing signal of the standard frequency from the vertical synchronizing signal. The time with the second window can be changed.

In this embodiment, a digital memory is used as the 1H delay line of the delay circuit of the color crosstalk removing filter (84), but a CCD delay line whose delay time can be changed may be used.

In the present embodiment, the second clock is frequency-divided to generate a composite sync, and the second clock is generated.
Although the video signal from the memory or the composite sync is switched in the window of, the synchronization signal portion may be written in the memory and the synchronization portion may be read out by changing the first window, which is not limited to the embodiment. Not something.

[0043]

As described above, according to the present invention, the color crosstalk component from the adjacent track can be removed even if the reproduction horizontal frequency is deviated from the standard frequency during high speed reproduction.
Moreover, since the video head drum can be rotated at the standard number of revolutions, the transient response from the high-speed reproduction to the normal reproduction or the opposite from the normal reproduction to the high-speed reproduction is good, which is very effective in industry.

[Brief description of drawings]

FIG. 1 is a block diagram which constitutes an embodiment of the present invention.

FIG. 2 is a block diagram of an internal memory write / read controller according to an embodiment of the present invention.

FIG. 3 is a diagram showing operations of the memory during normal reproduction and high-speed reproduction according to the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional example.

FIG. 5 is a block diagram showing a conventional configuration.

[Explanation of symbols]

61 ... High-pass filter (HPF) 62 ... FM demodulation circuit (FM DEM) 63 ... De-emphasis (DE-EMPH) 64 ... Analog-digital converter (ADC) 66 ... Memory 68 ... Digital-analog converter (ADC) 69 Switcher 70 Low pass filter (LPF) 72 Envelope detection circuit 73 Write control circuit 75 Read control circuit 76 Horizontal oscillator and frequency divider 79 Drum servo 80 Drum motor 81 ... Low-pass filter (LPF) 82 ... Analog-digital converter (ADC) 83 ... Digital AM modulator 84 ... Band pass filter-comb filter (BP)
F / COMB filter-) 85 ... Color demodulation circuit 86 ... Memory 87 ... Switch and AM modulation circuit 88 ... Digital-analog converter 89 ... Low-pass filter 91 ... Phase detection and loop filter- (PD / LPF) 92 ... VCO 93 ... AM modulator 94 ... 1/4 frequency divider.

Claims (3)

[Claims] 1. A means for generating a first clock phase-synchronized with a horizontal synchronizing signal obtained by synchronously separating a reproduction luminance signal, a means for generating a second clock oscillating a stable frequency, and a reproducing means. Means for adjusting the delay time of the delay circuit of the crosstalk component removal filter from the adjacent track during color signal processing to the time of the reproduced signal using the first clock; and dividing the second clock. Means for generating a vertical synchronizing signal having a standard frequency; means for stabilizing the drum rotational phase by using the vertical synchronizing signal as a reference signal of a drum servo that controls the rotational phase of the video head; Means for digitizing a reproduced color signal by using the first clock, and writing the digitized reproduced luminance signal and reproduced color signal in a memory by using the first clock. A magnetic recording / reproducing apparatus comprising: means, and means for reading the memory using the second clock to stabilize the time axis. 2. A means for generating a first window for selecting i horizontal signals from among n horizontal lines of the reproduction signal by dividing the first clock and adjusting the phase of the reproduction signal. Means for generating a second window for selecting j horizontal signals from among m lines of horizontal signals of a standard video signal by dividing the second clock; k field signal (k
Has a capacity for storing 1, 2, ..., Positive integers), means for writing the reproduction luminance signal and the reproduction color signal selected by the first window into the memory, and the means selected by the second window. The magnetic recording / reproducing apparatus according to claim 1, further comprising means for reading the reproduction luminance signal and the reproduction color signal from the memory. 3. The magnetic recording / reproducing apparatus according to claim 1, further comprising means for reproducing the magnetic tape by changing it from a speed of normal reproduction, and performing special reproduction such as high speed reproduction.