JPH06224404A - Manufacture of integrated circuit device - Google Patents

Abstract

PURPOSE:To manufacture an integrated circuit device excellent in element property by bonding element structure consisting of an InP or the like directly onto a semiconductor single crystal substrate different in lattice constant of Si or the like. CONSTITUTION:An integrated circuit device is manufactured by forming elements 2-5 made of Si materials on a single-crystal silicone substrate 1, and forming laminar structures 7-9 required for the elements on the etch stop layer 6 of a single-crystal InP substrate 5, and bringing it into contact with the top of the Si substrate 1, its substrate 5 and all, and bonding them directly by heat treatment, and then, removing the InP substrate 5. Hereby, an integrated circuit device can be gotten without deteropratomg the element property, together with the Si element and the InP element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an integrated circuit device in which a plurality of elements composed of semiconductor single crystals having different lattice constants are integrated on one semiconductor single crystal. . Certain types of optoelectronic integrated circuit devices and certain types of high-speed highly integrated circuit devices include, for example, Si elements, GaAs elements, InP on a Si single crystal substrate.
It is configured by integrating elements such as elements made of single crystals having different lattice constants.

[0002]

2. Description of the Related Art An example of a method of manufacturing an integrated circuit device of this type is disclosed in the following document. Reference: Paper title; "Selected area heteroepitaxial growt
h of GaAs on Silicon for advanced device structure
s ", author; RJ Matri and H. Shichijo, reference; Thin Sol
id Films, Vol.181 (1989) p.2 13-p.2 2 5 Publisher: Els
evier Seguoia S.A. (Switzerland) In this document, Si with a Si element formed on the surface is used.
A single crystal substrate is prepared, a trench is formed on the surface where no element is formed, and GaAs is crystal-grown at the same surface position as the surface of the Si single crystal substrate in the trench, and the GaAs single crystal is formed. On the surface of the part
An element is formed and then electrodes are formed.

[0003]

However, in the manufacturing method utilizing the hetero-crystal growth as described above, in order to grow high-quality GaAs or InP on the Si single crystal substrate, the Si substrate has a low temperature of 600 ° C. Above, 1 if high
There is a problem in that the device must be exposed to a high temperature atmosphere near 000 ° C., and therefore the device already built on the Si substrate deteriorates. In addition, GaAs and I
When crystal-growing nP, the device already built on the Si substrate must be covered with the protective film, and the polycrystalline layer deposited on it must be removed later. There was a problem that the process became complicated. The present invention eliminates the above-mentioned problems by using S
To provide a manufacturing method using a technique of directly adhering materials having different lattice constants such as i, GaAs, and Inp, which has good crystallinity at a relatively low temperature and enables an integrated device to be manufactured by a simple process. With the goal.

[0004]

In the manufacturing method of the present invention, a structure of a plurality of electric or optical elements of the first semiconductor single crystal is formed on the surface of the first semiconductor single crystal substrate, and at least a predetermined surface area is formed. Then, a first substrate body in which the first semiconductor single crystal is exposed is prepared. Further, an etch stop layer of a semiconductor crystal lattice-matched with the second semiconductor single crystal is formed on the entire surface of the second semiconductor single crystal substrate, and the second semiconductor single crystal is lattice-matched on the etch stop layer. A second substrate body in which a layer structure of a plurality of electric or optical elements of a second semiconductor single crystal system consisting of semiconductor crystals is formed with the top surfaces of these elements aligned, and the single crystals are exposed at those top surfaces. To prepare. Then, by surface treatment, a hydroxyl group (OH group) is bonded to the single crystal exposed surface of the first substrate body and the single crystal exposed top surface of the second substrate body. Then, low temperature heat treatment is performed in a state where the exposed surface of the first semiconductor single crystal and the top surface of the second semiconductor single crystal are in contact with each other. Then, the second semiconductor single crystal substrate is removed by etching using the etch stop layer as an etching stopper, and the etch stop layer is removed by ultrasonic vibration. After that, the surface is covered with an insulating layer such as a polyimide, and an electrode is appropriately formed.

[0005]

The surface treatment of the single crystal exposed surface of the first substrate body and the second substrate body can be performed with a sulfuric acid-based solution. Si, GaA
Most single crystal materials such as s and InP are washed with a sulfuric acid-based etchant, so that OH groups are bonded on the exposed surface of the single crystal and the top surface of the layer structure. The heat treatment process bonds the first substrate body and the second substrate body. The heat treatment is performed at a low temperature that does not deteriorate the element characteristics of the first substrate body and the second substrate body. Typically, heat treatment is performed at 450 ° C. By heat treatment at 450 ° C for about 30 minutes,
Bonding is performed with sufficient strength to withstand substrate polishing or dicing. In the bonding by heat treatment at 450 ° C., the lattice images of the constituent atoms are clearly observed near the bonding interface, the interface between the first single crystal and the second single crystal system is steep, and the bonding action is mainly It can be assumed that it is based on the dehydration condensation reaction of the OH group on the exposed surface of the crystal. It is considered that when the heat treatment is increased, the adhesive strength itself increases, and the recrystallization at the adhesive interface has an effect on the adhesive action. After the bonding, the second semiconductor single crystal substrate is removed by etching to leave only a thin etch stop layer, and the etch stop layer is removed by ultrasonic vibration. Since ultrasonic vibration is adopted in this step, it is possible to avoid the deterioration of the element characteristics and the exposed surface of the single crystal, which is caused by the etching solution.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a method of manufacturing an integrated circuit device according to the present invention will be described with reference to FIG. Here, a case is shown in which a transistor made of Si and a light emitting / receiving element structure made of InP are integrated. First, as shown in FIG. 1A, a source 2, a gate 3 and a drain 4 are formed on a silicon substrate 1 by a normal process to form a transistor. Here, the case of a MOS type transistor is shown as a typical example. At this time, InP
It is preferable to form a recess 1a in a portion where a device is to be provided, because alignment is easy later and a surface step after integration can be reduced. However, it may be omitted because the number of steps for forming the recess is increased.

On the other hand, in addition to the silicon substrate 1, FIG.
As shown in (B), an InP substrate 5 is prepared, and an InGaAs etch stop layer 6 (thickness: about 0.1 μm) and a p-InP clad layer 7 (thickness: about 1. 5 μm), InGaAsP active layer 8
(Thickness of about 0.15 μm) and n-InP clad layer 9 (thickness of about 1.5 μm) are sequentially grown. After this crystal growth step, an etching mask such as a SiO2 film is formed by a normal CVD method (Chemical Vapor Depositiong) and a photolithography method, and further, an RIE method (Reactive method).
Ion Etching) is used to remove layers 7 to 9 while leaving the element portion, and then the SIO2 film is removed with hydrofluoric acid to remove the InGaAs etch stop layer as shown in FIG. 1 (C). 6 on top of p-InP
Cladding layer 7, InGaAsP active layer 8, and n-In
An InP light receiving and emitting device structure including the P clad layer 9 is formed. The one produced in this way is
Using a mixture of O4: H2O2: H2O = 3: 1: 1,
After cleaning the surface for 30 seconds, soak it in hydrofluoric acid for 1 minute,
Then wash with water. By doing so, the clean top surface of the n-InP clad layer 9 is exposed, and the top surface is bonded with OH groups. The chemical formula numbers of the mixed solution should be indicated by subscript half-widths, but for convenience, they are shown by simple half-widths.

On the other hand, the surface of the silicon substrate on which the element is built, as shown in FIG. 1 (A), is similarly converted into H2SO4: H2O2:
It is washed for 30 seconds using a mixed solution of H2 O = 3: 1: 1 and then washed with water. By doing so, the silicon substrate 1
In the concave portion 1a, the clean noodles are exposed, and the exposed surface has OH groups bonded. Next these 2
Two kinds of wafers are spin-dried, respectively, and immediately thereafter, the both are aligned and brought into contact with each other as shown in FIG. At this time, when these wafers are surface-treated with H2SO4: H2O2: H2O, the OH groups absorbed on the surface form hydrogen bonds, so the strength of the wafers is weak even if they are contacted at room temperature, but Adhere to the extent that the position does not shift even if the is moved.

Next, this wafer is placed in an annealing furnace, a weight of about 30 g / cm 2 is placed, and a heat treatment is carried out at a low temperature of about 450 ° C. for about 30 minutes in a hydrogen atmosphere. By this heat treatment, H2 O is removed from the hydrogen-bonded OH groups, so-called dehydration condensation reaction occurs, and the adhesive strength becomes sufficiently strong. After that, as shown in FIG. 2B, the end of the wafer is covered with wax 10 so that the etching liquid does not penetrate between the bonded wafers, and then the InP substrate 5 is covered with B.
Etch with r-CH3 OH and then with HCl. HCl etches InP, but InGa
Since the As etch stop layer 6 is a selective etchant that is not etched, it stops automatically when the etching reaches the InGaAs etch stop layer 6. After removing the wax 10 with an organic solvent, the thin InGaAs etch stop layer 6 is cleaved and removed by ultrasonic vibration as shown in FIG. Next, FIG. 3 (B)
As shown in FIG. 3, after applying polyimide 12 or the like to the surface of the wafer and flattening it, an electrode 13 is formed by photolithography and etching as shown in FIG. Ends.

In the above embodiment, the p-InP clad layer 7 and InGaA are used as the layer structure of the element of the second substrate body.
3 composed of sP active layer 8 and n-InP clad layer 9
Although a layered structure was used, an n-InP clad layer, In
A three-layer structure composed of a GaAsP active layer and a p-InP clad layer can be formed, and a cap layer or the like can be added to form a further multi-layered structure, and lattice matching with the single crystal of the second substrate body is possible. Other compositions can also be used, provided that they do. Further, in the above-mentioned embodiment, the single crystal exposed surface portion (recess 1a) of the silicon substrate is non-doped, but it is also possible to form an island region having a high impurity concentration to reduce ohmic resistance. Other single crystal substrates such as GaAs may be used.

[0011]

As described above in detail, according to the present invention, the layer structure necessary for forming the light emitting / receiving element structure is preliminarily crystal-grown on the InP substrate and the like, and the layer structure is grown on the Si substrate. Since the integrated circuit device is formed by directly bonding it by heat treatment, the device prefabricated on the Si substrate does not deteriorate at high temperature, and the lattice defects caused by the difference in lattice constant Is effectively confined only to the interface directly bonded, so that an integrated device can be formed without impairing good crystallinity. Further, since the element is formed by using direct adhesion, selective etching, and cleavage of the thin film by ultrasonic vibration, there is no possibility of deteriorating the device built on the Si substrate.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of a method for manufacturing an integrated circuit device of the present invention.

FIG. 2 is an explanatory diagram of an embodiment of a method for manufacturing an integrated circuit device of the present invention.

FIG. 3 is an explanatory view of an embodiment of a method for manufacturing an integrated circuit device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 1a Recess 2 Source 3 Gate 4 Drain 5 InP substrate 6 InGaAs etch stop layer 7 p-InP clad layer 8 InGaAsP active layer 9 n-InP clad layer 10 InP light emitting / receiving device structure

Claims (1)

[Claims] 1. A structure of a plurality of electric or optical elements of the first semiconductor single crystal is formed on a surface portion of the first semiconductor single crystal substrate, and the first semiconductor single crystal is exposed at least in a predetermined surface region. A step of preparing the first substrate body, and an etch stop layer of a semiconductor crystal lattice-matched with the second semiconductor single crystal are formed on the entire surface of the second semiconductor single crystal substrate, and a first crystal is formed on the etch stop layer. A layer structure of a plurality of electric or optical elements of the second semiconductor single crystal system, which is composed of a semiconductor crystal lattice-matched with the two semiconductor single crystals, is formed with the top surfaces of the elements aligned, and the single crystals are formed on the top surfaces. A second substrate body in which the exposed surface of the second substrate body is exposed, a step of bonding a hydroxyl group to the single crystal exposed surface of the first substrate body by a surface treatment, and the single crystal exposed top of the second substrate body by a surface treatment. Hydroxyl groups on the surface A step of bonding, a step of performing a low temperature heat treatment in a state where the exposed surface of the first semiconductor single crystal and the top surface of the second semiconductor single crystal are in contact with each other, and thereafter, the etching stop layer is used as an etching stopper. 2. A method of manufacturing an integrated circuit device, comprising the steps of: etching away a semiconductor single crystal substrate, and further removing the etch stop layer by ultrasonic vibration.