JPH10256169A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the through-dislocation in a film, flatten the surface and perfectly relax the lattice by forming and heat-treating an Si or SiGe mixed crystal cover layer on the top of an epitaxially grown Ge laminar film on an Si substrate. SOLUTION: An Si or SiGe mixed crystal cover layer 11 is formed on the surface of an epitaxially grown Ge laminar film 13 on an Si substrate 12 and heat-treated to form edge-like dislocations (Burger spectrum representing the slip and direction of the dislocation is perpendicular to the dislocation line) with grown-in defects 14 existing at the interface of the substrate 12 and film 13 as nuclei, where they are localized at the interface and arranged like a cross hatch at spacings enough to perfectly relax the Si-Ge misfit strain distortion and their through-components are removed out of the crystal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for epitaxially growing a semiconductor crystal of germanium or silicon-germanium mixed crystal on a silicon substrate. Furthermore, 0.98 μm, 1.
A light receiving element sensitive to a wavelength of 3 μm or the like is made of silicon LS.
The present invention relates to a method of manufacturing a bipolar transistor using SiOEIC, germanium, and silicon-germanium mixed crystal, which is integrally formed on I.

[0002]

2. Description of the Related Art A heteroepitaxial structure of silicon and germanium or a mixed crystal of silicon and silicon germanium has attracted attention as a material for dramatically improving the characteristics of heterobipolar transistors and optical elements. Therefore, attempts have been made to form a heterostructure having good crystallinity by a vapor phase growth method such as CVD or MBE.

[0003] Germanium on a silicon substrate is about 4%
It is known to have a lattice mismatch (misfit) of and a growth mode of Stranski-Krastanov type. In the early stage of growth, the surface of the film is flattened by epitaxial growth, but when the film thickness exceeds about 3 atomic layers, an island structure of germanium is formed on the surface, and the film surface is formed. Is significantly impaired. Furthermore, misfit dislocations are introduced from the edge of the germanium island,
In particular, dislocations (called threading dislocations) penetrating in the thickness direction are formed in the film. In order to eliminate such germanium islands and threading dislocations as much as possible, JMBari
In a paper J. Vac Sci. Technol. A5 (4), 1898 (1987), beau et al. attempted a method of removing threading dislocations from a film by high-temperature growth and subsequent high-temperature heat treatment. In addition, since islanding and introduction of threading dislocations can be suppressed by mixing silicon into the germanium layer to form a silicon-germanium mixed crystal, A. Kastalsky et al. In their paper Symposium of the 1st International Symposium.
on silicon Molecular Beam Epitaxy, edited by JCB
ean (Electrochemical Society, Pennington, NJ, 1985), p. 4
In 06, a buffer layer and a superlattice layer having a changed mixed crystal ratio are inserted directly above the III-V substrate to form a germanium layer with few threading dislocations on the upper part.

Also, Igarashi et al. Described a method for forming a Si / SiGe superlattice layer having a flat interface, as described in the 56th Annual Meeting of the Japan Society of Applied Physics, Proceedings of the 1st Edition, page 174. First, SiGe on Si substrate
A method has been proposed in which a layer is formed with a thickness equal to or less than the critical thickness at which roughening occurs, and then a Si coating layer is formed on the SiGe surface. However, this method is a method of forming a Si / SiGe strained superlattice layer lattice-matched to a Si substrate,
This is not a method of forming a lattice-relaxed thin film having no threading dislocation of Ge or SiGe on a Si substrate.

[0005]

With any of the above methods, threading dislocations in a germanium film or a silicon-germanium mixed crystal film cannot be completely removed, and the film surface is flattened at an atomic level. Can not be
Furthermore, it was not possible to completely alleviate the strain in the formed germanium film or silicon-germanium mixed crystal film due to misfit with the silicon substrate. Such non-uniformity of the film structure leads to an increase in leakage current and the like, which is harmful in improving the characteristics of a device manufactured by applying the same.

Accordingly, an object of the present invention is to eliminate such conventional disadvantages, to eliminate threading dislocations in the film and to provide a flat surface.
It is an object of the present invention to provide a method for growing a germanium film or a silicon-germanium mixed crystal film on which a lattice is completely relaxed on a silicon substrate.

[0007]

Means for Solving the Problems The present inventors have conducted various studies to achieve the above object, and as a result, completed the present invention.

The first invention comprises a step of epitaxially growing a germanium film in a layer on a silicon substrate, a step of forming a coating layer made of silicon or a silicon-germanium mixed crystal on the germanium film, and a heat treatment step. And a method for manufacturing a semiconductor device.

According to a second aspect of the present invention, a step of epitaxially growing a first germanium film in a layer on a silicon substrate and a step of forming a coating layer made of silicon or a silicon-germanium mixed crystal on the first germanium film are provided. A heat treatment step; and a step of epitaxially growing a second germanium film in a layer on the coating layer.

According to a third aspect of the present invention, there is provided a step of epitaxially growing a first germanium film in a layer on a silicon substrate, and forming a first coating layer made of silicon or a silicon-germanium mixed crystal on the first germanium film. A first heat treatment step, a step of epitaxially growing a second germanium film in a layer on the first coating layer, and a step of silicon or silicon germanium mixed crystal on the second germanium film. The present invention relates to a method for manufacturing a semiconductor device, comprising a step of forming a second coating layer and a second heat treatment step.

A fourth invention relates to the method of manufacturing a semiconductor device according to the first, second or third invention, wherein the layered film grown on the silicon substrate is a silicon germanium mixed crystal film.

A fifth invention relates to the method of manufacturing a semiconductor device according to any one of the first to fourth inventions, wherein a silicon layer is formed on the uppermost germanium film or the uppermost coating film.

A sixth invention relates to a method of manufacturing a semiconductor device according to the fifth invention, wherein an electrode is formed by doping boron, phosphorus, or arsenic in an uppermost silicon layer.

According to a seventh aspect of the present invention, a Si device serving as a driver or an amplifier is disposed on the surface of a Si substrate, and a groove is formed by etching Si from the surface of the substrate. after covering the film, the GeH ₄ and Cl, or ₂ and the alternating Si ₂ H ₆ and GeH ₄ and Cl ₂ and step 1 are alternately supplied,
A Ge layer or a Si _1-x Ge _x layer serving as a light receiving portion is selectively formed in a groove, and a Si layer is selectively formed in the groove by a step 2 of alternately supplying Si ₂ H ₆ and Cl _2. Alternatively, by further repeating step 1 and step 2,
A light receiving portion composed of a plurality of layers of a Si layer and a Ge layer or a Si _1-x Ge _x layer is selectively formed in the groove, and thereafter, a Si ₂ H ₆
And B ₂ H ₆ and Cl ₂ alternately or Si ₂ H ₆ and PH ₃
Cl ₂ and the alternating or Si ₂ H ₆ and arsenic, Cl ₂ and the electrode layer by supplying alternately or first to sixth any, characterized by selectively formed in the groove The invention relates to a method for manufacturing a semiconductor device.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The principle of the present invention will be described with reference to a case where a germanium film is grown on a silicon substrate. As described above, germanium growth on a silicon substrate has a Stranski-Krastanov type growth mode in which an island structure is formed thereon after layered growth. Since this phenomenon depends on the diffusion distance of germanium atoms on the surface of the growing silicon substrate, for example, if the diffusion distance of germanium is shortened by simultaneously adsorbing hydrogen on the growth surface, the layered germanium epitaxially grown on the silicon substrate can be reduced. A membrane can be obtained. Since such a film does not completely relax the misfit strain and has threading dislocations, a subsequent heat treatment is required, but the heat treatment causes the layered germanium film to change to an island structure again. Resulting in. This is because the compressive strain remains in the layered germanium film.

On the other hand, the present inventor has proposed that if the surface of the layered germanium film thus formed is covered with silicon or silicon-germanium mixed crystal and heat-treated, the germanium film does not have an island structure, That is, it has been found that the dislocation for maintaining the flatness of the surface and for alleviating the misfit distortion is localized at the interface, and no threading dislocation remains in the film.

The formation of such a structure is based on the following principle. FIG. 1A is a cross-sectional view showing a structure in which a layered germanium film 13 is formed on a silicon substrate 12 and a coating layer 11 made of silicon or a silicon-germanium mixed crystal is formed on the surface thereof. At this time, at the interface between the silicon substrate and the layered germanium film, a defect formed by the attachment-type growth due to a short diffusion distance of the growing germanium atom, that is, a glow-in defect 14.
Are present and some are threading dislocations 15. FIG.
(B) shows the structure after heat treatment of such a laminated structure. By the heat treatment, edge-type dislocations (the Burger spectrum indicating the slip amount and direction of the dislocations) are generated with the growth-in defects 14 existing at the interface between the silicon substrate 12 and the layered germanium film 13 as nuclei. Vertical dislocations) 16 are formed. At that time, they are localized at the interface, are arranged in a cross-hatched manner with an interval for completely relaxing the misfit distortion between silicon and germanium, and the penetrating components are removed out of the crystal. In addition, since a coating layer whose lattice constant is smaller than that of germanium is formed on the surface of the layered germanium film where compressive strain remains, tensile stress is applied and the islanding of the germanium film during heat treatment is suppressed. Is done.

According to the above principle, a completely lattice-relaxed germanium film having a flat surface and no threading dislocations in the film can be grown on a silicon substrate.

[0019]

EXAMPLES The present invention will be further described below with reference to examples, but the present invention is not limited to these examples.

Here, an ultrahigh vacuum vapor phase epitaxy (UHV-CVD) apparatus with an ultimate vacuum of 1 × 10 ⁻¹⁰ Torr was used. A 6-inch p-type silicon (100) substrate was used as a sample wafer. The source gas for silicon is 100% disilane (S
i ₂ H ₆ ) and 100% germanium (G
eH ₄₎ was used. The initial substrate surface cleaning is performed in a cleaning liquid (NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 4: 20).
After washing for 0 minutes, HF treatment (HF: H ₂ O = 1: 30,
The natural oxide film was removed by a treatment time of 40 seconds and washing with water for 2 minutes). Further, before growth, in a UHV-CVD apparatus,
A cleaning annealing was performed in vacuum at 800 ° C. for 3 minutes.

Example 1 A substrate temperature of 330 ° C., a flow rate of GeH _{4 of} 20 sccm, and a growth time of 4
In 0 minutes, a Ge layer having a thickness of 200 ° was grown, and a substrate temperature of 3 ° C.
30 ° C., GeH ₄ flow rate 20 sccm, Si ₂ H ₆ flow rate 1 sccm,
After a growth time of 5 minutes, a SiGe layer (cap layer (coating layer)) having a film thickness of 10 ° or less was formed. After that, heat treatment (annealing) at a substrate temperature of 680 ° C. was performed in a UHV-CVD apparatus to alleviate the distortion. Heat treatment is 430-7
It is preferable to carry out in the range of 30 ° C.

FIG. 2 shows G after annealing for strain relaxation.
SE comparing the state of e-film with and without SiGe cap layer
An M photograph is shown (heat treatment at 680 ° C. for 10 minutes). (A) shows the case where there is no cap layer, and (b) shows the case where the cap layer is formed. The difference in surface morphology can be clearly seen. G
By providing a SiGe cap layer on the surface of the e film and annealing, a flat film having good surface morphology was formed.

Next, the relationship between island formation and Ge film thickness / annealing temperature will be described. FIG. 3 is a graph showing these relationships. The growth conditions of the Ge layer (relaxation layer) are a substrate temperature of 330 ° C., a flow rate of GeH _{4 of} 20 sccm, and the growth conditions of the SiGe cap layer are a flow rate of GeH _{4 of} 20 sccm, a flow rate of Si ₂ H _{6 of} 1 sccm, and a growth time of 5 minutes. When the Ge film thickness is 100 °, islands are formed at an annealing temperature of 580 ° C., but at 400 ° C., the surface is flat without an island at 730 ° C. From this result, it can be seen that when the Ge film is stacked thickly, the surface is flat without islanding even if the annealing temperature is increased. It can be selected in the range of allowable temperature and thickness.

If the thickness of the cap layer is increased, islands will not be formed at a high temperature with a thinner film. However, when Ge is further formed on this film, it becomes a source of dislocations. The thickness of the cap layer is suitably from 5 to 20 °.

Next, a cap layer is formed on the Ge film grown at a low temperature, and the Ge film obtained when the annealing conditions are changed thereafter.
The results of TEM observation of the crystallinity of the film will be described. 4 (a) to 4 (c) show the results before and after annealing, respectively.
It is a TEM photograph of the section of the sample which performed annealing at 430 ° C for 10 minutes and 680 ° C for 10 minutes. Sample (a) before annealing is a relatively flat film having a thickness of about 210 ° and no islands formed on the surface. This is because during the growth, the hydrogen adsorbed on the surface suppressed the surface diffusion of Ge atoms, thereby suppressing islanding. However, the crystallinity is poor,
It turns out that there are many threading dislocations. FIG.
The sample (a) was annealed at 430 ° C. for 10 minutes and had a thickness of about 250 °. Compared with (a), it can be seen that misfit dislocations at the interface increase and threading dislocations decrease. FIG. 4C shows the sample of FIG.
The sample is annealed at 10 ° C. for 10 minutes and has a film thickness of about 190 °. As compared with the samples of FIGS. 4A and 4B, the dislocations are localized only at the interface, indicating that a film with good crystallinity was obtained. 4 (a) to 4 (c), it can be seen that the annealing causes misfit dislocations and reduces threading dislocations. Further, it can be seen that the higher the annealing temperature is, the better the annealing temperature is in the range where islanding is not performed.

FIG. 5 shows X-ray diffraction spectra before and after annealing. The peak of the sample before annealing was Ge (40
0) is on the lower angle side, indicating that the Ge film is distorted. After annealing, the peak approaches Ge (400), and the sample annealed at 680 ° C. matches the diffraction position of Ge (400). From this result, it can be said that the annealing at 680 ° C. completely relaxes the distortion.

As described above, by using a UHV-CVD apparatus, a cap layer is formed after flat growth by hydrogen surfactant, and a high-temperature annealing treatment is performed to obtain a flat surface and good crystallinity. The film could be grown.

Embodiment 2 The Ge film formed as described above is lattice-relaxed and has very few dislocations penetrating through the Ge film. Therefore, even if a Ge film is further formed thereon, No new defects occur. This is no different from the growth of Ge on a Ge substrate. Therefore, the first Ge is performed as follows.
A film and a second Ge film were formed.

As a first step, a substrate temperature of 330 ° C. and Ge
H ₄ flow rate 20 sccm, growth time 40 minutes, film thickness 200Å
A first Ge film is grown, and then a substrate temperature of 330 ° C. and G
eH ₄ flow rate 20 sccm, Si ₂ H ₆ flow rate 1 sccm, growth time 5
In minutes, a SiGe cap layer having a thickness of 10 ° or less was formed. Thereafter, annealing was performed at a substrate temperature of 680 ° C. for 10 minutes in a UHV-CVD apparatus in order to alleviate distortion. Next, as a second stage, the substrate temperature is 380 ° C., the flow rate of GeH _{4 is} 20 scc.
m, a growth time of 100 minutes, and a second G
e film was grown.

FIGS. 6 and 7 show that the G grown on the Si substrate is shown in FIG.
4 shows a TEM photograph of a cross section of the e film. As can be seen from FIG. 6, the number of dislocations is small and the crystallinity is good. FIG. 7 is an enlarged TEM photograph of the interface in FIG. 6, which shows that dislocations are localized at the interface. Further, there are many misfit dislocations, but few threading dislocations.

Embodiment 3 After growing a second Ge thick film on the lattice-relaxed first Ge film and finally performing an annealing (second annealing) again, the crystallinity is further improved. This is because the remaining small number of threading dislocations are annealed out by the second annealing. Therefore, the second G of 3000 mm thick
e film is grown, then a cap layer is provided, then 850
A second anneal was performed at 30 ° C. for 30 minutes, and the effect of the presence or absence of the second anneal was examined.

As a first step, a substrate temperature of 330 ° C. and Ge
H ₄ flow rate 20 sccm, growth time 40 minutes, film thickness 200Å
Is grown at a substrate temperature of 330 ° C. and GeH ₄
At a flow rate of 20 sccm, a Si ₂ H ₆ flow rate of 1 sccm, and a growth time of 5 minutes,
A SiGe cap layer having a thickness of 10 ° or less was formed. Thereafter, in order to alleviate distortion, annealing is performed at a substrate temperature of 680 ° C. for 10 minutes in a UHV-CVD apparatus (first annealing).
Was done.

Next, as a second stage, a substrate temperature of 380 ° C.
GeH ₄ flow rate 20 sccm, growth time 100 minutes, film thickness 5
A second Ge film of 2,000 ° C. is grown and then a substrate temperature of 38
At 0 ° C., a flow rate of GeH _{4 was} 20 sccm, a flow rate of Si ₂ H _{6 was} 1 sccm, and a growth time was 5 minutes, a SiGe cap layer having a film thickness of 10 ° or less was formed. Then, to improve the crystallinity, UHV-CV
The second annealing was performed in a D apparatus at a substrate temperature of 680 ° C. for 30 minutes.

FIG. 8 is an X-ray diffraction spectrum of four crystals showing the effect of the second annealing. When the second annealing is performed, the half width becomes narrower and the peak position is Ge.
It can be seen that it is approaching the (400) position. By performing the second annealing in this manner, the crystallinity is improved.

FIG. 9 shows a TEM photograph of the cross section. FIG.
FIG. 9A shows a case where the second annealing is not performed.
(B) shows the case where the second annealing is performed, and both the film thicknesses are about 2900 °. 9A and 9B clearly show that the number of dislocations is smaller when the second annealing shown in FIG. 9B is performed.

Embodiment 4 An Si layer can be formed flat on the Ge film having good crystallinity described above. Therefore, in the present embodiment, the Si layer was formed as follows.

First, the substrate temperature was 330 ° C., the flow rate of GeH _{4 was} 2
0 sccm, a growth time of 70 minutes, and a 400 °
A film is grown, then at a substrate temperature of 330 ° C. and a GeH ₄ flow rate of 2
0 sccm, Si ₂ H ₆ flow rate 1 sccm, growth time 5 minutes, film thickness 1
A SiGe cap layer of 0 ° or less was formed. After that, in order to alleviate the distortion, the substrate temperature is reduced to 7 in a UHV-CVD apparatus.
A first anneal was performed at 20 ° C. for 10 minutes.

Next, at a substrate temperature of 355 ° C. and a GeH ₄ flow rate of 2
A second Ge film having a thickness of 3000 ° is grown at 0 sccm and a growth time of 100 minutes, and then a substrate temperature of 355 ° C., a flow rate of GeH _{4 of} 20 sccm, a flow rate of Si ₂ H _{6 of} 1 sccm, a growth time of 5 minutes and a film thickness of 10 ° or less are obtained. A SiGe cap layer was formed. Thereafter, in order to improve crystallinity, a second annealing was performed at a substrate temperature of 730 ° C. for 30 minutes in a UHV-CVD apparatus.

Finally, a 2000-nm thick Si film was grown at a substrate temperature of 660 ° C., a flow rate of Si ₂ H _{6 of} 20 sccm and a growth time of 10 minutes.

FIG. 10 and FIG. 11 show TEM photographs of cross sections of a case where the Si layer is not grown and a case where the Si layer is grown, respectively. FIG. 10 is a TEM photograph of the second annealing performed after the growth of the second Ge film having a thickness of 3000 °. The actual film thickness is about 2900 °, the surface on the Ge film is flat, and there are few dislocations in the film. FIG.
A second annealing is performed after the growth of the second Ge film of 0 °,
It is a TEM photograph of what grew a Si layer on it. G
The thickness of the e film is about 3200 °, and the thickness of the Si layer is about 240
0 °. A comparison between FIG. 10 and FIG. 11 shows that even if Si is grown on the Ge film, the dislocation in the Ge film does not increase. Also, many dislocations are seen in the Si layer,
Dislocations in the Si layer do not escape to the Ge film side. Therefore,
The crystallinity of the Ge film does not deteriorate due to the growth of the Si layer.

FIG. 12 is an X-ray diffraction spectrum of four crystals comparing the presence or absence of Si growth on the Ge film. From this figure, the peak value is lower when Si is grown on the Ge film. This is the result of growing Si on top. However, since the half width is almost the same in both cases, it can be seen that the crystallinity in the Ge film does not change even if Si is grown on the Ge film.

By forming the above structure,
Ge can be prevented from being exposed on the surface, and when such a structure is formed industrially using a Si process, it is possible to prevent Ge from melting from the surface and contaminating the process line.

Embodiment 5 FIG. 13 shows a device (SiOEIC: Si) according to the present invention.
Opt-Electric Integrated
(Circuits) is schematically shown. First, a drive element portion (driver silicon device) such as a preamplifier and an identification circuit is formed on a Si (100) substrate by a normal silicon process, and the entire surface is covered with an oxide film (FIG. 13A). Next, the drive element portion is masked with a resist, and a groove having a depth of 1 μm, a width of 30 μm, and a length of 500 μm is formed in the silicon substrate by dry etching (FIG. 13).
(B)). After the thermal oxidation, a sidewall of an oxide film is formed on the side surface of the groove by etch-back. At this time, silicon is exposed at the bottom of the groove. Further, arsenic is implanted into the bottom surface by ion implantation to form an n-type layer of about 2 × 10 ¹⁹ cm ⁻³ .

After the contamination on the bottom of the groove is removed by chemical cleaning, a PIN diode as a light receiving element is formed in the above-mentioned groove by selective epitaxial growth (FIG. 11).
(C)). A silicon UHV-CVD apparatus was used for growth. At a substrate temperature of 330 ° C., a GeH ₄ flow rate of 20 sccm, and a growth time of 70 minutes, a first Ge layer having a thickness of 400 ° is grown.
Then, the substrate temperature was 330 ° C., the flow rate of GeH _{4 was} 20 sccm, and the Si ₂
H ₆ flow rate 1 sccm, growth time 5 minutes, film thickness 10 ° or less S
An iGe cap layer was formed. At this time, in order to secure the selectivity, once every 20 minutes of the growth of Ge, 30 minutes of Cl ₂ was added.
Feed in seconds. After that, UHV-C
First annealing was performed in a VD apparatus at a substrate temperature of 720 ° C. for 10 minutes.

Next, at a substrate temperature of 355 ° C., a flow rate of GeH ₄ 2
A second Ge layer having a film thickness of 9000 ° was grown at 0 sccm for 300 minutes, and a substrate temperature of 355 ° C., a GeH ₄ flow rate of 20 sccm, a Si ₂ H ₆ flow rate of 1 sccm, a growth time of 5 minutes, and a film thickness of 10 ° or less were again formed. A SiGe cap layer was formed. At this time, in order to secure the selectivity, the Ge is grown once every 20 minutes.
Each time, Cl ₂ is supplied for 30 seconds. Thereafter, in order to improve the crystallinity, the substrate temperature is set to 730 ° C. in a UHV-CVD apparatus.
A second anneal was performed for minutes.

Finally, at a substrate temperature of 660 ° C., a flow rate of Si ₂ H ₆ was 1 sccm, and a flow rate of B ₂ H ₆ was 10 sccm (1% H ₂ dilution).
00 seconds and Cl ₂ for 30 seconds. By repeating this eight times, 2 × 10 ¹⁹ cm ^{-3 of} 2000 mm thick
A B-doped silicon layer was formed.

Next, the portion of the silicon substrate to which the optical fiber is fixed is etched to a depth of 63 μm and a width of 125 μm, and the optical fiber is fixed so that its core is at the same height as the light receiving portion. A structure was formed so as to be introduced in parallel along (FIG. 13D).

When each electrode is formed, since there is no step on the surface, there is no disconnection due to the step of the wiring, and it is possible to connect between the light receiving section and the Si device as the driver, and these are formed in the same chip. Can be. Further, since there are few defects in the Ge film, the leakage current due to the defects is small. Further, since the Ge film of the light receiving portion can be grown at the end of the device process, there is no possibility that a defect occurs due to a high-temperature heat treatment in the process of forming a silicon device portion serving as a driver and does not cause a dark current. Further, since the PN junction is completely covered by the sidewall oxide film during the process of selective epitaxial growth, generation of dark current due to junction leakage is small. At this time, the capacitance of the avalanche photodiode was 0.3 pF / μ ² when 10 V was applied. FIG. 14 shows the relationship between the reverse bias and the dark current of the present PIN photodiode. Appl. Phys.
Lett. A mesa type as shown in Vol. 49, p. 809 (1986) is also shown for comparison. As is apparent from FIG. 14, the avalanche photodiode embedded by the selective growth has a small dark current and therefore has a high sensitivity. Also, since the light receiving portion has few penetrating dislocations, the dark current is small as in the case of the PIN diode formed on the Ge substrate. 1.3 μm wavelength Nd: YAG
The receiving sensitivity of the present light receiving element when a laser pulse of 140 ps was sent was as good as -36 dBm, which was similar to that of a PIN diode formed on a Ge substrate. Furthermore, it was connected to the driver and amplifier made around the light-receiving part, and it was confirmed that the light-receiving circuit worked integrally.

In the above embodiment, the case where the PIN diode is used for the light receiving section has been described. However, it has been confirmed that the same effect can be obtained by using the avalanche photodiode.

Although the case of growing Ge on Si has been described above, it has been confirmed that the same applies to the growth of Si _1-x Ge _x mixed crystal on Si. However, the mixed crystal ratio x of Si _1-x Ge _x used for the cap layer is set to
It is important that the relationship of y> x be satisfied as compared with the mixed crystal ratio y of _1-y Ge _y . Without such a relationship, islanding occurs because no tensile strain is applied to the surface. Further, in the present embodiment, the description has been given on the silicon substrate.
It is sufficient that single crystal Si is present on the substrate surface, and it is naturally possible to use an SOI substrate.

[0051]

As is clear from the above description, according to the present invention, a germanium film or a silicon germanium mixed crystal film having no threading dislocations in the film, a flat surface, and a complete lattice relaxation is formed on the silicon substrate. Can grow. Further, according to the present invention, the uniformity of the film structure can be improved, and the characteristics of the device can be improved.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram for explaining the principle of the present invention, and is a cross-sectional structure in which a layered germanium film is formed on a silicon substrate and a coating layer made of silicon or a silicon-germanium mixed crystal is formed on the surface thereof. FIG.

FIGS. 2A and 2B are SEM photographs (drawing substitute photographs) comparing the state of a Ge film after annealing with and without a SiGe cap layer (FIG. 2A) without a cap layer, and FIG. 2B with a cap layer formed; ).

FIG. 3 is a graph showing the relationship between islanding and Ge film thickness / annealing temperature.

FIG. 4 is a TEM photograph (a photograph substituted for a drawing) of a cross section of a sample before and after annealing ((a) before annealing, and (b) 430 ° C.).
-10 minutes, (c) 680 ° C for 10 minutes).

FIG. 5 is an X-ray diffraction spectrum of a sample before and after annealing.

FIG. 6 is a TEM photograph (drawing substitute photograph) of a cross section of a Ge film grown on a Si substrate.

FIG. 7 is an enlarged TEM photograph (drawing substitute photograph) of the interface in FIG.

FIG. 8 is an X-ray diffraction spectrum of four crystals in which the presence or absence of the second annealing is compared.

FIG. 9 is a TEM photograph (a photograph as a substitute for a drawing) of a cross section showing the effect of the second annealing ((a) when the last annealing is not performed, and (b) when the last annealing is performed).

FIG. 10 is a TEM photograph (a photograph as a substitute for a drawing) of a cross section of a structure in which no Si layer is grown on a Ge film.

FIG. 11 shows a TE of a cross section of a Si film grown on a Ge film.
It is an M photograph (drawing substitute photograph).

FIG. 12 is an X-ray diffraction spectrum of four crystals comparing the presence or absence of Si growth on a Ge film.

FIG. 13 is a schematic view of a device manufacturing process according to the present invention.

FIG. 14 is a diagram showing a relationship between a reverse bias of a PIN photodiode and a dark current.

[Explanation of symbols]

Reference Signs List 11 coating layer made of silicon or silicon-germanium mixed crystal 12 silicon substrate 13 layered germanium film 14 glow-in defect 15 threading dislocation 16 edge dislocation

Claims (7)

[Claims] 1. A method according to claim 1, further comprising a step of epitaxially growing a germanium film in a layer on a silicon substrate, a step of forming a coating layer made of silicon or a silicon-germanium mixed crystal on the germanium film, and a heat treatment step. A method for manufacturing a semiconductor device. 2. A step of epitaxially growing a first germanium film in a layer on a silicon substrate, a step of forming a coating layer made of silicon or a silicon-germanium mixed crystal on the first germanium film, and a heat treatment step. And a step of epitaxially growing a second germanium film in a layer on the covering layer. 3. A step of epitaxially growing a first germanium film in a layer on a silicon substrate, and a step of forming a first coating layer made of silicon or a silicon-germanium mixed crystal on the first germanium film. A first heat treatment step, and a step of epitaxially growing a second germanium film in a layer on the first coating layer;
A method of manufacturing a semiconductor device, comprising: a step of forming a second coating layer made of silicon or a mixed crystal of silicon-germanium on the second germanium film; and a second heat treatment step. 4. The method according to claim 1, wherein the layered film grown on the silicon substrate is a silicon germanium mixed crystal film. 5. The method of manufacturing a semiconductor device according to claim 1, wherein a silicon layer is formed on the uppermost germanium film or the uppermost coating film. 6. The method according to claim 5, wherein the electrode is formed by doping boron, phosphorus, or arsenic in the uppermost silicon layer. 7. A Si device serving as a driver or an amplifier is provided on the surface of a Si substrate, a groove is formed by etching Si from the surface of the substrate, and a portion other than the bottom of the groove is covered with a silicon oxide film or a silicon nitride film. Later, G
By the step 1 of alternately supplying eH ₄ and Cl ₂ or alternately supplying Si ₂ H ₆ and GeH ₄ and Cl ₂ , a Ge layer or a Si _1-x Ge _x layer serving as a light receiving portion is selectively formed in the groove. And selectively forming a Si layer in the groove by Step 2 of alternately supplying Si ₂ H ₆ and Cl ₂ , or repeating Steps 1 and 2 to obtain a Si layer and Ge.
A light-receiving portion composed of a plurality of layers or a plurality of layers of Si _1-x Ge _x layers is selectively formed in the trench, and then, Si ₂ H ₆ and B ₂ H ₆ and Cl ₂ are alternately or Si ₂ H ₆ and PH ₃ and the electrode layer by alternately supplying Cl ₂ and the alternating or Si ₂ H ₆ and arsenic and Cl ₂ according to claim 1, wherein the selectively formed in the groove A method for manufacturing a semiconductor device according to claim 1.