JPH0622283A - Video signal processing unit - Google Patents

Abstract

PURPOSE:To obtain a regular macro vision signal. CONSTITUTION:A Y signal obtained by applying Y/C separation to a video signal is stored in an odd number field memory 46 or an even number field memory 48 depending on the field of the Y signal. In this case, a macro vision signal whose level is a pedestal level or over is stored together with the Y signal. On the other hand, the macro vision signal whose level is a pedestal level or below obtained from the video signal through synchronizing separation by a synchronizing separator circuit 20 is stored in an idle area of a field memory 54 by one field via a switch circuit 52. A RMVFLD signal is outputted from a read system of a control circuit 40 in response to a type of a field of the macro vision signal whose level is a pedestal level or below outputted from the field memory 54, the macro vision signal whose level is a pedestal level or over in the same field as the macro vision signal whose level is a pedestal level or below is outputted from the odd number field memory 46 or the even field memory 48 and synthesized by a mixer 76.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus, and more particularly to a video apparatus for processing a signal by using a memory for converting a television system, for example, and storing a video signal including a macrovision signal in the memory. The present invention relates to a video signal processing device that writes and reads back a video signal written in this memory.

[0002]

2. Description of the Related Art When a video signal to which a macrovision signal is added is input, a portion above the pedestal level of the video signal and a portion below the pedestal level are separately written in the memory and combined when read from the memory. A method of doing so is proposed in Japanese Patent Application No. 3-213861 of the present applicant. By this conventional technique, the vertical resolution of the digital conversion output is improved, and the waveform distortion of the sync signal portion can be solved.

[0003]

In this prior art, since one field memory is used in the luminance signal processing system, the following problems occur when switching between the PAL system and the NTSC system, for example. For example, to convert a PAL system that displays 25 images per second to an NTSC system that displays 30 images per second, simply convert 5 images out of 25 images displayed per second by the PAL system. It may be selected and added to 25 images to make a total of 30 images per second. However, in this case, since the same number of images are continuous, the movement becomes unnatural. On the other hand, when switching from the NTSC system to the PAL system, it is sufficient to thin out five images per second, but the motion is skipped and the screen motion becomes unnatural as before.

Therefore, by changing the weighting of images in two consecutive fields (weighting to 30:70, etc.) and synthesizing new images from these images, the above-mentioned unnaturalness of motion is eliminated. it can. That is, a technique has been proposed in which a plurality of field memories are used in the luminance signal processing system to perform field synthesis of video signals. However, in this technique, when the position of the macrovision signal from the horizontal synchronizing signal (Hsync) is different between the odd field and the even field as in the input signal shown in FIGS. 7A and 7B, for example, Synthesizes a macrovision signal below the pedestal level in the odd field and a macrovision signal above the pedestal level in the even field, or a macrovision signal below the pedestal level in the even field and a macrovision signal above the pedestal level in the odd field 7C and 7D are output, respectively.
There is a problem that the normal macrovision signal shown in (A) and (B) cannot be reproduced.

Therefore, a main object of the present invention is to reliably synthesize a macrovision signal below a pedestal level and a macrovision signal above a pedestal level for each same field to reproduce a normal macrovision signal. It is to provide a video signal processing device capable of performing the above.

[0006]

SUMMARY OF THE INVENTION According to the present invention, a video signal including a macrovision signal composed of positive and negative convex pulse trains on the basis of a pedestal level is divided into a component below the pedestal level and a component above the pedestal level. In the video signal processing device in which the data read from each memory are combined by the synthesizing means, the memory for storing the component at the pedestal level or higher includes the odd field memory and the even field memory. The video signal processing device is characterized in that a component having a pedestal level or higher in the same field is supplied to the synthesizing means from an odd field memory or an even field memory in synchronization with a component having a level or lower.

[0007]

According to the type of field (odd field or even field), a macrovision signal having a pedestal level or higher is provided together with a Y signal obtained by separating the video signal from Y / C, respectively. Store in memory. Also, among the signals obtained by synchronously separating the video signals, the macrovision signal below the pedestal level is input to another memory, and depending on the field type of the macrovision signal below the pedestal level output from this memory. The control circuit selects an odd field memory or an even field memory, and outputs a macrovision signal below the pedestal level and a macrovision signal above the pedestal level in the same field. Therefore, the macrovision signal below the pedestal level and the macrovision signal above the pedestal level output from the odd field memory or even field memory are always in the same field, and the original macrovision signal is reproduced.

[0008]

According to the present invention, since the macrovision signal below the pedestal level and the macrovision signal above the pedestal level are surely combined for each same field, the original normal macrovision signal can be reproduced. The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1 and 2, a video signal processing apparatus 10 of this embodiment is used for a video tape recorder, for example, and field synthesis is performed using a memory for two fields of Y signal and one field of C signal. To do. The signal processing device 10 includes an AGC circuit 12. In the AGC circuit 12,
The video signal as shown in FIG. 3A including the macrovision signal reproduced from the video soft tape is input terminal 14
The signal level is made constant by the AGC circuit 12. The output of the AGC circuit 12 is a low pass filter (L
It is supplied to the PF) 16, the bandpass filter (BPF) 18, and the sync separation circuit 20, respectively.

In the LPF 16, C of the video signal is
The (color) signal component is removed, and only the Y (luminance) signal is supplied to the delay circuit 24 via the amplifier circuit 22. The delay circuit 24 adjusts the deviation of the delay time associated with the Y / C processing, and then the pedestal clamp is performed by the clamp (CLP) circuit 26. On the other hand, in the video signal input to the BPF 18, only the C signal component is extracted by the BPF 18, and the C signal is input to the chroma decoder 28. Here, the C signal is converted into RY and BY color difference signals, passed through the LPFs 30 and 32 and the amplifier circuits 34 and 36, respectively, and then time-division multiplexed by the multiplexer 38.

Further, the sync separation circuit 20 outputs a sync signal extracted from the video signal and a macrovision signal below the pedestal level, of which the sync signal is a control circuit 40 including a system control section, a writing system and a reading system. And the macrovision signal is written to the field memory 54. The Y signal output output from the clamp circuit 26 is converted into a digital signal by the A / D converter 42, as shown in FIG. The Y signal data is written in the odd field memory 46 or the even field memory 48 via the switch circuit 44 depending on the type of the field (odd field or even field). A / D converter 4
Since the A / D conversion range of 2 is set to the pedestal level or higher, at the same time, the part of the macrovision signal that is higher than the pedestal level is also stored in the odd field memory 44 or the even field memory 46. The odd field memory 44 and the even field memory 46 are Y-system field memories. Here, the switch circuit 4
The switching of 4 is controlled by the WODD signal given from the writing system of the control circuit 40 and discriminating between the odd field and the even field of the input video signal, and the writing field is selected. In the WODD signal, as shown in FIG. 3C, the odd field is stored in the odd field memory 44.
"H" is output when writing into the even field and "L" is output when writing into the even field memory 46.

The C signal output from the multiplexer 38 is converted into a digital signal in the same manner as the Y signal by the A / D converter 50, and the C signal is passed through the switch circuit 52.
It is stored in the field memory 54 of the system. Further, in the empty area of the field memory 54, the sync separation circuit 20
Macrovision signal below the pedestal level from
Fields are written. The switching of the switch circuit 52 is controlled by the WMVG signal from the write system of the control circuit 40. As shown in FIG. 3B, the WMVG signal is "H" only in the macrovision period (the period in which the macrovision signal is added) in the input video signal.
Is output and the switch circuit 52 is connected to the sync separation circuit 20 side.

Next, the Y / C signal data is read from the odd field memory 46, the even field memory 48 and the field memory 54 at a constant timing asynchronous with the writing of the video signal. The Y signal data read from the odd field memory 46 and the even field memory 48 is the field synthesis circuit 56.
Are combined with the desired weighting. Field synthesis circuit 5
6 creates a new image to be used when converting the system between the NTSC system and the PAL system. Also, the odd field memory 46 and the even field memory 4
Either one of 8 is selected by the switch circuit 58. Then, the switch circuit 60 is connected to the field synthesizing circuit 56 side during the period other than the macrovision period, gives Y signal data to the D / A converter 62, and is connected to the switch circuit 58 side during the macrovision period, and switches. Odd field memory 4 determined by circuit 58
The macrovision signal from the 6 or even field memo 48 is applied to the D / A converter 62.

Here, the field synthesizing circuit 56, the switch circuit 58 and the switch circuit 60 are respectively the field synthesizing control signal from the read system of the control circuit 40, R.
It is controlled by the MVFLD signal and the RMVG signal which gives an output of "H" during the macrovision period when reading the video signal as shown in FIG. RMVFLD
The signals are, for example, as shown in FIG. 4, writing and reading of the video signal (the WMVG signal and the RMV signal, respectively).
(Indicated by the G signal) operates asynchronously,
This is a signal for reproducing a normal macrovision signal, and is, for example, a field selection circuit 64 as shown in FIG.
Generated by. The field selection circuit 64 includes two D-FFs 66 and 68 and an AND gate 70,
It is configured in the control circuit 40.

Referring to FIG. 6, field selection circuit 64
First, in the period T1, the phase of the RMVG signal leads the phase of the WMVG signal. Therefore, during the WMVG period, the macrovision signal below the pedestal level is written in the field memory 54, but at this time, it is necessary to read the macrovision signal from the field memory 54 during the preceding RMVG period.
In the WMVG period of the period T1, the WODD signal is "L" and the even field is being written to the field memory 54. Therefore, in the previous RMVG period, the macrovision signal from the field memory 54 to the pedestal level of the odd field or lower. Will be read. Therefore, the Y signal data of the same odd field and the macrovision signal of the pedestal level or higher can be read from the Y system field memory. That is, the RMVFLD signal output from the control circuit 40 is set to “H”, the switch circuit 58 is connected to the odd field memory 46 side, and the odd field is read from the odd field memory 46.

In the period T2, the above-mentioned period T
As in the case of 1, the phase of the RMVG signal leads the phase of the WMVG signal, but in the WMVG period, the WODD
The signal is "H" and the field memory 54 is about to write an odd field. Therefore, in the RMVG period before that, since the macrovision signal below the pedestal level of the even field is read from the field memory 54, the RMVFLD signal is also set to "L" and the switch circuit 58 is connected to the even field memory 48 side. The even field memory 48 is controlled to read the even field.

Further, in the period T3, the phase of the RMVG signal is behind the phase of the WMVG signal. Therefore,
During the WMVG period, the macrovision signals in the same field as the macrovision signals below the pedestal level written in the field memory 54 are sequentially read out. In this case, the WODD signal is "L" and the even field is written in the field memory 54. Therefore, WMVG
Even fields are read from the field memory 54 also in the RMVG period following the period. Therefore, RMV
The FLD signal is set to "L", the switch circuit 58 is connected to the even field memory 48 side, and the even field memory 48 is controlled to read the even field. In addition, in FIG. 6, and are respectively D- of FIG.
Outputs from FFs 66 and 68 are shown.

In this way, the switch circuit 58 is connected to the RM.
By controlling with the VFLD signal, the same field as the macrovision signal output from the C-system field memory 54 is displayed in the Y-system odd field memory 46.
Alternatively, the Y signal data and the macrovision signal can be read by selecting from the even field memory 48. Therefore, even if the macrovision signal can be written in the field memory 54 for only one field, it is possible to reproduce the regular macrovision signal in which the timings above and below the pedestal level are not shifted.

The Y signal data read in this way and the macrovision signal above the pedestal level are:
It is input to the mixer 76 via the D / A converter 62, the LPF 72, and the CLP circuit 74. In addition, the C signal data from the field memory 54 is the D / A converters 78 and 80 and the LPF 8 as the RY signal data and the BY signal data during the period other than the macrovision period.
It is input to the chroma encoder 86 via 2, 84. The output from the chroma encoder 86 is band-limited by the BPF 88, Y / C mixed in the mixer 76, input to the sync signal adding circuit 90, and the sync signal is added. The sync signal added by the sync signal adding circuit 90 is the macrovision signal below the pedestal level read from the field memory 54 and the control circuit 40.
And the composite sync signal (R.Csync) of the read system generated by the read system of No. 1 of FIG. In this way, the output to which the synchronization signal is added becomes the output terminal 9 as the output of the video signal shown in FIG.
It is output from 4.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a continuation of the embodiment of FIG.

FIG. 3 is a timing diagram showing each signal of this embodiment.

FIG. 4 is an illustrative view showing a phase relationship between an RMVG signal and a WMVG signal.

FIG. 5 is a circuit diagram showing an example of a field selection circuit.

FIG. 6 is a timing diagram illustrating the operation of the circuit of FIG.

FIG. 7 is a waveform diagram showing a timing shift between an input signal and an output signal in the conventional technique.

[Explanation of symbols]

 10 ... Video signal processing device 16 ... LPF 18 ... BPF 20 ... Sync separation circuit 40 ... Control circuit 44, 52, 58, 60 ... Switch circuit 46 ... Odd field memory 48 ... Even field memory 54 ... Field memory 64 ... Field selection circuit 76 ... Mixer

Claims (1)

[Claims] 1. A video signal containing a macrovision signal consisting of a pulse train that is positive and negative convex with respect to the pedestal level is divided into a component below the pedestal level and a component above the pedestal level, and each is written into a memory. In a video signal processing device configured to synthesize data read from a memory by a synthesizing means, a memory for storing components at or above the pedestal level includes an odd field memory and an even field memory, and is synchronized with components at or below the pedestal level. The video signal processing apparatus is characterized in that a component having a pedestal level or higher in the same field is given to the synthesizing means from the odd field memory or the even field memory.