JPH0622275A - Electronic video signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To compress information quantity required for recording by employing a means adopting a high efficiency coding technology for a video signal suitable for a picture characteristic. CONSTITUTION:A high efficiency coding section 4 implements moving compensation inter-frame prediction coding, a DCT orthogonal coding, entropy coding processing and generates coded signals YE, CRE of a luminance and color difference components. A high efficiency decoding section 12 implements reverse signal processing to that of the high efficiency coding section 4 and decodes picture signals Y, CR of the luminance component and the color difference component. The high efficiency coding technology for the video signal consists of combinations of moving compensation inter-frame prediction coding, orthogonal transformation coding by discrete cosine transformation(DCT) and entropy coding. Then the redundancy of the picture in the timewise direction is reduced by the moving compensation inter-frame prediction coding and the redundancy of the picture in the 2-dimension horizontal and vertical regions is reduced by the orthogonal transformation coding. Furthermore, a code bit number required for recording is compressed by entropy coding.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal recording / reproducing apparatus, and more particularly to a recording / reproducing apparatus suitable for digitally recording a digitized video signal and audio signal.

[0002]

2. Description of the Related Art In digital recording of video signals, S / N
It has excellent characteristics that are difficult to realize with conventional analog recording, such as recording / reproducing of high-quality images with a high ratio and no deterioration of S / N ratio due to dubbing. For this reason, research and development of digital recording of video signals in various forms for recording and reproducing high-quality, high-definition, and high-quality images have been advanced. And digital V for high definition
TR, D1-VTR (component compatible) D2-VT
Commercial VTRs such as R have already been put to practical use and have been introduced and used in broadcasting stations. these,
Since it is necessary to faithfully record and reproduce the material in the digital VTR for business use, the PCM-encoded video signal is digitally recorded. Therefore, the recording bit number is 140M.
It is an extremely large amount from 1 bit / second to 1 Gbit / second.

On the other hand, research and development on digital recording of video signals for home use are also in progress. In this home-use digital VTR, the amount of information is compressed by a high-efficiency coding technique that focuses on the redundancy of image signals.
A study is being made to realize a relatively small recording bit number of Mbit / sec to 30 Mbit / sec.

[0004]

In any of the above-mentioned conventional techniques, a magnetic recording medium (magnetic tape, magnetic disk) or an optical recording medium (optical laser disk, etc.) is used as the recording medium. However, in these recording media, it is inevitable that random code errors and burst errors (code errors concentrate in one place) occur due to the moving mechanism of the medium, scratches, and the like. Further, since the DC component cannot be recorded, it is necessary to record with a signal having a DC balance.

Therefore, in the prior art, error correction code addition, image data shuffling (interleaving), n
The bit code is a DC-balanced m-bit code (m>
Complex signal processing such as nm conversion (e.g., 8-10 conversion) for converting into n) is indispensable. In addition, there is also a problem that the coding efficiency (ratio of image data to the total number of recording bits) is reduced by this signal processing.

It is an object of the present invention to provide a video signal recording / reproducing apparatus which has a non-movable mechanism and is capable of digitally recording a video signal with excellent code efficiency.

[0007]

In order to achieve the above object, the present invention employs a means of high-efficiency encoding technology for video signals that is more suitable for the characteristics of an image, and significantly compresses the amount of information required for recording. Planned. Further, in the present invention, an IC memory card composed of a semiconductor memory is adopted as a recording medium, recording / reproducing of a signal by a non-movable mechanism is realized, and at the same time, coding efficiency is improved.

Further, in the present invention, the recording in the cinema mode is adopted for the material of the cinema image, which uses the video signal constituted by the same number of frames as the number of frames, and the recordable time is extended.

[0009]

The high-efficiency coding technique of the video signal according to the present invention comprises a combination of motion-compensated interframe predictive coding, orthogonal transform coding by discrete cosine transform (hereinafter abbreviated as DCT), and entropy coding. Then, the motion-compensated interframe predictive coding is performed to reduce the redundancy in the time direction of the image. Next, the orthogonal transform coding by the DCT is performed to reduce the redundancy in the horizontal and vertical two-dimensional regions of the image. Furthermore, variable-length coding is performed in which an output code having a short code length is assigned to a code having a high occurrence probability by entropy coding, and the number of code bits required for recording is 5 Mbit.
Significantly compresses at about / second. It should be noted that the deterioration of image quality due to this encoding is such that it cannot be detected except for a very special image, and the image quality can be achieved for business use without any practical problems.

Further, in the present invention, a semiconductor memory is used as a recording medium. In this semiconductor memory, random code errors rarely occur, and burst code errors do not occur at all. Therefore, measures against code errors, which are indispensable in the prior art, that is, addition of error correction codes,
Signal processing such as shuffling of image data becomes unnecessary. Further, since the semiconductor memory does not have a problem of direct current cut, signal processing of nm conversion for achieving direct current balance becomes unnecessary. Therefore, it is possible to perform recording / reproduction with a signal having extremely high code efficiency. Further, in the recording medium of the prior art, there is a problem that the mechanism is extremely complicated to perform recording / reproducing in the form of parallel data, and it is difficult to perform stable operation. However, in the present invention, for example, in units of bytes. Writing and reading operations to and from the semiconductor memory can be easily realized with parallel data.

Further, in the present invention, by recording in the cinema mode, for example, in the case of a cinema image material consisting of 24 frames per second, it is possible to record with a video signal composed of 24 frames per second corresponding thereto. Therefore, for a recording medium having the same recording capacity, the recording time can be extended by 1.25 times (30/24) as compared with a general television image (constructed at 30 frames per second).

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the block diagram shown in FIG. This is suitable for a video signal of a composite color TV signal in which a color signal is superimposed on a luminance signal like an NTSC signal of the current television system.

The composite color TV signal VC is sampled by the A / D converter 1 at a frequency four times as high as the color subcarrier, and converted into a digital signal. And the preprocessing unit 3
Then, the luminance component and the color component are separated by the YC separation process, the color difference signals I and Q are demodulated by the color signal demodulation process, and the color difference signal I,
Thinning processing of Q sample points (for example, 1/2 sub-sampling operation in each of the horizontal and vertical directions) and time division multiplexing processing are performed to generate an image signal Y of a luminance component and an image signal CR of a color difference component.

The high-efficiency encoder 4 performs motion compensation interframe predictive coding, orthogonal transform coding by DCT, and entropy coding to generate coded signals YE and CRE of luminance and chrominance components.

On the other hand, the audio signal is sampled by the A / D converter 2 according to, for example, the characteristics of the CD (compact disc) specification and converted into a digital signal. Then, the buffer memory unit 101 corrects the time delay caused by the signal processing on the image signal, and outputs the delay-corrected signal ADS.

In the multiplex section 5, as will be described later, coded signals YE, CRE, and audio signals corresponding to a plurality of sub-blocks of the image signal (each sub-block is composed of NH × NV pixels of horizontal NH and vertical NV). A recording signal RD is generated by time division multiplexing of ADS.

The recording / reproducing IC memory card section 6 has an I / O
The control unit 7, the semiconductor chip memory unit 8, and the memory control unit 9 are included. And the external control circuit 1
In accordance with the control signal CT of the recording instruction and the reproduction instruction supplied from 0, the memory control unit 9 controls the addresses of the signals necessary for the writing operation and the reading operation of the signal to the semiconductor chip memory unit 8 and the I / O control unit 7. Generates the control signal required for input / output operation at. Then, a control signal CT for instructing recording
Thus, the recording signal RD is stored in the memory of the semiconductor chip memory unit 8 at a predetermined address, and the recording signal RD is recorded. On the other hand, the reproduction signal PBD read from the memory of the semiconductor chip memory unit 8 at the predetermined address in response to the reproduction instruction control signal CT, the demultiplex unit 11 encodes the luminance and chrominance component encoded signals YE,
Separated into CRE and audio signal ADS.

The high-efficiency decoding unit 12 performs signal processing reverse to that of the high-efficiency encoding unit, and decodes the image signal Y of the luminance component and the image signal CR of the color difference component.

In the post-processing section 13, the image signal C of the color difference component
Color difference signals I and Q by R separation and sample point interpolation processing
Signal processing such as multi-tone processing, color modulation processing, and conversion into three primary color signals R, G, and B by a matrix calculation operation, and a signal SV in which a color signal is superimposed on a luminance signal and a luminance component signal SY. The component signal SC and the three primary color signal components SR,
Generate SG and SB. Then, it is converted into an analog signal by the D / A converter 14, and the composite color TV signal VC, the luminance signal Y and the color signal C corresponding to the S mode, the three primary color signals R, G, B are used.
To play.

On the other hand, the buffer memory unit 102 corrects the time delay generated in the decoding process of the image signal, and D /
The A converter 15 converts the analog signal into an analog signal and reproduces an audio signal synchronized with the image signal.

Next, each block portion in this embodiment will be described.

FIG. 2 shows an embodiment of the preprocessing unit 3. The input composite color TV signal is horizontally and
A luminance / color signal separation operation is performed by vertical two-dimensional or horizontal / vertical / time three-dimensional motion adaptive processing to separate into a luminance component YS and a color component CS. The color demodulation unit 17 synchronously detects the color component CS with the color subcarrier fsc to demodulate the color difference signals I and Q. The pre-filter circuit 18 removes a component that causes aliasing distortion by, for example, decimating the sampling points by ½ each in the horizontal and vertical directions. Then, the sub-sampling circuit 19 performs a decimation operation of 2: 1 on the sampling points, and the multiplexer 20 time-division-multiplexes these output signals to generate an image signal CR of a color difference component. In addition, the delay circuit 21
The image signal Y of the luminance component is generated by the signal whose time delay has been corrected by. The reason why the sampling points are thinned out for the chrominance components is that the visual characteristics of the chrominance components are deteriorated as compared with the luminance components. This is because it is difficult and the amount of information can be compressed significantly by using this property.

Next, FIG. 3 shows an embodiment of the high efficiency coding unit 4. In this example, the sampled horizontal NH pixels,
Motion-compensated interframe predictive coding in units of sub-blocks composed of NH × NV pixels composed of vertical NV pixels,
Orthogonal transform coding by CT is performed. Based on the luminance signal Y of the current frame and the decoded luminance signal YD of the previous frame, the motion vector extraction unit extracts the motion vector information MV per frame by a block matching method or the like in sub-block units. Then, the motion compensation prediction circuit unit 28 adds the motion vector information M to the signal YD of the previous frame.
A motion compensation process is performed at V to generate a motion compensated prediction signal YP of the current frame. Then, the subtraction circuit 22 subtracts the signal Y from the prediction signal YP to extract the prediction error signal FD by the motion compensation interframe prediction coding.

In the DCT calculation unit 23, the prediction error signal FD
And the DCT transform matrix to perform a matrix operation to obtain a DCT
The coefficient S1 is generated. Then, the adaptive quantizer 2
In 4, the quantization level is changed according to the signal BCT indicating the information amount in the buffer unit 26, and a finely quantized signal S1Q is generated when the buffer amount is small, and a coarse quantized signal is generated when the buffer amount is large. Then, the entropy coding unit 25 performs a variable length coding process in which codes having different code lengths are assigned according to the occurrence probability of the signal S1Q to generate a coded signal SL. Then, the variable length coded signal sequence is written in the buffer unit 26. on the other hand,
This signal sequence is read from the buffer unit 26 at a constant speed to generate an encoded signal S2. Then, in the multiplexing unit 33, the coded signal S2 in units of sub-blocks and the motion vector information M
V is added to generate the encoded signal YE of the luminance component.

On the other hand, the inverse quantizer 32 converts the signal S1Q into the original DCT coefficient S1 ', and the inverse DCT calculator 31.
Then, an inverse matrix calculation operation is performed to generate a prediction error signal FD '. Then, the addition circuit 30 adds the signal YP to decode the luminance signal Y ′. Then, the signal is stored in the frame memory of the memory unit 29, and the signal delayed by one frame period is output as the luminance signal YD of the previous frame.

Next, FIG. 4 shows a configuration example of the recording signal RD in the multiplex section 5. FIG. 1A shows an example of the structure of this one packet, which includes a packet synchronization section SB, a luminance corresponding to a plurality of sub-blocks, a video luminance data section which is an encoded signal of a color difference component, a video color data section, and audio data. It is composed of parts. Further, FIG. 2B shows the structure of this packet synchronization unit, in which a synchronization code for identifying a packet delimiter, a first subblock number of subblocks included in the packet, and a first block indicating the last subblock number are included. The code of the address and the last block address is assigned. FIG. 11C shows an example of the structure of the data section. The video luminance and video color data are composed of the coded data S2, the motion vector information MV, and the sub-block end information BE indicating the sub-block boundaries for each sub-block. Then
A data part is formed by the information of the plurality of sub-blocks.

An example of this is shown in FIG. The selection unit 34 temporarily stores the input signals YE, CRE, and ADS, and outputs the sub block information SBIF of the stored data. Further, in accordance with the control signal SLFG, corresponding signal data (video brightness, video color, audio) is read out from the temporarily stored data and output. The identification code adding section 35 adds the code of the packet synchronization section, the sub-block end information, etc., and generates the recording signal RD. The control unit 36 produces signals necessary for a predetermined operation, a control signal SLFG, etc., based on the control signal from the control circuit 10 and the sub-block information SBIF.

Next, an embodiment of the demultiplexer 11 is shown in FIG. The reproduction signal PBD read from the recording / reproduction IC memory card unit 6 is input to the identification code extraction unit 37 and the selection distribution unit 38. Then, the identification code extraction section 37 detects the synchronization code SYNC of the packet synchronization section of the reproduction signal PBD, the head block address FBN, the last block address EBN, and the sub block end information BE, and outputs the control signal SLCT necessary for data separation. To generate.
In accordance with this signal SLCT, the selective distribution unit 38 separates and outputs the data of the encoded signal YE of the luminance component, the encoded signal CRE of the color component, and the audio signal ADS from the reproduction signal PBD.

Next, FIG. 7 shows an embodiment of the high efficiency decoding unit 12. The separation unit 39 separates the variable length coded signal SL of the luminance component and the motion vector information MV. In the entropy decoding unit 40, for example, decoding processing by table lookup is performed, and decoding is performed into the fixed-length code S1Q. The inverse quantization unit 41 performs processing such as inverse quantization by table lookup and decodes the DCT coefficient S1. Then, the inverse DCT operation unit 42 performs an operation of inverse DCT matrix operation and decodes the prediction error signal FD. Then, in the adder circuit 43, the prediction error signal F is added to the prediction signal YP.
D is added and the decoded luminance signal Y is output. The luminance signal Y is supplied to the memory section 44, and the luminance signal YD delayed for one frame period is generated. Then, the motion compensation prediction circuit unit 45 generates a motion compensated prediction signal YP based on the luminance signal YD and the motion vector information MV. The same signal processing is performed on the coded signal CRE of the color component to decode the image signal CR of the color difference component.

Next, an embodiment of the post-processing section 13 is shown in FIG. In the separating unit 46, from the image signal CR of the color difference component,
The components of the time-division multiplexed color difference signals I and Q are separated. Then, the oversampling circuit 47 performs oversampling processing for doubling the sampling points in the horizontal and vertical directions by inserting zero values. Then, the post filter circuit 48 extracts a signal component in a predetermined frequency band, and the color difference signals I and Q having the same sampling structure as the luminance signal are extracted.
To decrypt. On the other hand, the delay circuit 49 corrects the time delay generated by the signal processing of the color difference components.

The color modulation circuit 50 quadrature amplitude modulates the color difference signals I and Q with the color subcarrier fsc to generate a color signal C. Further, the RGB conversion circuit 51 performs a matrix calculation process to convert the three primary color signals R, G, from the luminance and color difference signals.
Convert to B.

The adder circuit 52 adds and multiplexes the chrominance signal C to the luminance signal, and the process circuit 53 adds the synchronizing signal and the burst signal to generate a composite signal SV. On the other hand, in the process circuit 54, a sync signal is added to the luminance signal to add the signal SY, and a burst signal is added to the color signal to generate the signal SC.

Further, in the process circuit 55, the synchronizing signals are added to the three primary color signals R, G and B to add the signals SR, SG and SB.
To generate.

Next, FIG. 9 shows an example of the structure of the recording / reproducing IC memory card unit 6. The I / O control unit 7 performs an operation of fetching the data of the recording signal RD and outputting the data read from the semiconductor chip memory unit 8 as the reproduction signal PBD according to the control signal R / PBCT for the recording instruction and the reproduction instruction. . Note that this operation is performed in the form of parallel data in units of bytes, for example, to reduce the operation speed of the semiconductor chip memory unit. The semiconductor chip memory unit 8 is
.. 8n. Each memory unit is composed of a large capacity memory cell (each memory cell is in the form of RAM or ROM) having a capacity of several M bits or more. In addition, the memory control unit 9 controls write signals, read controls, addresses, etc., which are necessary for the operation of the semiconductor chip memory unit, according to a control signal CT supplied from the outside.
Generate O control signal R / PBCT.

As described above, according to the present embodiment, the amount of information required for recording is extremely small with respect to the video signal of the composite color TV signal, and it is of high quality and high quality for business use. A recording / reproducing device capable of reproducing a fine image can be realized. Further, this embodiment has a configuration suitable for an LSI, and is also effective for downsizing the device and making it economical.

Next, a second embodiment of the present invention is shown in FIG.
The entire block diagram shown in FIG. This is suitable for a component type signal such as a video signal of three primary color signals R, G, B, or a luminance signal Y, color difference signals RY, BY, and the like. Here, the three primary color signals R, G are used. , B is shown.

The three primary color signals R, G, B (the scanning form is the same as in the current television system) are sampled by the A / D converter 56, for example, at a frequency four times as high as the color subcarrier, and digitized. Converted to the signal. Then, in the preprocessing unit 57, conversion to luminance signals, color difference I and Q signals, thinning processing of sampling points of the color difference I and Q signals (for example, 1/2 sub-sampling operation in the horizontal and vertical directions, respectively), and time The division / multiplexing process is performed to generate a luminance component image signal Y and a color difference component image signal CR.

The high-efficiency encoder 4 performs motion compensation interframe predictive coding, orthogonal transform coding by DCT (discrete cosine transform), and variable-length coding by entropy coding, and a luminance component and a color difference component. The encoded signal Y of
Generate E and CRE.

On the other hand, the audio signal is sampled by the A / D converter 2 with the characteristics of, for example, a CD (compact disk) specification, and converted into a digitized signal. Then, the buffer memory unit 101 corrects the time delay generated in the signal processing for the image signal, and creates the signal ADS having the same delay.

In the multiplex section 5, the encoded signal Y
E, CRE, and audio signal ADS are time-division-multiplexed, and a sync code and the like are added to form a recording signal RD in a packet form. Then, this signal is recorded on the recording medium of the recording / reproducing IC memory card unit 6.

The recording / reproducing IC memory card unit 6 has an I / O
The control unit 7, the semiconductor chip memory unit 8, and the memory control unit 9 are included. Then, the memory control unit 9 controls the address and the like required for the signal writing operation and the reading operation to the semiconductor chip memory unit 8 by the recording instruction and reproduction instruction control signal CT supplied from the external control circuit 10. Signals and control signals for controlling the input / output operation of the I / O control unit 7 are generated. Then, according to the recording instruction,
The recording signal RD is stored in the memory of the semiconductor chip memory unit 8 at a predetermined address, and the recording signal RD is recorded.

On the other hand, the reproduction signal PBD read from the memory at a predetermined address of the semiconductor chip memory unit 8 according to the reproduction instruction is encoded by the demultiplexing unit 11 with the luminance signals, the color difference component encoded signals YE and CRE, and the voice signal, respectively. The signal ADS is separated.

The high-efficiency decoding unit 12 performs signal processing reverse to that of the high-efficiency encoding unit, and decodes it into an image signal Y of a luminance component and an image signal CR of a color difference component.

In the post-processing section 13, the color difference image signal C
Signal processing such as separation of color difference I and Q components of R, conversion into original sampling structure signal by sampling point interpolation processing, color modulation processing, conversion into three primary color signals R, G and B by matrix calculation The composite signal SV in which the color signal is superimposed on the luminance signal, the luminance component signal SY, and the color component signal S
C, and three primary color signal components SR, SG, SB are created.
Then, it is converted into an analog signal by the D / A converter 14, and the composite color TV signal VC, the luminance signal Y and the color signal C corresponding to the S mode, and the three primary color signals R in the component form,
Play G and B.

On the other hand, the audio signal ADS is corrected in the buffer memory unit 102 for the time delay generated in the decoding process of the image signal. Then, the D / A converter 15 converts it into an analog signal, and reproduces an audio signal synchronized with the image signal.

In this embodiment, each block can be realized with the same configuration as that of the first embodiment except for the preprocessing section 57. Therefore, in the following, the preprocessing unit 57
Will be described with reference to an embodiment shown in FIG. The three primary color signals R, G, B in the component form are subjected to matrix calculation processing in the YIQ conversion circuit 58, and the luminance signal Ys,
The color difference signals I and Q are converted. With respect to the color difference signals I and Q, the pre-filter circuit 18 removes the component that causes aliasing distortion by thinning out the sampling points. Then, the sub-sampling circuit 19 performs a sub-sampling process in which the sampling points are halved in the horizontal and vertical directions, respectively. The multiplexing unit 20 time-division multiplexes the signals obtained by thinning out the sample points to generate the image signal CR of the color difference component.
Further, the delay circuit 21 corrects the time delay generated by these signal processings to generate the image signal Y of the luminance component.

As described above, according to the present embodiment, the amount of information required for recording is extremely small for a video signal in the form of a component, and it is of high quality and high definition that does not hinder business use. A recording / reproducing device capable of reproducing an image can be realized. Further, in the present embodiment, the configuration is a form suitable for an LSI, and it is also effective for downsizing the device and making it economical.

Next, a third embodiment of the present invention will be described with reference to FIG.
It will be described with reference to the overall block diagram shown in FIG. This is suitable for a video signal of a cinema image of 24 frames per second.

The three primary color signals R, G, B consisting of 24 frames per second using a cinema image as a material are sampled by the A / D converter 56 and converted into digitized signals. Then, in the pre-processing unit 57, conversion to luminance signals, color difference I and Q signals, thinning processing of sampling points of the color difference I and Q signals (for example, thinning operation of 1/2 of the sampling points in the horizontal and vertical directions), And time-division multiplexing processing to generate a luminance component image signal Y and a color difference component image signal CR.

The high-efficiency coding unit 4 performs motion compensation inter-frame predictive coding, orthogonal transform coding by DCT (discrete cosine transform), and variable length coding by entropy coding to obtain a luminance component and a color difference component. The encoded signal Y of
Generate E and CRE.

On the other hand, the audio signal is sampled and digitized by the A / D converter 2, for example, with the characteristics of the CD (compact disc) specification. Then, the buffer memory unit 10
In No. 1, the time delay generated by the signal processing for the image signal is corrected, and the signal ADS with the delay is created.

In the multiplex section 5, the encoded signal Y
E, CRE, and audio signal ADS are time-division-multiplexed and a sync code is added to form a packet-type recording signal RD.

In the recording medium of the recording / reproducing IC memory card section 6, the recording signal RD is recorded according to the recording instruction and the reproduction signal PBD is read out according to the reproducing instruction. The memory control unit 9 receives control signals CT such as a recording instruction and a reproduction instruction, which are supplied from an external control circuit 10, and controls signals such as addresses necessary for writing and reading signals to and from the semiconductor chip memory unit 8. A control signal for controlling the input / output operation of the I / O controller 7 is generated. Then, the recording signal R
D is stored and recorded in the memory of the semiconductor chip memory unit 8 at a predetermined address. Further, the semiconductor chip memory unit 8 performs reproduction by reading from the memory of a predetermined address, and outputs a reproduction signal PBD.

The demultiplexer 11 separates the time-division-multiplexed coded signals YE and CRE of the chrominance component and the audio signal ADS based on the synchronization code.

The high-efficiency decoding unit 12 performs the opposite signal processing to that of the high-efficiency encoding unit, and decodes the image signal Y of the luminance component and the image signal CR of the color difference component, which are composed of 24 frames per second.

The post-processing unit 59 converts the number of frames from 24 frames per second to 60 frames, separates the color difference I and Q components of the image signal CR, and converts the original sampling structure signal by interpolation processing of sampling points. , Signal processing such as color modulation processing and conversion into three primary color signals R, G, B by matrix calculation are performed, and a composite type signal SV and luminance component signal SY are obtained.
And color component signal SC, and three primary color signal components SR, SG,
Make SB. Then, it is converted into an analog signal by the D / A converter 14, and a composite color TV signal VC that is the same as the current television system, a luminance signal Y and a color signal C that correspond to the S mode,
And the three primary color signals RP, GP, BP of 60 frames per second in the component form and progressive scanning are reproduced.

On the other hand, the audio signal ADS is corrected in the buffer memory unit 102 for the time delay generated in the decoding process of the image signal. Then, the D / A converter 15 converts it into an analog signal, and reproduces an audio signal synchronized with the image signal.

In this embodiment, the blocks excluding the post-processing unit 59 can be realized by the same configuration as the first and second embodiments, so that the post-processing unit 59 will be described below by the embodiment shown in FIG. Will be explained.

The frame number converter 60 converts the image signals Y and CR, which are composed of 24 frames per second, into the image signals YT and CRT, which are 60 frames per second. FIG. 14 shows an explanatory diagram of the signal processing of this conversion. Here, 24 per second
The signal of one frame (composed of scanning lines 1, 2, 3, and 4 in the figure) of the image signal of the frame, the signal of two frames of the image signal of 60 frames per second, the other frame (the scanning line in the figure) The signals of (a, b, c, d) form a signal of three frames of the image signal of 60 frames per second, and the number of frames is converted from 24 to 60.

In the separating section 46, the image signal CR of the color difference component
The color difference I and Q components which are time-division multiplexed at T are separated. Then, the oversampling circuit 47 performs oversampling processing for doubling the sampling points in the horizontal and vertical directions by inserting zero values of the sampling points. Then, the post-filter circuit 48 extracts a predetermined frequency component and decodes the color difference signals IP and QP having the same sampling structure as the luminance signal. Further, the delay circuit 49 corrects the time delay generated by this signal processing to generate the luminance signal YP.

The interlaced scan conversion unit 61 converts the interlaced scan luminance signal Y and color difference signals I and Q in the same scanning mode as the current television system by thinning the scanning lines 2: 1. FIG. 15 shows an explanatory diagram of this signal processing. That is, every 60 frames per second, a signal sequence for interlaced scanning is constituted by every other scanning line of a signal sequence for progressive scanning, and scanning conversion from sequential to interlaced scanning is performed.

In the color modulation circuit 50, the color difference signals I and Q are subjected to quadrature amplitude modulation with the color subcarrier f _SC to form a color signal C. In the adder circuit 52, the color signal C is added and multiplexed to the luminance signal Y,
A sync signal and a burst signal are added in the process circuit 53, and the composite signal S of the current television system is added.
V is generated. In the process circuit 54, a synchronization signal and a burst signal are added to the luminance signal and the color signal, respectively, and the luminance signal SY and the color signal SC corresponding to the S mode are generated.

On the other hand, the RGB conversion circuit 51 converts the signals into the three primary color signals R, G and B by a matrix calculation operation. Then, the process circuit 55 adds a synchronization signal to 60 frames per second, and sequentially scans three primary color signals SR, SG,
Generate SB.

As described above, according to the present embodiment, the amount of information required for recording is extremely small with respect to the video signal of the cinema image, and the high quality and high definition image which does not cause any trouble for business use can be reproduced. A playback device can be realized. Further, since this embodiment has a configuration suitable for LSI, it is also effective for downsizing the device and making it economical.

Next, a fourth embodiment of the present invention will be described with reference to the block diagram shown in FIG. This is suitable for a signal formed by frame completion scanning conversion in which a video signal is rearranged in the signal of one frame of progressive scanning to generate a signal sequence of interlaced scanning.

In the solid-state image pickup device section 62, for example, an FIT CCD image pickup device having an electronic shutter mechanism is used to interlace scan an image signal picked up by sequential scanning of 30 frames per second with a storage time of 1/60 seconds by frame completion scan conversion. 3 primary color signals R, G, B converted to
To generate a video signal.

In the A / D converter 56, for example, sampling is performed at a frequency that is four times as high as the color subcarrier and converted into a digitized signal. Then, in the preprocessing unit 57, conversion to luminance signals, color difference signals, and thinning processing of sampling points of the color difference I and Q signals (for example, subsampling operation for thinning the sampling points to 1/2 in the horizontal and vertical directions). Further, the time division multiplexing processing is performed to generate the image signal Y of the luminance component and the image signal CR of the color difference component.

The high-efficiency encoder 4 performs motion compensation interframe predictive coding, orthogonal transform coding by DCT (discrete cosine transform), and variable length coding by entropy coding to obtain a luminance component coded signal. A coded signal CRE of YE and color difference components is generated.

On the other hand, the audio signal is sent to the A / D converter 2 for CD
(Compact disc) Sampling is performed based on the characteristics of the specifications, etc., and converted into a digitized signal. Then, the buffer memory unit 101 corrects the time delay generated in the signal processing for the image signal, and creates an ADS with a matched delay.

The multiplex section 5 multiplexes the coded image signals YE, CRE and the audio signal ADS in a time division manner,
A recording signal RD in the form of a packet is created by adding a sync code or the like. Then, this signal is recorded in the recording / reproducing IC memory card unit 6 of the recording medium.

The recording / reproducing IC memory card section 6 has an I / O
The control unit 7, the semiconductor chip memory unit 8, and the memory control unit 9 are included. Then, in the memory control unit 9, based on the control signal CT of the recording instruction and the reproduction instruction supplied from the external control circuit 10, an address necessary for the signal writing operation and the reading operation to the semiconductor chip memory unit 8 and the like. And the control signals for the input / output operation of the I / O controller 7. Then, in accordance with the recording instruction, the recording signal RD is stored in the memory of the semiconductor chip memory unit 8 at a predetermined address to perform recording. In addition, the reproduction signal PBD is reproduced by a reproduction operation of reading a signal at a predetermined address of the semiconductor chip memory unit 8 according to a reproduction instruction.
Is output.

The demultiplexer 11 detects the sync code and encodes the coded signals YE,
The CRE and the audio signal ADS are separated from each other. Then, the high-efficiency decoding unit 12 performs signal processing for decoding in the reverse procedure of the high-efficiency encoding unit, and decodes the image signal Y of the brightness warming and the image signal CR of the color difference component.

In the post-processing unit 63, the image signal C of the color difference component
For R, color difference I and Q components are separated, and sampling points are interpolated to be converted into signals of the original sampling structure, and color difference signals I and Q having the same sampling structure as the luminance signal Y are decoded. To do. Then, color modulation processing is performed to generate a composite signal SV in which a color signal is superimposed on a luminance signal, a luminance component signal SY, and a color component signal SC. Further, the matrix conversion and the signal processing of the scanning conversion into the sequential scanning by the frame complete scanning conversion are performed to generate the three primary color signals SR, SG and SB of the sequential scanning of 60 frames per second.

The D / A converter 14 performs conversion into an analog signal, and a composite color TV signal VC similar to the current television system, a luminance signal Y and a color signal C compatible with the S mode,
And the three primary color signals RP, GP, BP of the component form, which are sequentially scanned at 60 frames per second are reproduced.

On the other hand, the audio signal ADS is corrected in the buffer memory unit 102 for the time delay generated in the decoding process of the image signal. Then, the D / A conversion unit 15 performs conversion into an analog signal and reproduces an audio signal synchronized with the image signal.

This embodiment can be realized by the same configuration as the first to third embodiments except for the block except the post-processing unit 63. Therefore, the post-processing unit will be described below by one embodiment shown in FIG. 63 will be described.

In the separating section 46, the color difference image signal CR
The components of the color differences I and Q that are time-division multiplexed are separated from each other. Then, the oversampling circuit 47 performs oversampling processing for doubling the sampling points in the horizontal and vertical directions by inserting zero values of the sampling points. Then, the post-filter circuit 48 extracts a predetermined frequency component and decodes the color difference signals I and Q having the same sampling structure as the luminance signal. Further, the delay circuit 49 corrects the image signal Y of the luminance component for the time delay generated by this signal processing.

In the color modulation circuit, the color difference signals I and Q are subjected to quadrature amplitude modulation with the color subcarrier f _SC to form the color difference signal C. The adder circuit 52 performs addition multiplexing of the color signal on the luminance signal,
In the process circuit 53, a sync signal and a burst signal are added, and the signal S in the composite form of the current television system is added.
V is generated. Further, in the process circuit 54, a synchronization signal is added to the luminance signal and a burst signal is added to the color signal to generate an S mode compatible luminance signal SY and a color signal SC.

On the other hand, the signals converted into the three primary color signals R, G, B by the matrix calculation operation in the RGB conversion circuit 51 are
The progressive scan conversion circuit 64 performs scan conversion into progressive scan by frame completion scan conversion, and generates three primary color signals RP, GP, BP of 60 frame sequential scans per second. The operation of this signal processing is shown in FIG. In the frame completion scan conversion, an interlaced scan video signal is generated by a rearrangement operation of signals of 30 sequential scans per second obtained from an image pickup system. Then, the signal of the reproduction frame of 30 sequential scans per second is reproduced by the rearrangement operation of the signal sequence of the interlaced scanning, and the signal sequence of the interpolated frame indicated by the diagonal lines is subjected to the frame interpolation processing, for example, the signal of the reproduction frame. It is generated by repeating or averaging the signals of the playback frames before and after. Then, it is converted into a signal of sequential scanning of 60 frames per second.

In the process circuit 55, a sync signal is added and the sequential scanning of 60 frames per second in the component form is performed.
The primary color signals SR, SG, SB are generated.

As described above, according to the present embodiment, the amount of information required for recording is extremely small for a video signal formed by frame completion scan conversion, and is for high-quality and high-definition business use. It is possible to realize a recording / reproducing apparatus capable of reproducing images without any trouble. In addition, this embodiment has a configuration suitable for use in an LSI, and is effective for downsizing the device and making it economical.

Next, a fifth embodiment of the present invention will be described with reference to FIG.
The block diagram shown in FIG. This is suitable for playback only such as a video package.

The reproducing IC memory card section 65 comprises a semiconductor chip ROM memory section 66, an I / O control section 7, and a memory control section 9. The semiconductor chip ROM memory section 66 has a video / audio recording signal RD according to the present invention. Are stored in the ROM. Then, in the memory control unit 9, a control signal C for reproduction instruction supplied from the external control circuit 10.
Based on T, control signals such as an address necessary for the read operation from the semiconductor chip ROM memory unit 66 and control signals for the output operation of the I / O / control unit 7 are generated. Then, the reproduction signal PBD is output by the reproduction operation of reading the signal of the predetermined address of the semiconductor chip ROM memory unit 66. In addition, recording mode information indicating the material of the recorded image,
For example, a cinema image, an image by frame completion scan conversion,
Identification of a general image or the like is input to the control circuit 10. In addition, the control circuit 10 controls the memory control unit 9 so as to generate control signals of addresses corresponding to the reproduction mode in accordance with the reproduction mode information such as the normal reproduction mode and the search reproduction mode.
To make.

The demultiplexer 11 separates the coded signal YE of the luminance component, the coded signal CRE of the color difference component, and the audio signal ADS of the images multiplexed in the time division form.

The high-efficiency decoding unit 12 performs a predetermined decoding signal process to decode the luminance component image signal Y and the color difference component image signal CR.

In the post-processing section 67, the color difference image signal C
The color difference signals I and Q having the same sampling structure as the luminance signal are decoded by the separation of the color difference I and Q components time-division multiplexed at R and the oversampling process. Then, signal processing such as color modulation, RGB conversion, and progressive scanning conversion is performed, and a composite type signal SV, a luminance component signal SY and a color component signal SC corresponding to the S mode, and 60 frames /
Second, sequential primary scanning color signals SR, SG, SB are generated. Then, the D / A conversion unit 14 performs conversion into an analog signal, and a composite color TV signal VC of the current television system, a luminance signal Y corresponding to the S mode, a color signal C, and 6 are provided.
0 frame / sec, progressive scanning 3 primary color signals RP, GP, B
Play P.

On the other hand, the audio signal ADS is corrected in the buffer memory unit 102 for the time delay generated in the decoding process of the image signal, converted into the analog signal by the D / A conversion unit 15, and the audio signal synchronized with the image signal is reproduced. Play the signal.

FIG. 20 shows an embodiment of the post-processing section 67.
The separation unit 46 separates the color difference components I and Q that are time-division multiplexed in the image signal CR of the color difference component. The sampling point restoration circuit 68 interpolates the sampling points by oversampling processing and decodes the color difference signals I and Q having the same sampling structure as the luminance signal. The delay circuit 69 corrects the time delay generated by this signal processing.

In the cinema image interlace converter 71,
For a cinema image signal of 24 frames per second,
The signal processing of the frame number conversion and the interlace scanning conversion shown in FIGS. 14 and 15 described above is performed, and the signal is converted into a signal of the same scanning form as the current television system. Further, the delay circuit 70 corrects the time delay generated by this signal processing. Then, the selection circuit 72 selects and outputs the signal of the cinema image interlace conversion unit 71 in the case of a cinema image and the signal of the delay circuit 70 in other cases according to the recording mode information.

In the color modulation circuit 50, the color difference signal is quadrature-amplitude modulated by the color subcarrier f _SC to form the color signal C. And
The adder circuit 52 adds and multiplexes the chrominance signal to the luminance signal, and the process unit 53 adds a synchronization signal and a burst signal to generate a signal SV in the composite form similar to the current television system. In the process circuit 54,
A sync signal is added to the luminance signal and a burst signal is added to the color signal to generate an S-mode compatible luminance signal SY and color signal SC.

On the other hand, the RGB conversion circuit 51 performs conversion into the three primary color signals R, G, B by matrix calculation.

In the cinema image progressive scan conversion unit 73, as shown in FIG.
By the signal processing shown in, a signal of 60 frames / second and progressive scanning is generated. Further, in the frame completion progressive scan conversion unit 74, by the rearrangement process of the interlaced scan signal sequence and the frame interpolation process shown in FIG.
Frame / sec, progressive scan signals are generated. On the other hand, the motion adaptive progressive scan conversion unit 75 generates interpolation scanning lines by motion adaptive processing and generates a signal of 60 frames / sec. Then, in the selection circuit 76, according to the recording mode information, the sequential scanning conversion unit 73 for the cinema image,
The signal of the progressive scan conversion unit 74 is selected for the image configured by the frame completion scan conversion, and the signal of the sequential scan conversion unit 75 is selected and output for the other images. Then, the process circuit 55 adds a synchronization signal to generate three primary color signals SR, SG and SB for 60 frames / sec, progressive scanning.

As described above, according to this embodiment, it is possible to realize a low-cost, compact reproducing apparatus capable of reproducing a video package medium as a high-quality and high-definition image.

In any of the embodiments, as for the high-efficiency coding technique of the image signal, a configuration is used which is a combination of motion-compensated interframe predictive coding, orthogonal transform coding by DCT (discrete cosine transform), and entropy coding. Explained in the example. However, the present invention is not limited to this, and can be configured in various forms by combining various image coding techniques such as DPCM coding, subband coding, and vector quantization. .

Further, in the present invention, by providing a function of changing the quantization characteristic, entropy encoding characteristic, etc. according to the recording mode at the time of high-efficiency encoding, the recordable time is extended several times and long. Time can be saved.

[0096]

According to the present invention, since an IC memory card composed of a semiconductor memory is used as a recording medium, it is possible to perform signal recording / reproducing operation with an immovable mechanism.
In addition, a semiconductor memory can record and reproduce signals with error-free and DC-free characteristics. Therefore, a video signal recording / reproducing apparatus that reproduces a high-quality and high-definition image by performing digital recording with excellent encoding efficiency by a high-efficiency encoding technique that has an extremely high information amount compression effect on an image signal is provided. realizable.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of an embodiment of the preprocessing unit.

FIG. 3 is a block diagram of an embodiment of the high efficiency coding unit.

FIG. 4 is an explanatory diagram of a signal form of this recording signal.

FIG. 5 is an explanatory diagram of an example of the multiplex unit.

FIG. 6 is an explanatory diagram of an example of a demultiplexing unit.

FIG. 7 is a block diagram of an embodiment of a high efficiency decoding unit.

FIG. 8 is a block diagram of an example of a post-processing unit.

FIG. 9 is a block diagram showing a configuration example of a recording / reproducing IC memory card unit.

FIG. 10 is a block diagram of a second embodiment of the present invention.

FIG. 11 is a block diagram of an embodiment of the preprocessing unit.

FIG. 12 is a block diagram of a third embodiment of the present invention.

FIG. 13 is a block diagram of an example of the post-processing unit.

FIG. 14 is an explanatory diagram of this signal processing.

FIG. 15 is an explanatory diagram of this signal processing.

FIG. 16 is a block diagram of a fourth embodiment of the present invention.

FIG. 17 is a block diagram of an example of the post-processing unit.

FIG. 18 is an explanatory diagram of signal processing of this frame completion scan conversion.

FIG. 19 is a block diagram of a fifth embodiment of the present invention.

FIG. 20 is a block diagram showing an embodiment of this post-processing unit.

[Explanation of symbols]

1, 2 ... A / D conversion unit, 3 ... Preprocessing unit, 4 ... High efficiency coding unit, 5 ... Multiplex unit, 6 ... Recording / reproducing IC memory card unit, 7 ... I / O control unit, 8 ... Semiconductor Chip memory unit, 9 ... Memory control unit, 10 ... Control circuit, 1
1 ... Demultiplexing unit, 12 ... High efficiency decoding unit, 1
3 ... Post-processing unit, 14, 15 ... D / A conversion unit, 16 ... YC
Separation unit, 17 ... Color demodulation unit, 18 ... Pre-filter circuit, 1
9 ... Sub-sampling circuit, 20 ... Multiplexing section, 21 ... Delay circuit, 22 ... Subtraction circuit, 23 ... DCT operation section, 24 ... Adaptive quantization section, 25 ... Entropy coding section, 26
... buffer section, 27 ... motion vector extraction section, 28 ... motion compensation prediction circuit section, 29 ... memory section, 30 ... addition circuit, 3
DESCRIPTION OF SYMBOLS 1 ... Inverse DCT operation part, 32 ... Inverse quantization part, 33 ... Multiplexing part, 34 ... Selection part, 35 ... Identification code addition part, 36 ... Control part, 37 ... Identification code extraction part, 38 ... Selection distribution part, 39 …
Separation unit, 40 ... Entropy decoding unit, 41 ... Inverse quantization unit, 42 ... Inverse DCT operation unit, 43 ... Addition circuit, 44 ... Memory unit, 45 ... Motion compensation prediction circuit unit, 46 ... Separation unit, 4
7 ... Oversampling circuit, 48 ... Post filter circuit, 49 ... Delay circuit, 50 ... Color modulation circuit, 51 ... RG
B conversion circuit, 52 ... Addition circuit, 53, 54, 55 ... Process circuit, 56 ... A / D conversion section, 57 ... Preprocessing section, 58
... YIQ conversion circuit, 59 ... Post-processing unit, 60 ... Frame number conversion unit, 61 ... Interlaced scan conversion unit, 62 ... Solid-state image sensor unit, 63 ... Post-processing unit, 64 ... Sequential scanning conversion circuit,
65 ... Reproduction IC memory card section, 66 ... Semiconductor chip R
OM memory section, 67 ... Post-processing section, 68 ... Sampling point restoration circuit, 69, 70 ... Delay circuit, 71 ... Cinema image interlace conversion section, 72, 76 ... Selection circuit, 73 ... Cinema image progressive scan conversion section, 74 ... Frame complete progressive scan conversion unit,
75 ... Motion adaptive progressive scan conversion unit, 8a, 8b, 8n ... Memory unit, 101, 102 ... Buffer memory unit.

Claims (4)

[Claims] 1. A video signal recording / reproducing apparatus for recording / reproducing a digitized video signal and audio signal, wherein a high efficiency encoding means for removing redundancy of the video signal and an output signal of the high efficiency encoding means are provided. Multiplexing means for time-division-multiplexing digital audio signals, storage means for storing output signals of the multiplexing means, write control for sequentially writing to the storage means by recording instruction, and read control for reading storage content by reproducing instruction Means, a separating means for separating the output signal read from the storage means into a digital audio signal and an output signal of the high efficiency encoding means, and a high decoding means for decoding the output signal of the high efficiency encoding means obtained by the separating means into a video signal. A video signal recording / reproducing apparatus comprising an efficiency decoding means. 2. The high-efficiency coding means for the digitized video signal according to claim 1, wherein the motion-compensated interframe predictive coding, orthogonal transform coding by discrete cosine transform,
A video signal recording / reproducing apparatus having a combination of entropy coding. 3. A video signal recording / reproducing apparatus according to claim 1 or 2, wherein the digitized video signal is a video signal in which the number of frames of 24 frames per second is 24 frames per second. 4. The first and second fields of interlaced scanning by rearranging a signal sequence of one frame of progressive scanning by frame completion scanning conversion with the digitized video signal according to claim 1 or 2. The video signal recording / reproducing apparatus in which the signal sequence of is generated.