JPH0622252B2 - Gold plating method for electronic components for semiconductor integrated circuits - Google Patents

Gold plating method for electronic components for semiconductor integrated circuits

Info

Publication number
JPH0622252B2
JPH0622252B2 JP6581888A JP6581888A JPH0622252B2 JP H0622252 B2 JPH0622252 B2 JP H0622252B2 JP 6581888 A JP6581888 A JP 6581888A JP 6581888 A JP6581888 A JP 6581888A JP H0622252 B2 JPH0622252 B2 JP H0622252B2
Authority
JP
Japan
Prior art keywords
gold
plating
gold plating
thallium
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP6581888A
Other languages
Japanese (ja)
Other versions
JPH01239856A (en
Inventor
隆裕 山田
一雄 有村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP6581888A priority Critical patent/JPH0622252B2/en
Publication of JPH01239856A publication Critical patent/JPH01239856A/en
Publication of JPH0622252B2 publication Critical patent/JPH0622252B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はプラスチックパッケージやセラミックパッケー
ジ等の半導体集積回路用電子部品の所要部分に金めっき
を施す方法に関するものである。
Description: TECHNICAL FIELD The present invention relates to a method for applying gold plating to required parts of electronic components for semiconductor integrated circuits such as plastic packages and ceramic packages.

(従来の技術及び発明が解決しようとする課題) プラスチックパッケージなどの半導体集積回路用電子部
品には高い信頼性が要求されるため従来から金めっきが
施されているが、1979年の金価格の高騰により、そ
の必要な部分だけに高速度で金めっきを行い生産性を向
上させることが望まれている。
(Problems to be Solved by Conventional Techniques and Inventions) Electronic components for semiconductor integrated circuits, such as plastic packages, have been conventionally plated with gold because high reliability is required. Due to the sharp rise, it is desired to improve the productivity by performing gold plating on only the necessary portions at a high speed.

従来、半導体集積回路用電子部品への金めっきはタリウ
ム等の添加剤を10mg/以上含むめっき浴を使用して
直流法でめっきされている。この方法でめっき速度を速
めて生産性を向上させるため、高い電流密度(例えば1
A/dm以上)でめっき作業を行おうとすると、めっ
き皮膜中に添加剤であるタリウムが多量(100ppm
以上)に共析してくる。しかしながら、この多量のタリ
ウムが共析すると、金めっき表面でタリウムの酸化物を
形成し、後工程であるワイヤーボンディング工程におい
てワイヤーと金めっき皮膜とが良好に接合しない、耐熱
性試験時におけるタリウムの拡散移動による接合力等の
不良を生じる。
Conventionally, gold plating on electronic parts for semiconductor integrated circuits is performed by a direct current method using a plating bath containing an additive such as thallium at 10 mg / or more. In this method, in order to increase the plating rate and improve the productivity, a high current density (for example, 1
When trying to perform plating work with A / dm 2 or more), a large amount of thallium (100 ppm) as an additive is present in the plating film.
Above). However, when this large amount of thallium is co-deposited, an oxide of thallium is formed on the gold-plated surface, and the wire and the gold-plated film are not well bonded in the wire bonding step which is a post-process. Defects such as bonding force due to diffusion movement occur.

したがって、現在ではタリウムの共析量を少なくするた
め、直流法により0.25A/dm程度の低電流密度
でめっき作業をしている。その結果、めっきに長時間を
要し、めっきの生産性は低いものとなっている。
Therefore, in order to reduce the co-deposition amount of thallium, plating work is currently performed by a direct current method at a low current density of about 0.25 A / dm 2 . As a result, it takes a long time for plating, and the productivity of plating is low.

一方、タリウム等の添加剤を含有させないめっき浴を用
いて直流法で金めっきを施した場合は、金めっき皮膜は
無光沢で粗雑なものしか得られず、半導体集積回路用の
電子部品用金めっきとして満足できる特性を有しない。
On the other hand, when gold plating is performed by the direct current method using a plating bath that does not contain additives such as thallium, the gold plating film is only matte and rough, and the gold for electronic components for semiconductor integrated circuits is obtained. It does not have satisfactory characteristics as plating.

(課題を解決するための手段) 本発明は上記のような課題を解決した半導体集積回路用
電子部品の金めっき法を提供するもので、金めっき皮膜
中のタリウム共析量を100ppm以下に減少させ、ワ
イヤーボンディング性等の特性が優れた半導体集積回路
用電子部品の金めっき皮膜を高速度でえることを可能と
するものであり、すなわち、クエン酸又はクエン酸塩を
含み、かつタリウムを1mg/以下含有する金シアン
化物めっき浴を用い、定電流パルス法によって電子部品
に金めっきを施すことを特徴とする半導体集積回路用電
子部品の金めっき法である。
(Means for Solving the Problems) The present invention provides a gold plating method for electronic components for semiconductor integrated circuits, which solves the above problems, and reduces the amount of thallium eutectoid in the gold plating film to 100 ppm or less. It is possible to obtain a gold plating film of an electronic component for a semiconductor integrated circuit having excellent characteristics such as wire bonding property at a high speed, that is, containing citric acid or citrate and containing 1 mg of thallium. / A gold plating method for an electronic component for a semiconductor integrated circuit, characterized in that an electronic component is gold-plated by a constant current pulse method using a gold cyanide plating bath contained below.

本発明においては、クエン酸又はクエン酸塩をめっき浴
中に含有せしめているが、これによって金めっき浴の適
正phが安定的に保持できるものであり、通常30〜8
0g/含有せしめられている。金シアン化物として
は、シアン化第一金カリウム、シアン化第一金アンモニ
ウムなどが用いられ、そのめっき中の含有量は5〜50
g/程度である。
In the present invention, citric acid or a citrate salt is contained in the plating bath, which allows the proper pH of the gold plating bath to be stably maintained, and is usually 30 to 8
0 g / content is included. As the gold cyanide, potassium gold (I) cyanide, ammonium (I) gold cyanide, etc. are used, and the content thereof in the plating is 5 to 50.
g / degree.

ところで従来、金めっき浴中にはタリウムを含有せしめ
ているが、この理由はタリウムが金めっき表面で吸着と
脱着を繰り返しながら電析した金めっき粒子を適正な大
きさの結晶に調整する作用があるためである。それ故、
高い電流密度(1A/dm以上)で高い生産性のめっ
き作業を行おうとすると、金めっき表面におけるタリウ
ムの脱着が阻害され、結果的にその共析量が増加し、不
良な金めっき皮膜層が形成される。
By the way, conventionally, thallium is contained in the gold plating bath. The reason for this is that thallium has the function of adjusting the gold-plated particles electrodeposited while repeating adsorption and desorption on the gold-plating surface into crystals of an appropriate size. Because there is. Therefore,
When attempting to perform highly productive plating work at a high current density (1 A / dm 2 or more), desorption of thallium on the gold plating surface is hindered, resulting in an increase in the amount of eutectoid and a defective gold plating film layer. Is formed.

そこで、本発明では定電流パルス法を採用する。Therefore, in the present invention, the constant current pulse method is adopted.

この方法は、間欠的に電流を流すめっき法であり、電流
のオン・オフが定期的に繰り返されるものである。本発
明においては、定電流パルス法を採用したことにより、
前記電流がオフになる時間、すなわち電流が流れない時
間にタリウムの脱着が促進されるため、金めっき皮膜中
のタリウム共析量が減少するものと考えられる。本発明
にしたがってめっき浴中のタリウム添加量を従来法の1
/10(1ppm)に低減し、パルス電流密度(電流が
オンの時に流れる電流の電流密度)を高くして(2A/
dm以上)金めっきを施した場合、従来法であるタリ
ウムを10mg/以上含むめっき浴を使用する低電流
密度の直流法によって作製した製品と同等の特性を有す
る金めっき皮膜を得ることが可能となった。
This method is a plating method in which an electric current is intermittently applied, and ON / OFF of the electric current is periodically repeated. In the present invention, by adopting the constant current pulse method,
It is considered that the amount of thallium co-deposited in the gold plating film decreases because the desorption of thallium is promoted during the time when the current is turned off, that is, when the current does not flow. According to the present invention, the amount of thallium added to the plating bath is set to 1 of the conventional method.
/ 10 (1 ppm) and increase the pulse current density (current density of the current that flows when the current is on) (2 A /
dm 2 or more) When gold plating is applied, it is possible to obtain a gold plating film having the same characteristics as a product manufactured by a DC method with a low current density using a conventional plating bath containing 10 mg / thickness of thallium. Became.

一方、タリウムを含まないめっき浴を使用した場合、従
来の直流法では粗雑なめっき皮膜となってしまう。しか
し、本発明における定電流パルスめっき法を採用してパ
ルス電流密度を非常に高く(10A/dm以上)設定
してめっき作業を行うと、瞬間的に多くの金の結晶核が
高範囲に生成するものと考えられ、その結果、緻密で光
沢のある金めっき皮膜が得られるものである。
On the other hand, when a plating bath containing no thallium is used, the conventional DC method results in a rough plating film. However, when the constant current pulse plating method according to the present invention is adopted and the pulse current density is set to be extremely high (10 A / dm 2 or more) and plating work is performed, a large number of gold crystal nuclei are momentarily in a high range. It is thought that the gold plating film is formed, and as a result, a dense and glossy gold plating film is obtained.

本発明における定電流パルスの使用条件としては、タ
リウム不含のめっき浴の場合、パルス電流密度10〜1
00A/dm、パルスオン時間0.1〜10mse
c.平均電流密度0.1〜0.5A/dm、タリウ
ム含有量1mg/の場合、パルス電流密度2〜5A/
dm、パルスオン時間0.1〜10msec.平均電
流密度0.1〜1A/dmが好ましい。
The conditions for using the constant current pulse in the present invention include pulse current density of 10 to 1 in the case of a thallium-free plating bath.
00A / dm 2 , pulse on time 0.1 to 10 mse
c. When the average current density is 0.1 to 0.5 A / dm 2 and the thallium content is 1 mg /, the pulse current density is 2 to 5 A /
dm 2 , pulse on time 0.1 to 10 msec. The average current density is preferably 0.1 to 1 A / dm 2 .

本発明において使用される金めっき浴はクエン酸又はク
エン酸塩含有浴であり、例えば(A)クエン酸50g/
、クエン酸ナトリウム(あるいはクエン酸カリウム、
あるいはクエン酸アンモニウム)50g/、さらにシ
アン化第一金カリウム10〜50g/を含有したもの
を基本浴とし、また、例えば(B)クエン酸30g/
、クエン酸ナトリウム(あるいはクエン酸カリウム、
あるいはクエン酸アンモニウム)50g/、リン酸二
水素カリウム140g/、さらにシアン化第一金カリ
ウム10〜50g/を基本浴としたものにタリウムを
0〜1mg/添加したものである。これらのめっき浴
のPHは3.7〜4.5であり、浴温50〜70℃でめ
っき作業を行うものである。なお、リン酸二水素カリウ
ム(リン酸二水素塩)は、上記クエン酸との組み合わせ
で本発明に係るめっき浴のPH変動を抑制する緩衝剤の
働きを奏するものである。ところで、従来の直流法で作
製した金めっき皮膜はその膜厚が薄い(2μm以下)場
合は、それに小孔が多数存在し、その孔を通して下地の
ニッケルが金めっき表面に拡散し酸化物を形成する結
果、ダイボンディング工程においてICチップと金めっ
きとの融着を阻害する問題がある。このため、現在では
膜厚を3〜5μmに厚くしてニッケルの拡散を防止して
上記問題に対処している。
The gold plating bath used in the present invention is a citric acid- or citrate-containing bath, for example (A) citric acid 50 g /
, Sodium citrate (or potassium citrate,
Alternatively, ammonium citrate) 50 g /, and further, potassium primary cyanide 10 to 50 g / is used as a basic bath, and (B) citric acid 30 g /
, Sodium citrate (or potassium citrate,
Alternatively, ammonium citrate) 50 g /, potassium dihydrogen phosphate 140 g /, and potassium primary gold cyanide 10-50 g / are used as the basic bath, and thallium 0-1 mg / is added. The pH of these plating baths is 3.7 to 4.5, and the plating operation is performed at a bath temperature of 50 to 70 ° C. In addition, potassium dihydrogen phosphate (dihydrogen phosphate salt) plays a role of a buffering agent for suppressing the PH fluctuation of the plating bath according to the present invention in combination with the above citric acid. By the way, when the thickness of the gold plating film produced by the conventional direct current method is thin (2 μm or less), a large number of small holes are present in the gold plating film, and the underlying nickel diffuses on the gold plating surface to form an oxide. As a result, there is a problem that the fusion of the IC chip and the gold plating is obstructed in the die bonding process. Therefore, at present, the film thickness is increased to 3 to 5 μm to prevent nickel from diffusing and the above problem is addressed.

本発明の定電流パルス法はこの孔の数を減少させるのに
有効なめっき法であり、従来の約半分の膜厚に薄くして
も同等の機能を有する金めっき皮膜を得ることができ半
導体集積回路用電子部品製造のコストダウンに大きく寄
与するものである。
The constant-current pulse method of the present invention is an effective plating method for reducing the number of holes, and even if the thickness is reduced to about half that of the conventional method, a gold plating film having the same function can be obtained. This greatly contributes to the cost reduction of manufacturing electronic components for integrated circuits.

(実施例) 実施例1 タリウム含有量0mg/のめっき浴 クエン酸 50g/ クエン酸ナトリウム 50g/ シアン化第一金カリウム 50g/ 上記の金めっき浴を使用して攪拌しながら浴温約60℃
で、セラミックパッケージ基板に、以下のパルス条件に
より金めっきを行った。
(Example) Example 1 Plating bath having a thallium content of 0 mg / citric acid 50 g / sodium citrate 50 g / potassium primary potassium cyanide 50 g / bath temperature of about 60 ° C while stirring using the above gold plating bath
Then, gold plating was performed on the ceramic package substrate under the following pulse conditions.

パルス条件 パルス電流密度 10A/dm パルスオン時間 0.1ms パルスオフ時間 1.9ms 上記のめっき浴及び条件で金めっき作業を行ったとこ
ろ、金めっき層にタリウムの共析がなく、しかも半導体
集積回路用電子部品用金めっきとして必要な優れたワイ
ヤーボンディング性、ダイボンディング性及び耐食性を
有する金めっき皮膜が得られた。
Pulse conditions Pulse current density 10 A / dm 2 Pulse on time 0.1 ms Pulse off time 1.9 ms When gold plating work was performed under the above plating bath and conditions, there was no co-deposition of thallium in the gold plating layer and for semiconductor integrated circuits. A gold plating film having excellent wire bonding properties, die bonding properties and corrosion resistance required for gold plating for electronic parts was obtained.

なお、定電流パルス法における平均電流密度は、直流法
の電流密度に相当し、実施例1の場合0.5A/dm
となり、従来の直流法の一般的電流密度0.25A/d
に比較し、2倍の電流密度、即ち2倍の速度でめっ
き作業が行われるものである。そして、本発明における
平均電流密度は、めっきの生産性及び皮膜特性の観点か
ら、0.1〜0.5A/dmが好ましい。
The average current density in the constant current pulse method corresponds to the current density in the direct current method, and in the case of Example 1, 0.5 A / dm 2
Therefore, the general current density of the conventional DC method is 0.25 A / d.
Compared to m 2 , the plating operation is performed at twice the current density, that is, at twice the speed. The average current density in the present invention is preferably 0.1 to 0.5 A / dm 2 from the viewpoint of plating productivity and film characteristics.

実施例2: タリウム含有量1mg/のめっき浴 クエン酸 30g/ クエン酸ナトリウム 50g/ リン酸二水素カリウム 140g/ シアン化第一金カリウム 50g/ 上記の金めっき浴を使用して浴温約60℃で、セラミッ
クパッケージ基板に、以下のパルス条件により金めっき
を行った。
Example 2: Plating bath with thallium content of 1 mg / citric acid 30 g / sodium citrate 50 g / potassium dihydrogen phosphate 140 g / potassium dihydrogen cyanide 50 g / bath temperature of about 60 ° C. using the above gold plating bath Then, gold plating was performed on the ceramic package substrate under the following pulse conditions.

パルス条件 パルス電流密度 2A/dm パルスオン時間 0.1ms パルスオフ時間 0.1ms このパルス条件下では平均電流密度が1A/dmとな
り、直流法の通常電流密度0.25A/dmと比較し
て4倍の電流密度、即ち4倍の速度でめっき作業が可能
となった。なお、実施例2の条件で作製した金めっき皮
膜中へのタリウム共析量は約70ppmであり、これは
ワイヤーボンディング不良を生じ始めるといわれている
タリウム共析量100ppmよりも低いものであって、
良好なワイヤーボンデイング性を有している。
Pulse condition Pulse current density 2A / dm 2 Pulse on time 0.1ms Pulse off time 0.1ms Under this pulse condition, the average current density is 1A / dm 2 , which is compared with the normal current density of 0.25A / dm 2 in the DC method. It became possible to perform plating work at a current density four times higher, that is, at a speed four times faster. The amount of thallium eutectoid in the gold plating film produced under the conditions of Example 2 was about 70 ppm, which is lower than the amount of thallium eutectoid, which is said to start causing wire bonding defects. ,
Has good wire bonding properties.

(発明の効果) 上記のとおり、クエン酸又はクエン酸塩を含み、かつタ
リウム1mg/以下含有する金シアン化物めっき浴を
用い、定電流パルス法によって半導体集積回路用電子部
品に金めっきを施す本発明の金めっき法によれば、タリ
ウム含有量の極めて少ない金めっき浴を用いてワイヤー
ボンディング性等の特性が優れた電子部品の金めっき皮
膜を高速度(高生産性)で得ることができる。
(Effects of the Invention) As described above, a gold cyanide plating bath containing citric acid or a citrate and containing 1 mg / l or less of thallium is used to perform gold plating on electronic components for semiconductor integrated circuits by a constant current pulse method. According to the gold plating method of the invention, a gold plating film of an electronic component having excellent characteristics such as wire bondability can be obtained at high speed (high productivity) using a gold plating bath having an extremely low thallium content.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】クエン酸又はクエン酸塩を含み、かつタリ
ウムを1mg/以下含有する金シアン化物めっき浴を
用い、定電流パルス法によって電子部品に金めっきを施
すことを特徴とする半導体集積回路用電子部品の金めっ
き法。
1. A semiconductor integrated circuit characterized in that an electronic component is gold-plated by a constant current pulse method using a gold cyanide plating bath containing citric acid or a citrate and containing 1 mg / l of thallium. Plating of electronic components for automobiles.
【請求項2】金シアン化物めっき浴が、タリウムを実質
的に含有しないものである請求項1に記載の半導体集積
回路用電子部品の金めっき法。
2. The gold plating method for electronic components for semiconductor integrated circuits according to claim 1, wherein the gold cyanide plating bath is substantially free of thallium.
【請求項3】金シアン化物めっき浴が、リン酸二水素塩
を含有している請求項1又は請求項2に記載の半導体集
積回路用電子部品の金めっき法。
3. The gold plating method for an electronic component for a semiconductor integrated circuit according to claim 1, wherein the gold cyanide plating bath contains a dihydrogen phosphate salt.
JP6581888A 1988-03-22 1988-03-22 Gold plating method for electronic components for semiconductor integrated circuits Expired - Lifetime JPH0622252B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6581888A JPH0622252B2 (en) 1988-03-22 1988-03-22 Gold plating method for electronic components for semiconductor integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6581888A JPH0622252B2 (en) 1988-03-22 1988-03-22 Gold plating method for electronic components for semiconductor integrated circuits

Publications (2)

Publication Number Publication Date
JPH01239856A JPH01239856A (en) 1989-09-25
JPH0622252B2 true JPH0622252B2 (en) 1994-03-23

Family

ID=13297988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6581888A Expired - Lifetime JPH0622252B2 (en) 1988-03-22 1988-03-22 Gold plating method for electronic components for semiconductor integrated circuits

Country Status (1)

Country Link
JP (1) JPH0622252B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3341763B2 (en) 2000-04-27 2002-11-05 住友電気工業株式会社 Method for manufacturing compound semiconductor device and apparatus for manufacturing compound semiconductor device
CN111819310B (en) * 2018-03-07 2022-11-25 住友电气工业株式会社 Coating film and coated member

Also Published As

Publication number Publication date
JPH01239856A (en) 1989-09-25

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