JPH0622227A - Defect correction device for solid-state image pickup element - Google Patents

Abstract

PURPOSE:To provide the defect correction device for a solid-state image pickup element which is able to cope with a defect change attended with electrostatic breakdown or a secular change and does not require circulation form needing a solid-state image pickup element and defect data in pairs. CONSTITUTION:A subtractor 8 takes a difference between a CCD output (i) of a CCD image pickup element 1 and a CCD output (l) resulting from delaying the output (i) by a period equivalent to one picture element pitch at a 1-bit delay circuit 6, the difference signal (m) is triggered by detection levels Va, Vb to obtain defect object pulses (p), (q), a subtractor 17 takes a difference between the CCD output (i) and a 1H delay output (r) resulting from delaying the output (i) by a 1H delay circuit 18, the difference signal (s) is detected by detection levels Vc, Vd to obtain defect object pulses (t), (u) and a defect picture element is detected by ANDing the defect candidate pulses (p), (q) and the defect candidate pulses (t), (u) at NAND circuits 15, 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect correction device for a solid-state image pickup device.

[0002]

2. Description of the Related Art In a solid-state image pickup device formed of a semiconductor such as CCD, a defective pixel whose sensitivity is lowered due to a local crystal defect of the semiconductor may occur. In such a case,
It is known that the image quality is deteriorated due to the defective pixel. In order to correct the image quality deterioration due to this defective pixel by signal processing, conventionally, the defect data of the defective pixel included in the solid-state imaging device is manufactured in the all-white or all-black imaging state. Detected in a semiconductor factory and stored in ROM in advance, specify a defective pixel based on the ROM data during normal image pickup, and replace the image pickup output of the defective pixel with the image pickup output one pixel before, for example. The defect was corrected by.

[0003]

However, in the conventional defect correcting apparatus, the defect correction is performed by using the defect data stored in the ROM at the manufacturing stage of the solid-state image pickup device, so that the local crystal of the semiconductor is not corrected. Although it is possible to deal with pixel defects due to defects, it is not possible to deal with electrostatic damage when the solid-state image sensor is built into the video camera and defect change due to aging after mounting on the video camera, and solid-state imaging There has been a problem that a distribution form in which an element and defect data are paired is indispensable. Therefore, an object of the present invention is to provide a defect correction apparatus for a solid-state image sensor that can cope with a change in defects due to electrostatic breakdown or a change over time and that does not require a distribution mode in which the solid-state image sensor and defect data are paired. And

[0004]

A defect correction apparatus for a solid-state image pickup device according to the present invention comprises a first delay means for delaying the image pickup output of the solid-state image pickup device by a period corresponding to one pixel pitch.
First subtraction means for performing subtraction between the input of the first delay means and the output thereof, first defect detection means for detecting defective pixels based on the subtraction output of the first subtraction means, and solid-state imaging Second delay means for delaying the image pickup output of the element by one horizontal scanning period, second subtraction means for subtracting the input of the second delay means and its output, and the subtraction of the second subtraction means Second defect detection means for detecting a defective pixel based on the output, storage means for storing and holding defect data relating to the defective pixel detected by both the first and second defect detection means, and the storage means. A correction unit that corrects the imaging output of the defective pixel based on the retained defect data is provided.

[0005]

By delaying the image pickup output of the solid-state image pickup device by a period corresponding to one pixel pitch, the signals of the pixels adjacent in the horizontal direction are synchronized, and the image pickup output of the solid-state image pickup device is horizontally scanned. By delaying by a period, signals of pixels adjacent in the vertical direction are synchronized. Then, defective pixels are detected by comparing the signal levels between the pixels that are synchronized in the horizontal and vertical directions, and defective data regarding the defective pixels is stored and held in a RAM or the like as address data. At the time of normal image pickup, defect correction is performed based on address data stored and held in the RAM or the like to improve image quality deterioration due to pixel defects.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the solid-state imaging device according to the present invention uses, for example, a monochrome CCD imaging device 1 as a solid-state imaging device. The CCD image pickup device 1 adopts, for example, an interline transfer system as a charge transfer system. C
The image pickup output (CCD output) of the CD image pickup device 1 includes a reset section, a precharge section, and a data section.
It is supplied to the S (correlated double sampling) circuit 2 to reduce reset noise and the like.

The CDS circuit 2 samples / holds the precharge portion of the CCD output and delays it by a period corresponding to one pixel pitch S / H (sample / hold)
The circuits 201 to 203 and the data part of the CCD output are sampled / held, and this is synchronized with the precharge part S
/ H circuits 204 and 205. S / H circuit 2
01, 203 and 205 perform the sampling operation by the sampling pulse SHP, and the S / H circuits 202 and 204 perform the sampling operation by the sampling pulse SHD.

Since the same noise component is superimposed on the synchronized precharge section and data section, each S / H output of the S / H circuits 203 and 205 is subjected to subtraction processing by the subtractor 3. By doing so, the noise component is canceled and only the signal component is extracted and derived as an imaging output (CDS output) via the AGC (automatic gain control) circuit 4. The same subtraction output as the subtraction output of the subtracter 3 is also obtained by the subtracter 5 that subtracts the S / H outputs of the S / H circuits 203 and 205.

The respective S / H outputs of the S / H circuits 203 and 205 are further input to the subtractor 7 via the 1-bit delay circuit 6. That is, the S / H output of the S / H circuit 203 becomes the subtraction input of the subtractor 7 via the S / H circuits 601, 602, and the S / H output of the S / H circuit 205 is the S / H circuit 60.
It becomes a subtracted input of the subtractor 7 via 3,604. Thus, as the subtraction output of the subtractor 7, an imaging output delayed by 1 bit, that is, a period corresponding to one pixel pitch, is derived from the subtraction output of the subtractor 5, and the pixel information of adjacent pixels in the horizontal direction is synchronized. Is done.

The subtraction output of the subtractor 5 becomes the subtracted input of the subtractor 8, and the subtraction output of the subtractor 7 becomes the subtraction input of the subtractor 8. That is, the subtractor 8 performs the subtraction process between the image pickup outputs of the two pixels that are adjacent in the horizontal direction and are synchronized with each other. The subtracted output of the subtractor 8 is a Schmitt circuit 9 or 1 having positive and negative detection levels Va and Vb.
Supplied to zero. The Schmitt circuits 9 and 10 function as a level comparison circuit, generate a detection output when the subtraction output of the subtracter 8 exceeds the positive and negative detection levels Va and Vb, and supply it to the latch circuits 11 and 12. The positive and negative detection levels Va and Vb are variable by adjusting the variable resistors VR1 and VR2.

The latch circuits 11 and 12 latch the detection outputs of the Schmitt circuits 9 and 10 for a period corresponding to one pixel pitch. The outputs of the latch circuits 11 and 12 are AN
It becomes one input for each of the D circuits 13 and 14. Further, the respective inputs of the latch circuits 11 and 12 become the respective other inputs of the AND circuits 13 and 14. The outputs of the AND circuits 13 and 14 are NAND
It becomes one input of each of the circuits 15 and 16.

On the other hand, the subtraction output of the subtractor 3 is the subtractor 17
And the 1H delay circuit 18 delays it by one horizontal scanning period (1H). As a result, the pixel information adjacent in the vertical direction is synchronized. 1
The H-delayed output becomes the subtraction input of the subtractor 17 after the noise is reduced again by the CDS circuit 19. The subtraction output of the subtractor 17 is supplied to Schmitt circuits 20 and 21 having positive and negative detection levels Vc and Vd. Schmitt circuit 20,
21 serves as a level comparison circuit, and the subtractor 1
When the subtraction output of 7 exceeds the positive and negative detection levels Vc and Vd, a detection output is generated and supplied to the latch circuits 22 and 23. The positive and negative detection levels Vc and Vd are variable by adjusting the variable resistors VR3 and VR4.

The latch circuits 22 and 23 latch the respective detection outputs of the Schmitt circuits 20 and 21 for a period corresponding to one pixel pitch. Each output of the latch circuits 22 and 23 is N
It becomes the other inputs of the AND circuits 15 and 16. The outputs of the NAND circuits 15 and 16 are supplied to the address counter 24 as defect information. The address counter 24 is a CCD
The counting operation is performed in synchronization with the horizontal scanning of the image sensor 1,
The count value at the time when the defect information is supplied from the NAND circuit 15 or 16 is supplied to the address conversion circuit 25.

The address conversion circuit 25 specifies the position of the defective pixel based on the count value supplied from the address counter 24 and converts it into address data indicating the position. This address data is stored and held in the RAM 26. The address indicating the position of the defective pixel may be either an absolute address or a relative address. The address data regarding the defective pixel stored and held in the RAM 26 is used for defect correction during normal imaging.

That is, in the correction pulse generation circuit 27, the defective pixel is specified based on the address data stored in the RAM 26, and the defect correction pulse is generated in each field at a timing corresponding to the defective pixel. The defect correction pulses are sampling pulses SHP and SHD.
Is supplied to a sampling pulse generation circuit 28 that generates When the defect correction pulse is supplied, the sampling pulse generation circuit 28 stops the generation of the sampling pulse SHP one pixel before the defective pixel. As a result, the CCD output (imaging output) for the defective pixel is changed to the CC one pixel before.
Defect correction is performed by pre-interpolation that replaces the D output.

Next, defect detection and defect correction in the defect correction device having the above-mentioned structure will be described with reference to the timing waveform charts of FIGS. Note that the waveforms (a) to (u) in FIGS. 2 to 4 correspond to the portions (a) to (u) in FIG.
Represents the waveform of. First, the operation at the time of defect detection will be described. The CCD output (a) is composed of a reset section, a precharge section and a data section, and the precharge section is the S / H circuit 201, as is clear from FIG. In S / H circuit 204, the data portion is sampled / held by the sampling pulse SHD (c) while being sampled / held by the sampling pulse SHP (b).

The S / H output (d) of the S / H circuit 201 is
The S / H circuit 202 samples / holds by the sampling pulse SHD (c) and outputs the S / H (e)
Is the sampling pulse SHP in the S / H circuit 203.
Sampled / held by (b). On the other hand, S /
The S / H output (g) of the H circuit 204 is the S / H circuit 205.
At the sampling pulse SHP (b)
To be held. As a result, the precharge part and the data part of the CCD output (a) are synchronized. And the subtractor 5
At S / H output (h) of the S / H circuit 25,
By subtracting the S / H output (f) of the H circuit 23, the CCD output from which the noise component is removed is obtained as the subtraction output (i) of the subtractor 5.

The S / H output (f) of the S / H circuit 203 is output to the sampling pulse SHD by the S / H circuit 601.
(C) is sampled / held, and the S / H output is further sampled by the S / H circuit 602 to generate a sampling pulse SH.
Sampled / held by P (b). On the other hand, S
The S / H output (h) of the / H circuit 205 is the S / H circuit 603.
At the sampling pulse SHD (c)
It is held and its S / H output is further S / H circuit 60.
At 4, the sampling / holding is performed by the sampling pulse SHP (b). Then, in the subtractor 7, S / H
By subtracting the S / H output (j) of the S / H circuit 602 from the S / H output (k) of the circuit 604, the subtraction output (i) of the subtractor 5 is obtained as the subtraction output (l) of the subtractor 6. ), A CCD output delayed by a period corresponding to one pixel pitch is obtained.

Subsequently, in the subtractor 8, the subtraction output (l) of the subtractor 7 is subtracted from the subtraction output (i) of the subtractor 5,
That is, by taking the difference between the signals of two pixels that are adjacent in the horizontal direction, the subtraction output (m) of the subtracter 8 is positive in units of 2 bits (pixels) when a pixel has a white spot defect. When there is a black spot defect, negative and positive differential waveforms are obtained. And the Schmitt circuits 9 and 10
At, the defect candidate pulses (n) and (o) are obtained by triggering the differential waveform output (m) at certain detection levels Va and Vb. These defect candidate pulses (n) and (o) are latched by the latch circuits 11 and 12, and then ANDed with the other defect candidate pulses (o) and (n) by the AND circuits 13 and 14. , White spot defect candidate pulse (p) or black spot defect candidate pulse (q).

Further, in the subtractor 17, the 1H delay output (r) obtained by delaying the subtraction output (i) of the subtractor 3 by the 1H delay circuit 18 for 1H period is subtracted, that is, adjacent in the vertical direction. The subtraction output (s) is obtained by taking the difference between the respective signals of the two pixels. Based on this subtraction output (s), the Schmitt circuits 20 and 21 detect at certain detection levels Vc and Vd, and the latch circuits 22 and 23 latch for a period corresponding to one pixel pitch. As a result, the defect is detected independently from the difference signal from the pixel information of one line below on the screen, and the latch circuit 2
2 and 23, the defect candidate pulse (t),
(U) is obtained.

In the NAND circuits 15 and 16, the defect candidate pulses (p) and (q) which are the outputs of the AND circuits 13 and 14 and the defect candidate pulses (t) which are the outputs of the latch circuits 22 and 23, respectively. By taking the logical product with (u), the white spot defect pulse (v) or the black spot defect pulse (w) can be obtained. In the address counter 24,
The position of the defective pixel is specified by address counting the white spot defect pulse (v) or the black spot defect pulse (w). Then, the count value of the address counter 24 is converted into address data by the address conversion circuit 25, and RA
Store in M26.

Next, to explain the operation at the time of defect correction, first, in the correction pulse generation circuit 27, the RAM 26 is used.
A defect correction pulse is generated based on the address data stored and stored in the sampling pulse generation circuit 28. As a result, the sampling pulse SHP one pixel before the defective pixel is blanked. As a result, the CCD output (imaging output) of the defective pixel is replaced with the CCD output of the previous pixel, and the defect correction is performed.

In other words, the above-described defect detection processing is S
Taking the difference between the CCD output (i) after DC and the CCD output (l) delayed by a period corresponding to one pixel pitch,
The difference signal (m) is triggered by detection levels Va and Vb respectively to obtain defect candidate pulses (p) and (q), and the CCD output (i) after SDC and its 1H delay output (r) are obtained. And the difference signal (s) is detected at a certain detection level Vc, Vd to detect a defect candidate pulse (t),
The defective pixel is detected by obtaining (u) and taking the logical product of the defect candidate pulses (p) and (q) and the defect candidate pulses (t) and (u). According to this, as shown in FIG. 5, with respect to a certain pixel B, the pixels A before and after it,
Since the defective pixel B can be detected by the correlation between C and the lower pixel D on the screen in the three directions A, C, and D, the defective pixel detection accuracy can be improved.

That is, assuming that an image is projected as indicated by the diagonal lines in FIG. 5, if a defective pixel is detected only by the correlation of the pixels before and after, the pixel B corresponding to the edge image is mistaken as a defective pixel. Although it may be detected, the defective pixel is also detected by the correlation with the lower pixel on the screen, so that erroneous detection due to the edge image can be prevented, and the detection accuracy can be improved.

The address conversion circuit 24 shown in FIG.
In the subsequent stage, when the address data are compared on the time axis (every frame) and they match, it is determined that the detected pixel is indeed a defective pixel, and at that time, the address data for the defective pixel is stored in the RAM 25. By providing a determination circuit (not shown) for storing, for example, in the case of a moving image,
Since the edge image has a low probability of resting on the same pixel, erroneous detection due to the edge image can be more accurately avoided.

In the above embodiment, the case where the present invention is applied to a solid-state image pickup device using a monochrome CCD image pickup device as a solid-state image pickup device has been described.
A solid-state image pickup device using a CD image pickup element has a color separation S / H.
After that, the same processing as in the case of black and white is performed on the signal after color separation, so that the same can be realized. However, when the color filter is, for example, the complementary color checkered system, the color coding is so-called horizontal 2-repetition. Therefore, the delay circuit 6 delays the CCD output by a period corresponding to twice the pixel pitch, and further the delay circuit 18 Then, it is necessary to delay the CCD output by the 2H period.

Further, although the 1-bit delay circuit 6 is constructed by using the S / H circuit in the above-mentioned embodiment, it is not limited to the S / H circuit configuration, and the point corresponds to one pixel pitch. CC for the period (double that for color)
Any configuration that can delay the D output may be used. further,
In the above embodiment, the defect correction is performed by the pre-interpolation in which the CCD output of the defective pixel is replaced by the CCD output of the previous pixel using the S / H circuit, but the adaptive interpolation using the digital signal processing is performed. In the system, the CCD output for the defective pixel is replaced with the CC output for the pixels before and after it.
It is also possible to perform defect correction using average value interpolation in which the average value of D output is replaced.

[0028]

As described above, according to the present invention,
The difference between the image pickup output of the solid-state image pickup device and the image pickup output delayed by a period corresponding to one pixel pitch is detected, and a defective pixel is detected based on the difference signal, and the difference between the image pickup output and its 1H delay output is obtained. The defective pixel is detected on the basis of the difference signal, and the defective pixel is finally detected by the logical product of both detection outputs. Since the defective pixel can be detected by the correlation with the pixel of, the effect of improving the detection accuracy of the defective pixel can be obtained.

Further, since the image point defect detection function is incorporated in the camera itself, it is possible to detect a defect in real time even in a normal image pickup state, and it is also possible to cope with a defect change due to electrostatic breakdown or aging. Moreover, there is an effect that a distribution form in which the solid-state image sensor and the defect data are paired is unnecessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing waveform diagram (No. 1) for explaining the operation of defect detection and defect correction.

FIG. 3 is a timing waveform chart (No. 2) for explaining the operation of defect detection and defect correction.

FIG. 4 is a timing waveform diagram (No. 3) for explaining operations of defect detection and defect correction.

FIG. 5 is a diagram showing a relationship between defective pixels and peripheral pixels.

[Explanation of symbols]

 1 CCD image sensor 2, 19 CDS (correlated double sampling) circuit 3, 5, 7, 8, 17 Subtractor 4 AGC (automatic gain control) circuit 6 1-bit delay circuit 11, 12, 22, 23 Latch circuit 18 1H Delay circuit 24 Address counter 25 Address conversion circuit 26 RAM 27 Correction pulse generation circuit 28 Sampling pulse generation circuit

Claims (7)

[Claims] 1. A first delay means for delaying an image pickup output of a solid-state image pickup element by a period corresponding to one pixel pitch, and a first subtraction means for subtracting an input of the first delay means and its output. A first defect detecting means for detecting a defective pixel based on the subtraction output of the first subtracting means; a second delay means for delaying the image pickup output by one horizontal scanning period; and a second delay Second subtraction means for performing subtraction between the input of the means and the output thereof, second defect detection means for detecting a defective pixel based on the subtraction output of the second subtraction means, and the first and second A storage unit that stores and holds defect data relating to a defective pixel detected by both of the defect detection units, and a correction unit that corrects the imaging output of the defective pixel based on the defect data stored and held in the storage unit are provided. Characterized by Defect correction apparatus of the solid-state imaging device. 2. The defect correction apparatus for a solid-state image pickup device according to claim 1, wherein the first delay means comprises a sample / hold circuit for sampling / holding the image pickup output. 3. The first and second defect detection means each include a pair of level comparison circuits for comparing the level of the subtraction output with two positive and negative detection levels, and the two detection levels are variable. The defect correction apparatus for a solid-state image pickup device according to claim 1, wherein 4. A pair of latch circuits for latching each comparison output of the pair of level comparison circuits for a period corresponding to one pixel pitch, and one input of the pair of latch circuits. 4. The solid-state imaging device according to claim 3, further comprising a pair of logical product circuits that take a logical product of the output and the other output, and the defect data is obtained based on each output of the pair of logical product circuits. Defect correction device. 5. The defect correction apparatus for a solid-state image pickup device according to claim 1, further comprising an address conversion unit that converts the defect data into address data and stores the address data in the storage unit. 6. The pre-interpolation for replacing the image pickup output for the defective pixel with the image pickup output one pixel before,
2. The defect correction apparatus for a solid-state image pickup device according to claim 1, wherein correction is performed by average value interpolation in which an image pickup output of the defective pixel is replaced with an average value of image pickup outputs of pixels before and after the defective pixel. 7. The defect correcting apparatus for a solid-state image pickup device according to claim 5, further comprising a judging unit for judging a pixel defect by comparing the address data on a time axis.