JPH06222145A - Method for detecting radiation - Google Patents

Abstract

PURPOSE:To greatly enhance the sensitivity at which radiation is detected by repeating data reading, checking and writing cycles, and simultaneously performing reading and checking of data and writing of the next data. CONSTITUTION:If a pulse signal S5 from a fundamental wave transmitting circuit 2 is inputted to a line address generating circuit 5 while a line address is 0, the line address counter of the circuit 5 is incremented by the signal S5 and a signal S9 is inputted to a line address generating circuit 6. The circuit 6 is incremented according to the signal S9 and a pulse signal S6 from the circuit 2, and these operations are repeated in sequence. The data output S12 of a designated address in a DRAM 1 is thereby read and checked with the data S11 of a write data generating circuit 9. A data checking circuit 8 checks write data with read data and when inversion of the data S12 is recognized a data inversion pulse S13 is transmitted from the circuit 9 to a count display circuit 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention includes, for example, radiation control operations (detection of surface contamination of clothes and the like due to alpha-ray "ionizing radiation") in nuclear facilities, and aerosol condensation nuclei suspended in the environment. The present invention relates to a radiation detection method for detecting a radionuclide (radon and its daughter nuclide).

[0002]

2. Description of the Related Art Conventionally, by using a DRAM (Dynamic Random Access Memory), a phenomenon in which the data stored in the memory is inverted by the invasion of the alpha ray, that is, a so-called soft error is detected to detect the alpha ray. It has been proposed to perform detection (see, for example, JP-A-55-18044 and JP-A-63-61983). Here, soft errors occur randomly in memory and do not occur repeatedly.
It can be defined as a bit error, and the bit in which a soft error has occurred is characterized by being completely recovered in the next write cycle.

[0003]

In the conventional DRAM used in the alpha ray detecting device, data is sequentially written in each information storage element (memory cell),
Then, after a lapse of a predetermined time, the data is sequentially read from each of the information storage elements, the write data and the read data of each of the information storage elements are collated, and the number of inconsistencies between the write data and the read data is counted. ,
It is designed to detect alpha rays. Therefore, in the case of performing continuous detection, data writing, data reading, and collation are repeated,
There is a problem that the alpha ray is not detected from the time when the data is read and the collation is performed until the time when the next data is written, so that the alpha ray count rate (sensitivity) is low. In order to improve this problem, if the time from writing of data to reading of data and collation is lengthened, the probability that alpha rays will penetrate into one information storage element more than once increases, and the alpha rays may be missed. Will increase.

The present invention has been made in view of the above circumstances, and an object of the present invention is to significantly improve the sensitivity of radiation detection and to suppress the counting down of radiation. To provide a method.

[0005]

In order to achieve the above object, the present invention inputs a row address and a column address into a dynamic random access memory in which a layer absorbing ionizing radiation is removed, and the dynamic random access memory is provided. Select a large number of information storage elements in order,
A cycle of writing data to these information storage elements is performed, then data is read from each of the information storage elements, and the write data and the read data of each of the information storage elements are compared with each other. The data read, collation, and write cycles are repeated, while the data collation is performed to count the number of inconsistencies between the write data and the read data of each of the information storage elements. It detects radiation.

[0006]

In the radiation detecting method of the present invention, by repeating the data reading, collating and writing cycles, the data reading and collating and the next data writing are performed at the same time, and the radiation is not detected. Get rid of.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.

In FIG. 1, reference numeral 1 is 1M × 1 (256K × 4 or 25) from which the layer that absorbs alpha rays is removed.
6K × 1 or the like) (dynamic random access memory) of DRAM, and the DRAM 1 includes three types of control signals S1, S2, S3 from the basic waveform transmission circuit 2.
Have been entered respectively. These control signals S1,
S2 and S3 are row address strobe pulse, column address strobe pulse, write, and read / verify cycle control signals, respectively. A clock pulse S4 of 4 MHz is input from the clock 3 to the basic waveform transmitting circuit 2.
4 based on the various signals S1, S2, S3, and S5.
It is configured to generate and output S8. That is, the signal S5 is input to the row address generation circuit 5 including the row address counter of the address generation circuit 4, and is the inverted version of the control signal S1. Then, when the row address counter of the row address generation circuit 5 counts up by the signal S5 (increments from 0 to 1023, from 1023 to 0).
Returning to this), the signal S9 is input to the column address generation circuit 6 including the column address counter of the address generation circuit 4. Further, the signal S6 is inputted to the column address generation circuit 6, and the signal S6
6, the column address generation circuit 6 is configured to be incremented (+1). When the column address generation circuit 6 counts up (increments from 0 to 1023, 10
After returning from 23 to 0), the signal S10 is input to the basic waveform transmitting circuit 2, and based on the signal S10, the write data and the read data are collated in the read, collate, and write (read modify write) cycles. A signal S8 for controlling the signal is output. Further, the signal S7 is input to the address selection circuit 7, and when the signal S7 is at the high (H) level, the address selection circuit 7 selects the row address output by the row address generation circuit 5. Latched and the signal S
When 7 is at low (L) level, the address selection circuit 7 is configured to select and latch the column address output by the column address generation circuit 6. The output of the address selection circuit 7 is output from the terminals A0 to A0 of the DRAM 1.
It is adapted to be input to A9 (in FIG. 4 to FIG. 7, reference numeral RA indicates a row address and CA indicates a column address). Furthermore, the signal S8 is the write data S11 and D output from the write data generation circuit 9 during the read, collation and write cycles.
It controls collation with the read data S12 output from the data output terminal DOUT of the RAM 1, and is input to the data collating circuit 8. The data S11 input from the write data generation circuit 9 to the data input terminal DIN of the DRAM and the data collation circuit 8 is set to 0 (L), which causes the DRAM 1 in FIG. The content (0) stored in the memory cell MC of each information storage element is not inverted even if an alpha ray is incident (a memory cell error does not occur). On the other hand, data reading, collation,
During writing, the potential of the bit line BL is temporarily undefined, and then the transistor Tr is turned on from the word line WL until the potential of the bit line BL is fixed (about 10 ns). BL unit in (n ⁺ region of the n ⁺ regions and the sense amplifier SA bit line BL is in contact), the electrons induced by alpha flows, data stored in the memory cell MC is inverted (0 → 1, bit line error occurs). When the data collating circuit 8 collates the write data with the read data and, as a result, it is confirmed that the data is inverted, the data inversion pulse S13 is sent to the count display circuit 10, and in the count display circuit 10, The number of inversion pulses S13 input within a predetermined time is output to a counting display device such as an LCD or an electronic buzzer.

A power supply circuit for driving each circuit shown in FIG. 1 is, as shown in FIG. 2, a DC voltage source 20 such as a battery,
Connected to this DC voltage source 20 and fixed voltage (5V)
Positive voltage regulator 21 for supplying each circuit other than the DRAM 1 to the DC voltage source 20 and a resistor R
1, R2, diode D, amplifier AMP and variable resistance V
A DRAM power supply circuit 22 configured by R1 for applying a voltage-adjustable power supply voltage (VCC-VSS) between a power supply terminal VCC of the DRAM1 and a terminal VSS which is grounded (GND), and the DC voltage source. 20 and is composed of a negative voltage converter 23, a negative voltage regulator 24, a resistor R3, and a variable resistor VR2, and is capable of adjusting the substrate bias voltage (VBB−) between the substrate bias terminal VBB and the terminal VSS of the DRAM 1. And a substrate bias voltage circuit 25 for DRAM for applying (VSS). Here, the substrate bias terminal VBB of the DRAM 1 is normally connected to the substrate bias generation circuit in the DRAM 1 by
Although a voltage of about −3 V (with respect to the terminal VSS) is applied, when a voltage is applied from the DRAM substrate bias voltage circuit 25, the external voltage becomes dominant due to the impedance relationship.

When the method of the present invention is carried out using the alpha ray detecting apparatus constructed as described above, first of all,
In the data write (delay write) cycle (see FIGS. 4 and 5), when the column address is 0 and the pulse signal S5 from the basic waveform transmission circuit 2 is input to the row address generation circuit 5, the pulse signal S5 causes , The row address counter of the row address generation circuit 5 is incremented (+1), and at the moment when it counts up and returns from 023 to 0, the signal S9 is input to the column address generation circuit 6 including the column address counter, This signal S
The column address generation circuit 6 is incremented (0 → 1) based on 9 and the pulse signal S6 from the basic waveform transmission circuit 2. Then, by repeating this operation in sequence, the column address is incremented each time the row address is counted up, becomes 0 to 1023, and returns to 0 again until the write data generation circuit 9 is reached.
0 (L) which is the write data S11 is sequentially written to the designated address in the DRAM 1. At this time, the data output terminal DOUT of the DRAM 1 is connected to the data output terminal DOUT of FIG.
Signal S12 of high impedance (High
The (h-Z) state and the uncertain output state are repeated.

After the write data S11 has been written to all the addresses in the DRAM 1 in this way, a data read, collation and write (read modify write) cycle starts (see FIGS. 6 and 7). The read, collate, and write cycles are basically the same as the above data write cycle, except that the write data S11 output from the write data generation circuit 9 and the data output terminal DOUT of the DRAM 1 are different at every predetermined timing.
This is the point at which the signal S8 for controlling the collation with the read data S12 output from is output (becomes L level).
That is, when the pulse signal S5 from the basic waveform generation circuit 2 is input to the row address generation circuit 5 in the state where the column address is 0, the row address counter of the row address generation circuit 5 is incremented by this pulse signal S5. The signal S9 is input to the column address generation circuit 6 composed of a column address counter at the moment when the count is counted up from 1023 to 0, and based on this signal S9 and the pulse signal S6 from the basic waveform transmission circuit 2. The column address generation circuit 6 is incremented (0 → 1). By sequentially repeating this operation, the column address is incremented each time the row address is counted up, and when it goes from 0 to 1023, the column address returns to 0 again and the increment is repeated. As a result, the above D
The data output S12 of the designated address in the RAM1 is temporarily stored in the output buffer in the DRAM1 sequentially,
The data is read out through the output buffer and collated with the write data S11 of the write data generation circuit 9, and at the same time, 0 (L) which is the write data S11 is DRA.
The addresses are sequentially written again through the input latch in M1. Then, at the time of reading, collating, and writing, as described above, the potential of the bit line BL is temporarily undecided, then the transistor Tr is turned on from the word line WL, and the potential of the bit line BL is fixed. In the meantime (about 10 ns), the bit line BL portion (the n ⁺ region in contact with the bit line BL and the sense amplifier SA
(N ⁺ region), when the electrons induced by the alpha rays flow in, the data stored in the memory cell MC is inverted (0 → 1). When the data collating circuit 8 collates the write data with the read data and confirms that the read data S12 is inverted, the data collating circuit 8 sends a data inversion pulse S13 to the counting display circuit 10, and the count is displayed. In the display circuit 10, the number of inversion pulses S13 input within a predetermined time is output to a count display device such as an LCD or an electronic buzzer.

In this way, as shown in FIG.
Data is first written (indicated by W in the figure) for all addresses of AM1, and then data reading, collation, and writing are repeatedly performed (RC in the figure).
(Shown as MW) causes problems that have occurred in the past (the alpha ray count rate is low, and alpha rays are missed)
The number of bit line errors at each address can be smoothly counted, and the write (delay write) cycle and the read, collate, write (read modify write) cycle control are the same. Since only the signal S8 needs to be operated, the logic circuit becomes compact.

In the above embodiment, the column address is incremented every time the row address is incremented and counted up.
Not limited to this, a method of decrementing the column address each time the row address is decremented (−1) and returned from 0 to 1023, or a method of incrementing the row address and decrementing the column address. And so on.

[0014]

As described above, according to the present invention, the data read, collation, and write cycles are repeated to simultaneously perform the data read, the collation, and the next data write, and no radiation is detected. The radiation detection sensitivity can be greatly improved by eliminating
Moreover, counting down of radiation can be suppressed.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a power supply circuit unit.

FIG. 3 is an equivalent circuit diagram of a memory cell and a sense amplifier.

FIG. 4 is a timing diagram showing an initial stage of a write (delay write) cycle.

FIG. 5 is a timing diagram showing the end stage of a write cycle.

FIG. 6 is a timing chart showing an initial stage of a read, collation, and write (read modify write) cycle.

FIG. 7 is a timing diagram showing the stages of a read, collate, and write cycle termination.

FIG. 8 is an explanatory diagram showing an alpha ray detection operation.

[Explanation of symbols]

 1 DRAM (Dynamic Random Access Memory) 8 Data collation circuit 9 Write data generation circuit 10 Count display circuit

Claims (1)

[Claims] 1. A row address and a column address are input to a dynamic random access memory from which a layer absorbing ionizing radiation is removed, and a large number of information storage elements in the dynamic random access memory are sequentially selected,
A cycle of writing data to these information storage elements is performed, then data is read from each of the information storage elements, and the write data and the read data of each of the information storage elements are compared with each other. The data read, collation, and write cycles are repeated, while the data collation is performed to count the number of inconsistencies between the write data and the read data of each of the information storage elements. A radiation detection method for detecting radiation.