JPH0622169A - Clock generating circuit and ghost monitor - Google Patents

Abstract

PURPOSE:To obtain the clock generating circuit generating a stable clock signal. CONSTITUTION:A synchronizing separator circuit 1 extracts a synchronizing signal from a video signal. A 1st PLL circuit A generates a 1st clock from the synchronizing signal. A Y/C separation circuit 5 extracts a luminance signal from the video signal. A high frequency signal extract circuit B extracts a leading high frequency signal of the luminance signal. An inverting signal generating circuit C extracts a horizontal synchronizing signal from the high frequency signal and inverts the horizontal synchronizing signal for a prescribed time to generate an inverted signal. A phase signal generating circuit D generates the phase signal whose phase is nearly matched with the phase of the inverting signal from the horizontal synchronizing signal. A correlation device 21 generates a correlation signal between the inverting signal and the phase signal. A fundamental correlation signal extract circuit E extracts an autocorrelation signal of the fundamental wave component of the signal from the correlation signal. A 2nd PLL circuit F generates a 2nd clock from the autocorrelation signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improving television reception by generating a stable clock.
The present invention relates to an improvement of a clock generation circuit of a receiver and a ghost monitor to which main parts of this clock generation circuit are applied.

[0002]

2. Description of the Related Art Conventionally, a PLL type circuit has been known as a clock generation circuit used in a television receiver. As shown in FIG. 6, this circuit includes a sync separation circuit 1, a phase comparator 2, a VCO 3 and a frequency divider 4,
The sync separation circuit 1 extracts a sync signal from the video signal and generates a clock tuned to the video signal based on the sync signal.

[0003]

However, the conventional clock generating circuit of this type has the following problems. That is, in the conventional clock generation circuit, the measures for generating the clock depending on the input signal and stabilizing the clock against disturbances such as jitter and ghost have been insufficient. Therefore, the television receiver having this type of clock generation circuit has a problem that the clock becomes unstable due to the influence of jitter or ghost contained in the video signal, resulting in incomplete synchronization. In particular, when this type of receiver is used as an in-vehicle television to perform mobile reception, there is a problem in that jitter is more likely to occur due to movement and vibration of the vehicle, and this effect easily deteriorates the reception state.

Further, since the clock is unstable as described above, the ghost monitor for measuring the ghost of the reception failure has the following problems. That is, in the conventional ghost monitor, the ghost measurement reference is based on the relatively stable vertical synchronization signal having a long interval. For example, the delay time of the ghost and the degree of the ghost (D / U ratio) are measured by sequentially sampling and holding from the leading edge of the vertical synchronizing signal of the video signal and performing the synchronous detection while rotating the detection phase. However, since the conventional ghost monitor of this type uses only the vertical synchronizing signal as a measurement reference, when the ghost changes at high speed within a time shorter than one field, this change must be measured in relation to the horizontal synchronizing signal. However, there was a problem that the change could not be confirmed.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and its object is to provide a clock generation circuit for generating a stable clock. Another object of the present invention is to provide a ghost monitor which is capable of monitoring a fast change in ghost by applying the main part of this clock generation circuit.

[0006]

In order to achieve the above object, a clock generation circuit of the present invention provides a luminance signal extraction means for extracting a luminance signal from a video signal and a rising high frequency signal of the signal from the luminance signal. High-frequency signal extraction means for extracting, a horizontal sync signal from the high-frequency signal, inverted signal generation means for inverting the horizontal sync signal for a predetermined time to generate an inverted signal, and the inverted signal from the horizontal sync signal Phase signal generating means for generating a phase signal substantially in phase with, correlation signal generating means for generating a correlation signal between the inverted signal and the phase signal, and an autocorrelation signal of a fundamental wave component of the signal from the correlation signal And a clock generating means for generating a clock from the autocorrelation signal.

Further, the ghost monitor according to claim 2 is
Luminance signal extraction means for extracting a luminance signal from the video signal,
Sync signal extracting means for extracting a composite sync signal from the video signal, high frequency signal extracting means for extracting a rising high frequency signal of the signal from the luminance signal, and horizontal sync signal from the high frequency signal, Inversion signal generation means for inverting the horizontal synchronization signal for a predetermined time to generate an inversion signal, phase signal generation means for generating a phase signal in which the horizontal synchronization signal is approximately in phase with the inversion signal, the inversion signal and the phase It is characterized by further comprising: a correlation signal generating means for generating a correlation signal with the signal; and a synthesizing means for synthesizing the correlation signal and the composite synchronizing signal to generate a display signal for monitor display.

[0008]

The present invention having the above structure has the following functions. That is, in the clock generation circuit of claim 1, the inversion signal generation means inverts the horizontal synchronization signal for a predetermined time to generate an inversion signal, and at the same time, the phase signal generation means substantially aligns the horizontal synchronization signal with the inversion signal. Each phase signal is generated. Then, the correlation signal generating means generates a correlation signal of the inverted signal and the phase signal.
At this time, since the temporal directionality of the inversion signal and the phase signal is inverted, the deviation of the interval of the horizontal synchronization signal due to the jitter of the video signal is caused between the inversion signal and the phase signal when the correlation signal is generated. Offset. Therefore, a stable clock can be generated.

Further, in the same circuit, since the fundamental wave correlation signal extraction means extracts the autocorrelation signal of the fundamental wave component of the signal from the correlation signal, the ghost having a weaker correlation with the fundamental waves than the fundamental waves. Can be eliminated from the clock.

Further, in the ghost monitor according to the second aspect, as in the clock generation circuit according to the first aspect, since the fundamental wave correlation signal indicating the fundamental wave is generated based on the horizontal synchronizing signal, the period shorter than one field. Changes in ghosts that occur within can be monitored.

Further, as in the clock generating circuit according to the first aspect, since the deviation of the intervals of the horizontal synchronizing signals is canceled out, the ghost delay time and the D /
The U ratio can be confirmed.

[0012]

Embodiments of the present invention will be specifically described below with reference to the drawings.

A. First Embodiment (1) Configuration of the First Embodiment ... FIG. 1 [Overall Configuration] This embodiment is a clock generation circuit of a television receiver, and a sync separation circuit 1 for extracting a sync signal from the video signal. A first PLL circuit A for generating a first clock from the sync signal; a Y / C separation circuit 5 for extracting a luminance signal from a video signal; and a rising high frequency signal of the signal from the luminance signal. A high-frequency signal extraction circuit B, an inversion signal generation circuit C that extracts a horizontal synchronization signal from the high-frequency signal, inverts the horizontal synchronization signal for a predetermined time to generate an inversion signal, and the inversion signal from the horizontal synchronization signal. A phase signal generation circuit D that generates a phase signal that is substantially in phase with the signal, a correlator 21 that generates a correlation signal between the inverted signal and the phase signal, and an autocorrelation of the fundamental wave component of the signal from the correlation signal. Extract signal That has a fundamental correlation signal extracting circuit E, and a second PLL circuit F for generating a second clock from the auto-correlation signal.

[Sync Separation Circuit] The input side of the sync separation circuit 1 is connected to a video signal input line outside the clock generation circuit. The output side of the sync separation circuit 1 is connected to the input side of the first PLL circuit A.

[First PLL Circuit] First PLL Circuit A
Has a phase comparator 2, a VCO 3, and a frequency divider 4. The first input side of the phase comparator 2 is connected to the output side of the sync separation circuit 1 as the input side of the first PLL circuit A. The output side of the phase comparator 2 is connected to the input side of the VCO 3. The output side of the VCO 3 is connected to the input side of the frequency divider 4 and at the same time, the first PL
The output side of the L circuit A is connected to a sampling clock input port of an A / D conversion circuit 9 described later. The output side of the frequency divider 4 is connected to the second input side of the phase comparator 2.

[Y / C separation circuit] The input side of the Y / C separation circuit 5 is connected to the video signal input line at the same time as the synchronization separation circuit 1. The output side of the Y / C separation circuit 5 is connected to the input side of the high frequency signal extraction circuit B.

[High-frequency signal extraction circuit] High-frequency signal extraction circuit B
Has an LPF 6, a differentiating circuit 7, and a clipping circuit 8. The input side of the LPF 6 is connected to the output side of the Y / C separation circuit 5 as the input side of the high frequency signal extraction circuit B. The output side of the LPF 6 is connected to the input side of the differentiating circuit 7. The output side of the differentiating circuit 7 is connected to the input side of the clipping circuit 8. Also, the clip circuit 8
Is the output side of the high frequency signal extraction circuit B, and is the input side of the inverted signal generation circuit C and the phase signal generation circuit D.
It is connected to the input side of the / D conversion circuit 9.

[Inverted Signal Generation Circuit] Inverted Signal Generation Circuit C
Is A / which extracts a horizontal synchronization signal from the high frequency component signal.
The D conversion circuit 9 and the horizontal synchronization period extraction circuit 11, and the time axis inversion circuit 13, the D / A conversion circuit 15, the amplitude modulation circuit 17, and the BPF 20 which invert the horizontal synchronization signal for a predetermined time to generate an inversion signal. Have. Of these, the A / D conversion circuit 9 also has a role of configuring the phase signal generation circuit D as well as the inverted signal generation circuit C. That is, the input side of the A / D conversion circuit 9 is connected to the output side of the high frequency signal extraction circuit B as the input side of the inverted signal generation circuit C and the phase signal generation circuit D. The output side of the A / D conversion circuit 9 is divided into two systems, one of which is connected to the input side of the horizontal synchronization period extraction circuit 11 which constitutes the inverted signal generation circuit C,
The other is connected to the input side of the horizontal synchronization period extraction circuit 10 which constitutes the phase signal generation circuit D.

The sampling clock input port of the A / D conversion circuit 9 is connected to the output side of the first PLL circuit. In addition, the horizontal synchronization period extraction circuit 11
The output side of is connected to the input side of the time axis inverting circuit 13. The output side of the time axis inverting circuit 13 is connected to the input side of the D / A conversion circuit 15. The output side of the D / A conversion circuit 15 is connected to the input side of the amplitude modulation circuit 17. An oscillator 18 is connected to the modulation frequency input port of the amplitude modulation circuit 17 and the amplitude modulation circuit 16 described later. Further, the output side of the amplitude modulation circuit 17 has a BPF.
It is connected to the input side of 20. The output side of the BPF 20 is the output side of the inverted signal generation circuit C, and the correlator 21
Is connected to the first input side of.

[Phase Signal Generation Circuit] Phase Signal Generation Circuit D
Is the A / D conversion circuit 9 / horizontal synchronization period extraction circuit 10 / D
It has an A / A conversion circuit 14, an amplitude modulation circuit 16, and a BPF 19, and is configured almost the same as the inverted signal generation circuit C.
Instead of the time axis inverting circuit 13, a delay circuit 12 for generating a phase signal that is substantially in phase with the inversion signal is provided. The input side of the horizontal synchronization period extraction circuit 10 that constitutes the phase signal generation circuit D is connected to the output side of the A / D conversion circuit 9. The output side of the BPF 19 is connected to the second input side of the correlator 21 as the output side of the phase signal generation circuit D.

[Correlator] The correlator 21 uses an elastic surface delay line, and the first and second input sides of this correlator 21 have an inverted signal generating circuit C and a phase signal generating circuit D, respectively. Is connected to the output side of. The output side of the correlator 21 is connected to the input side of the fundamental wave correlation signal extraction circuit E.

[Fundamental Correlation Signal Extraction Circuit] The fundamental wave correlation signal extraction circuit E has a BPF 22, a detection circuit 23, a clipping circuit 24, and an fH pulse generation circuit 25.
Of these, the input side of the BPF 22 is connected to the output side of the correlator 21 as the input side of the fundamental wave correlation signal extraction circuit E. The output side of the BPF 22 is connected to the input side of the detection circuit 23. The output side of the detection circuit 23 is connected to the input side of the clip circuit 24. The output side of the clip circuit 24 is connected to the output side of the fH pulse generation circuit 25. The output side of the fH pulse generation circuit 25 is connected to the input side of the second PLL circuit F as the output side of the fundamental wave correlation signal extraction circuit E.

[Second PLL Circuit] Second PLL Circuit F
Has a phase comparator 26, a VCO 27, and a frequency divider 28, and the first input side of this phase comparator 26 has a second PL.
The input side of the L circuit F is connected to the output side of the fH pulse generation circuit 25. The output side of the phase comparator 26 is connected to the input side of the VCO 27. Also, VCO
The output side of 27 is connected to the input side of frequency divider 28.
The output side of the VCO 27 is simultaneously connected to the clock output line outside the clock generation circuit as the output side of the second PLL circuit F. The output side of the frequency divider 28 is connected to the second input side of the phase comparator 26.

(2) Operation and effect of the first embodiment ... FIG. 2 Clock generation by the clock generation circuit of the present embodiment having the above configuration is performed as follows.

[Input of video signal] The video signal input to the clock generation circuit from the external video signal input line is divided into two systems and simultaneously input to the sync separation circuit 1 and the Y / C separation circuit 5, respectively. It

[Generation of First Clock] Sync Separation Circuit 1
Extracts a horizontal synchronizing signal from the input video signal and outputs it to the first PLL circuit A. First PLL
The circuit A generates a first clock from the input horizontal synchronizing signal and outputs it as a sampling clock to the A / D conversion circuit 9.

[Extraction of Luminance Signal] On the other hand, the Y / C separation circuit 5 extracts a luminance signal from the input video signal and outputs it to the LPF 6 on the input side of the high frequency signal extraction circuit B. This luminance signal is one to which a ghost with a delay time tτ is added (A in FIG. 2).

[Extraction of rising high-frequency signal] The high-frequency signal extraction circuit B extracts a rising high-frequency signal from the input luminance signal as follows, and outputs it to the inverted signal generation circuit C and the phase signal generation circuit D. Output. That is, the LPF 6 limits the band of the input luminance signal to improve the S / N ratio, and outputs this to the differentiating circuit 7. The differentiating circuit 7 extracts rising and falling portions, which are contour portions, from this signal (a in FIG. 2) and outputs it to the clipping circuit 8. The clip circuit 8 removes the minus signal from this signal,
The high-frequency part on the side is extracted to be a rising high-frequency signal (c in FIG. 2), and this is output to the A / D conversion circuit 9 which is the input side of the inverted signal generation circuit C and the phase signal generation circuit D. .

[Generation of Inverted Signal] The inverted signal generation circuit C extracts a horizontal synchronizing signal from the input rising high frequency signal as follows, and inverts the horizontal synchronizing signal for a predetermined time to generate an inverted signal, This is output to the correlator 21.
That is, the A / D conversion circuit 9 converts the rising high-frequency signal (c) into a digital signal using the first clock as the sampling clock. This digital signal is distributed into two systems, and is input to the horizontal synchronization period extraction circuit 11 of the inverted signal generation circuit C and the horizontal synchronization period extraction circuit 10 of the phase signal generation circuit D, respectively. The horizontal synchronization period extraction circuit 11 of the inversion signal generation circuit C extracts the horizontal synchronization period including the time width of the horizontal synchronization signal from the input digital signal, removes signals other than this period, and inverts this in the time axis. Output to the circuit 13. The time axis inversion circuit 13 inverts the temporal directionality of the input digital signal and outputs this signal to the D / A conversion circuit 15. The D / A conversion circuit 15 converts the input digital signal into an analog signal and outputs it to the amplitude modulation circuit 17. This signal becomes an inverted signal via the amplitude modulation circuit 17 and the BPF 20 (e in FIG. 2) and is output to the first input side of the correlator 21.

[Generation of Phase Signal] Phase signal generation circuit D
In the same operation sequence as the inversion signal generation circuit C, extracts the horizontal synchronization signal from the input rising high-frequency signal, and the delay circuit 12 delays this horizontal synchronization signal by td to substantially align the phase with the inversion signal. Then, a phase signal (D in FIG. 2) is generated and output to the second input side of the correlator 21.

[Generation of Correlation Signal] The correlator 21 generates a correlation signal of the input inverted signal and phase signal (F in FIG. 2) and outputs it to the fundamental wave correlation signal extraction circuit E. Here, the phase signal is f (t) and the inverted signal is g (t).
Then, the correlation signal c (t) is expressed by the following equation.

[0032]

[Equation 1] That is, the autocorrelation output peak can be obtained at the moment of t = 0.

Note that the correlator 21 uses a surface elastic delay line, and the propagation directions of the inverted signal and the phase signal inside the correlator 21 are opposite. Further, since the temporal directionality of the inversion signal and the phase signal is inverted, the deviation of the interval of the horizontal synchronizing signal due to the jitter of the video signal is canceled between the inversion signal and the phase signal when the correlation signal is generated. To be done.

[Extraction of Fundamental Wave Correlation Signal] The fundamental wave correlation signal extraction circuit E extracts the autocorrelation signal of the fundamental wave component of the input correlation signal to obtain the fundamental wave correlation signal, which is the second To the PLL circuit. That is, the input correlation signal is input to the clip circuit 24 via the BPF 22 and the detection circuit 23. Here, the clipping circuit 24 utilizes the fact that the autocorrelation of the fundamental wave is usually larger than the correlation between the fundamental wave and the ghost, and extracts only the fundamental wave autocorrelation signal from the input signal to reduce the influence of the ghost. Exclude from the signal (key in Figure 2). This fundamental wave autocorrelation signal is output to the fH pulse generation circuit 25, which generates a pulse of 1 / fH cycle and outputs it to the second PLL circuit F.

[Generation of Second Clock] The second PLL circuit F generates a second clock from the input fundamental wave autocorrelation signal and outputs it from the clock output line to the outside of the clock generation circuit. Here, from the fundamental autocorrelation signal (key in FIG. 2) that is the basis of the second clock generation, as described above,
The influence of jitter is removed by the inverted signal generation circuit C, the phase signal generation circuit D and the correlator 21, and the influence of ghost is removed by the fundamental wave correlation signal extraction circuit E. Therefore, the clock generation circuit of this embodiment can generate a stable clock.

B. Second Embodiment (1) Configuration of Second Embodiment ... FIG. 3 [Overall Configuration] The present embodiment is a clock generation circuit of a television receiver, which generates a clock from a sync separation circuit 1 and a horizontal synchronization signal. A PLL circuit A, a sync generation circuit 29 for generating a composite sync signal from the clock, and Y /
The C separation circuit 5, the high frequency signal extraction circuit B, the inverted signal generation circuit C, the phase signal generation circuit D, the correlator 21, the correlation signal, and the composite synchronization signal are combined to display on a monitor. It has an adder 30 for generating a display signal and a monitor 31.

[Common points with the first embodiment] Of the above, the synchronous separation circuit 1, PLL circuit A, Y / C separation circuit 5, high frequency signal extraction circuit B, inverted signal generation circuit C, phase signal generation The circuit D and the correlator 21 are configured similarly to the first embodiment.

[Synchronization Generation Circuit] On the other hand, the input side of the synchronization generation circuit 29 peculiar to the second embodiment is connected to the output side of the PLL circuit A. The output side of the synchronization generation circuit 29 is connected to the first input side of the adder 30. The clock may be used as a sampling clock in the A / D conversion circuit 9.

[Adder] The second input side of the adder is the BPF
It is connected to the output side of the correlator 21 via 32 and the detection circuit 33. The output side of the adder 30 is the monitor 3
Connected to 1.

(2) Operation and effect of the second embodiment ... FIG. 4 In this embodiment, the sync separation circuit 1 extracts the horizontal sync signal from the video signal, and the PLL circuit A generates the clock from the horizontal sync signal. Then, while the synchronization generation circuit 29 generates a composite synchronization signal from the clock, the Y / C separation circuit 5 converts the video signal to the luminance signal (see FIG. 4) in substantially the same manner as in the first embodiment.
4) is extracted, and the high frequency signal extraction circuit B rises the signal from the luminance signal (marked in FIG. 4) and the high frequency signal (marked in FIG. 4).
And the inversion signal generation circuit C extracts a horizontal synchronization signal from the high frequency signal (FIG. 4) and inverts this horizontal synchronization signal for a predetermined time to generate an inversion signal (FIG. 4). The phase signal generation circuit D generates a phase signal (in FIG. 4, the delay time is 0 in this embodiment) which is substantially in phase with the inversion signal from the horizontal synchronization signal, and the correlator 21 generates the inversion signal and the phase signal. Generate a correlation signal with
The adder 30 adds the input correlation signal and the composite synchronizing signal and synthesizes them into a display signal (FIG. 4), and the monitor 31 displays this on the screen.

In the monitor display at this time, as shown in FIG. 5, the time difference of (a) and (b) represents the delay time (tτ / 2), and the brightness difference of (a) and (b) is D / U. Ratio ((exp
(-Ar cosh (1 / 2n))). As described above, according to the present embodiment, since the fundamental wave correlation signal indicating the fundamental wave is generated based on the horizontal synchronizing signal, the rapid change of the ghost occurring within the period shorter than one field is monitored. can do. Also, as in the first embodiment,
Since the influence of the ghost itself and the jitter is removed from the fundamental wave correlation signal, the ghost delay time and the D / U ratio can be confirmed in relation to the stable and accurate fundamental wave.

C. Other Embodiments The present invention is not limited to the above embodiments, and includes the following other embodiments. For example, in the first and second embodiments, the correlation signal may be generated directly from the video signal without modulating the baseband signal. That is, the correlation signal may be generated without passing through the amplitude modulators 14 and 19.

[0043]

As described above, according to the present invention of claim 1, it is possible to provide a clock generation circuit for generating a stable clock. Further, according to the invention of claim 2 to which this is applied, it is possible to provide a ghost monitor capable of monitoring a change in ghost at high speed. In particular, claim 2
INDUSTRIAL APPLICABILITY The invention can be used for removing a ghost of a vehicle-mounted television receiver. Therefore, according to the present invention described above, the reception state of the television receiver can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock generation circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram of each signal in the circuit.

FIG. 3 is a circuit block diagram of a ghost monitor according to a second embodiment of the present invention.

FIG. 4 is a waveform diagram of each signal in the same circuit.

FIG. 5 is a diagram showing a monitor display by the ghost monitor.

FIG. 6 is a block diagram of a conventional clock generation circuit.

[Explanation of Codes] A: (First) PLL circuit B: High frequency signal extraction circuit C: Inversion signal generation circuit D: Phase signal generation circuit E: Fundamental correlation signal extraction circuit F: Second PLL circuit 1: Synchronous separation circuit 2, 26: Phase comparator 3, 27: VCO 4, 28: Frequency divider 5: Y / C separation circuit 6: LPF 7: Differentiation circuit 8, 24: Clip circuit 9: A / D conversion circuit 10 , 11: Horizontal synchronization period extraction circuit 12: Delay circuit 13: Time axis inversion circuit 14, 15: D / A conversion circuit 16, 17: Amplitude modulation circuit 18: Oscillator 19, 20, 22: BPF 21: Correlator 23 : Detection circuit 25: fH pulse generation circuit 29: Synchronization generation circuit 30: Adder 31: Monitor 32: BPF 33: Detector

Claims (2)

[Claims] 1. A luminance signal extracting means for extracting a luminance signal from a video signal, a high frequency signal extracting means for extracting a rising high frequency signal of the signal from the luminance signal, and a horizontal synchronizing signal from the high frequency signal. Then, an inversion signal generation unit that inverts the horizontal synchronization signal for a predetermined time to generate an inversion signal, a phase signal generation unit that generates a phase signal that is substantially in phase with the inversion signal from the horizontal synchronization signal, and the inversion signal. A correlation signal generating means for generating a correlation signal between the phase signal and the phase signal, a fundamental correlation signal extracting means for extracting an autocorrelation signal of a fundamental component of the signal from the correlation signal, and a clock from the autocorrelation signal A clock generation circuit comprising: 2. A luminance signal extracting means for extracting a luminance signal from a video signal, a synchronizing signal extracting means for extracting a composite synchronizing signal from the video signal, and a high signal for extracting a rising high frequency signal of the signal from the luminance signal. An area signal extracting means, an inversion signal generating means for extracting a horizontal synchronization signal from the high frequency signal, and inverting the horizontal synchronization signal for a predetermined time to generate an inversion signal; and a phase substantially in phase with the inversion signal from the horizontal synchronization signal. Phase signal generating means for generating a combined phase signal, correlation signal generating means for generating a correlation signal between the inverted signal and the phase signal, and a composite signal for synthesizing the correlation signal and the composite synchronizing signal for monitor display. And a synthesizing means for generating a display signal of the ghost monitor.