JPH0621825A - Signal processing unit - Google Patents

Abstract

PURPOSE:To improve the processing speed by relieving a program processing load of a digital signal processor or the like by adopting the hardware configura tion for the processing unit such that coding and decoding processing is executed for an audio signal recorded/reproduced in/from a recording medium. CONSTITUTION:This processing unit is provided with a shift clock generating circuit 4, an n-bit shift register 8 shifting data before n-bit coding into a setting MSB direction, an m-bit shift register 7 inputting the bit data overflowed by the shift operation to the LSB to shift the data in the MSB direction and a stop signal circuit 21, and the stop circuit 21 stops the shift clock at a count designated by allocation data and at an m-th count, the set of the data before coding and the relevant allocation data is set and shifted at every stop of the shift clock, then the data reduced in bit number designated by the allocation data are inputted sequentially to the m-bit shift register 7, the shift clock is stopped when the m-bits are filled, and a ready signal representing the end of processing is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device for audio signals and image signals in a digital recording / reproducing device.

[0002]

2. Description of the Related Art In recent years, read-only devices for discs such as CDs and LDs that digitally record audio and video have become widespread and have become the mainstream in this field. On the other hand, the development of a device that digitally records and reproduces voice on a magnetic tape, which has a long history, is also in progress, and in order to develop as a new voice device, the development of a device that can demonstrate high performance with a simple configuration. is necessary. In particular, the configuration of a signal processing device that handles audio signals as digital signals is an important issue.

Digital recording / reproduction of voice has been conventionally performed, and various means are used depending on the purpose and application. For example, there are optical, magneto-optical, and magnetic recording / reproducing means corresponding to the recording medium, and various means are developed depending on whether or not the signal is compressed.

The digital recording / reproducing means to which the present invention relates is a means for compressing a signal such as a voice or an image and recording / reproducing it on / from a recording medium such as a magnetic tape, and a means belonging to the frequency domain processing of the signal. , A coding means called high efficiency signal coding is used. When this means is applied to a voice signal, it is compressed to a very small number of bits by using the audible limit of voice and the masking effect.

An outline of a conventional audio signal recording / reproducing apparatus using a high efficiency encoding means will be described below with reference to the drawings. It should be noted that the content described below shows one concept of high-efficiency coding and is not the whole of a specific system. FIG. 9 is a block diagram showing the configuration of an apparatus for recording and reproducing a voice signal by encoding the voice signal by the high efficiency encoding. In the figure, 1 is an analog voice signal input terminal, 2 is an AD converter for converting the voice signal into a digital signal, and 3 is the converted digital signal into FIR.
(Finite Impulse Response) An input / output interface 4 for inputting / outputting to / from the filter 4 in a predetermined order inputs the digital signals in a predetermined order at the time of recording, and has a plurality of audio frequency regions, for example, 32 equal intervals. It outputs digital data of audio signals (hereinafter referred to as subband signal data) in each band divided into frequency bands (hereinafter referred to as subbands), and FIR for performing the reverse process during reproduction. A filter 5 is a code for applying the minimum audible limit characteristic and the auditory masking effect to each of the sub-band signal data at the time of recording to reduce and compress the number of bits, arrange and code them, and perform the reverse process at the time of reproduction. An encoder and a decoder, and a recording unit 6 for recording and reproducing the encoded signal.

The signal processing in the FIR filter 4 is not the subject matter of the present application, so a detailed description thereof will be omitted.
The FIR filter 4 inputs, for example, continuous 512 samples of audio signal data digitized by the AD converter 2 through the interface 2 and processes them while shifting them by 32 samples, as shown in FIG. It is a filter that outputs digital data of audio signals for each of 32 sub-bands, that is, sub-band signal data, obtained by dividing the audible frequency band from DC to 24 KHz at a frequency interval of 750 Hz. This subband signal data is composed of, for example, 12 pieces of uncoded data for each subband, and the voice signal of subband i is Di, 0, Di,
, ..., Di, 10, Di, 11 (i = 0, 1, ..., 31) before being coded. Each of these uncoded data Di, j (i = 0,1 ... 31, j = 0,1, ... 11) is, for example, a data of a large number of bits of 24 bits, and the data amount Many are not suitable for high density recording on magnetic tape. In high-efficiency encoding, the encoder 5 compresses the pre-encoded data by using the minimum audible limit characteristic and the masking effect, so that the pre-encoded data D is obtained.
i, 0, Di, 1, ..., Di, 10, Di, 11 are pre-encoded data having a non-constant number of bits smaller than 24 bits (hereinafter,
Called variable-length sample data) di, 0, di, 1, ...
32 pieces of data of the same timing, which are compressed into di, 10, di, 11 and taken one by one from each subband, for example, 0th variable length sample data d0,0, d1,0, d of each subband
, 0, ..., d31,0 are collectively arranged to generate a 0th recording signal, and similarly, a recording signal is also generated for the 1st to 11th subbands, and these signals are arranged. One recording signal unit is referred to as a signal frame. The details of the signal frame will be described later.

The compression of uncoded data will be briefly described below. As described above, each subband signal data obtained from the output of the FIR filter 4 has 12 bits of 12 bits.
, Uncoded data Di, 0, Di, 1, ..., Di, 10, Di, 11 in the subband i. These uncoded data Dij (i = 0, 1, ...
・ 、 32. Each of j = 0, 1, ..., 11) is 24-bit data and is not compressed at all. In high-efficiency coding, these uncoded data are compressed by focusing on the minimum audible limit characteristic and the masking effect. That is,
There is a minimum level of sound level that humans can hear, and signals below this level cannot be heard, and sounds in the vicinity of high-level sounds are masked and become inaudible or difficult to hear. . Such characteristics depend on the frequency of the voice.

FIG. 11 is a graph showing the outline of such auditory characteristics. In the figure, the characteristic indicated by the curve indicates the minimum audible limit in decibels, and the characteristic indicated by the vertical bar indicates the number of bits assigned to the sample data in the range. The details of the compression processing using this characteristic are also omitted because they are not the gist of the present application, but in the extreme, sounds below the minimum audible limit are ignored, sample data is discarded, and the code of the range with a low audible limit level is used. The pre-encoding data is represented by a large number of bits, and the pre-encoding data in the range having a high audible limit level is represented by a small number of bits. Further, when there is a high level sound, the minimum audible limit level is set to be large for the sound of the frequency near the high level sound. By such compression processing, the pre-coding data of the subband is 24
Variable-length sample data having a bit number equal to or less than the bit number is converted into di, 0, di, 1, ..., Di, 10, di, 11.

Further, in the high-efficiency coding system, the value of the variable-length sample data is expressed as a ratio to the maximum sample value in the subband, and the sample maximum value of each subband is common to all subbands. A 6-bit quantized expression is used as a scale, and a 2 dB difference is set for each bit. Therefore, one of the features is that each sample value is represented by the floating point method in which the quantization maximum value of the subband is the exponent part and the ratio to it is the mantissa part.

A recording signal for recording the variable length sample data will be described below. For example, as one recording method, variable-length sample data d of subband 0
It is said that 0, 0, d0, 1, ..., D0, 12 are sequentially recorded, then the variable length sample data of subband 1 is sequentially recorded, and then the variable length sample data of subband 2 is sequentially recorded. As described above, it is possible to generate a recording signal in units of subbands. In this method, the recording signal of the sub-band unit is 3
If two signals are recorded, all subband signals will be recorded. However, in the high efficiency coding system, the recording signal is generated by the following method. That is, one piece of data at the same timing from the variable length sample data of each subband, for example, 0th data d0,0, d1,0, ..., D3.
1,0 is taken, and the data string arranged together with the respective compression condition data is used as a recording signal. A signal frame is a collection of such variable length sample data for each subband.

FIG. 12 is a schematic diagram showing the structure of the signal frame. In the figure, a signal frame has a slot having a specific number of bits, for example, 32 bits as a structural unit, and one slot at the head including a synchronization signal and coding information and sample data Dij are variable length sample data d.
Two pieces of information that give compression conditions to ij, that is, a plurality of slots in which bit allocation information and scale factor information are arranged, and variable-length sample data d0, j, d1, j at the same timing of each subband ,,, d31, j are arranged and an encoded data string composed of a plurality of slots. Bit allocation information (hereinafter referred to as allocation data) gives the number of bits of the mantissa part of each variable length sample data compressed.
(That is, it indicates how many bits are stored in the encoded data string), and the scale factor information gives the quantization maximum value of the sample data in the exponent part, that is, the subband. Since this compression condition is different for each subband, the compression conditions for each subband are arranged in multiple slots in a predetermined order and given in the same order as the allocation data and scale factor. There is. Also, the variable length sample data d0,
The arrangement order of j, d1, j, ..., D31, j is the same as the arrangement order of the allocation data and scale factor. Note that the allocation data is, for example, 0 (4
If the number of bits is 0000), the number of bits is reduced by omitting the sample data without arranging.

As described above, one signal frame has variable length sample data obtained by collecting 32 pieces of one of 12 pieces of variable length sample data of subbands from each subband, d0,
j, d1, j, ..., di, j, ..., d31, j (j =
0, 1, ..., 11). Therefore, twelve variable length sample data of each subband are obtained from the information of the signal frame, and for example, di, 0, di, 1, d
It is possible to reproduce the signal of sub-band i by obtaining i, 2, ... Di, 11, and it is possible to reproduce the original signal, that is, the audio signal by frequency-synthesizing the signals of the sub-bands.

In the above description, the audio signal is described as monaural. However, since a stereo audio signal is actually handled, there are 32 sub-bands on each of the left and right channels, and the allocation data and scale corresponding to each sub-band are provided. A factor and an encoded data string composed of a plurality of compressed sample data are stored in one signal frame.

A conventional signal processing apparatus for arranging variable length sample data in a coded data string region of a signal frame in the above high efficiency coding will be described below with reference to the drawings. For simplification of explanation, it is assumed that the audio signal is monaural and one slot is 16 bits. FIG. 13 is a schematic diagram showing the processing steps of a conventional signal processing device. Further, FIG. 14 shows a microcomputer and a digital signal processor (hereinafter referred to as DSP).
An operation of the conventional signal processing device by the control means such as is shown in a flowchart. In FIG. 13, the sample data compression unit outputs sample data obtained by converting the sample data output from the FIR filter by the minimum audible limit characteristic and the masking effect, and at the same time, allocates data indicating how many bits the mantissa is to be shortened (bits). (Allocation information) and the scale factor are output. Although this sample data has been converted into the data to which the voice characteristic has been applied, the sample data before encoding in which the mantissa part is not truncated to the number of bits specified by the allocation data (hereinafter referred to as pre-encoding data) ).

Therefore, in order to arrange the variable-length sample data in the encoded data area of the signal frame, the pre-encoded data of the subband corresponding to the arrangement order of the allocation data is selected, and the MSB of the data is used to select the allocation data. It is necessary to take a specified number of bits, discard the rest, and arrange them in a signal frame according to the arrangement order of allocation data. 12 for each sub-band output from the sample data compression means in FIG.
The unencoded data are temporarily stored in the memory as a process of digital processing. The pre-encoding data of each sub-band to be array-processed is the memory 0 to the memory 31.
Stored in. These uncoded data are stored as data having a number of bits larger than the number of bits designated by the allocation data. The frame memory is a memory that stores the array result, that is, the signal frame, and the synchronization signal and the coding information are stored in the leading slot of the frame memory.

The allocation data and scale factor output by the sample data compression means are written in predetermined positions in the frame memory. The order of variable-length sample data arranged in the frame memory is the same as the order of allocation data as described above. Now, the order is set as subband 0, subband 1, ..., Subband 30, and subband 31. Further, as shown in FIG. 13, the allocation data is 6 bits for pre-coding data of subband 0 and 8 bits for subband 1.
It is assumed that the number of bits is designated as 10 bits for subband 2, 3 bits for subband 3, and so on.

First, the uncoded data of subband 0 is sequentially taken out from the MSB of the memory 0 by 6 bits and stored in the LSB of the register 1 while shifting to the right. Next, the pre-encoding data of subband 1 is sequentially taken out from the MSB of the memory 1 by 8 bits and stored in the LSB of the register 1 while right shifting. Next, the pre-encoded data of subband 2 is sequentially taken out from the MSB of the memory 2 by 10 bits and stored in the LSB of the register 1 while shifting to the right. However, as described above, since one slot has 16 bits in the embodiment, the pre-encoding data of the subband 2 is stored in the register 1 in 2 bits.
Transfer is stopped when bits are stored. Then, it is stored in the first position of the encoded data string area of the frame memory. Next, clear register 1 once, then memory 2
The remaining 8 bits are sequentially stored in the register 1, and then the pre-encoding data of the subband 3 is read from the MSB of the memory 3 to 3 bits.
The bits are sequentially taken out and stored in the LSB of the register 1 while right shifting.

By repeating the above operation,
The uncoded data of each subband is selected from the MSB by the number of bits designated by the allocation data, the rest is truncated, and stored in a predetermined position in the frame memory. As described above, if the allocation data is 0000 in a 4-bit configuration, that data is not arranged.

FIG. 14 is a schematic flow chart showing the above-mentioned operation, but since the operation is clear from the above explanation, its explanation is omitted.

The demodulating means for the coded signal will be described below with reference to the drawings. FIG. 15 shows a conventional D
The process of decoding in the decoding means using SP is shown in a schematic diagram. The signals of a plurality of tracks reproduced from the recording medium are separated into allocation data, scale factor, and coded data through processes such as error correction, and are composed into a signal frame, which are temporarily stored in predetermined positions of registers. However, details of this process are omitted because they are not the object of the present invention.

In FIG. 15, the frame memory is a memory that stores signals obtained by reproducing the recording medium.
Further, the register 1 receives a signal for one slot of the encoded data string of the frame memory, shifts it by the number of bits specified by the allocation data, and transfers the data to the memory of the corresponding subband, 0
Reference numerals 31 to 31 are memories for storing subband data.

The mutual relationship and operation of the above components will be described below. This decoding process is just the reverse process of the coded array process. For simplification of explanation, 1 slot is 1
It has 6 bits, and the data array condition is the same as the data array shown in FIG. First, the control means inputs the data for one slot at the head of the frame (hereinafter referred to as encoded data) to the register 1 from the frame memory. For example, as shown in FIG. 15, 6-bit, 8-bit, and 2-bit array from MSB to LSB is input. Next, the contents of the register 1 are right-shifted by the number of bits "6" designated by the allocation data, and the overflowing bit data are sequentially stored from the MSB of the memory 0. By this processing, the memory 0 stores 6 bits of data of the subband 0. The control means inputs the following allocation data, that is, "8", and the 8-bit data of subband 1 is stored in the memory 1 in the same manner as the above processing. Next, the control means inputs the next allocation data “10”,
Register 1 is right-shifted and 2-bit data is stored in memory 2.
Becomes empty. At this point, the encoded data for the next one slot is input to the register 1, the remaining 8 bits designated by the allocation data are shifted with respect to the data, and the remaining 8 bits of data of the subband 2 are stored in the memory 2. Is stored. In this way, allocation data "1
One of the features is that the decoded signal is obtained from the 2-bit data of the first slot and the 8-bit data of the next slot with respect to "0", and may be obtained from the data that spans two or more slots. .

By repeating the above operation, the data of each subband is stored in each of the memories 0 to 31,
The decoding process ends. FIG. 16 is a schematic flowchart showing the above operation, but the operation is clear from the above description, and therefore the description is omitted. In the above description, the data of the audio signal has been described as an example, but other signals, for example, the data of the image signal can be compressed by applying the visibility limit.

[0024]

In such a conventional signal processing apparatus, there is a problem that the number of processing steps in the DSP or the like increases and the signal processing for generating the recording signal does not end within a predetermined time. there were. Also, DSP
Could not secure a sufficient period for executing other processing such as compression processing.

An object of the present invention is to solve the above problems, and an object thereof is to provide a signal processing apparatus which performs an encoding process and a decoding process with a hardware configuration independent of a microcomputer and having a high operation speed.

[0026]

In order to achieve the above object, the first object of the present invention is to provide a shift clock generating circuit for generating a shift clock and a pre-encoding data load pulse. An n-bit first shift register for shifting the set n-bit uncoded data in the MSB direction by the shift clock and bit data overflowed by the shift operation of the first shift register are sequentially input to the LSB. M by the shift clock
An m-bit second shift register that shifts in the SB direction and the shift clock are input, and a first stop signal is output at the number of clocks set by the allocation data.
A stop signal circuit for outputting a second stop signal at the same number of clocks as m, and after setting the allocation data in the stop signal circuit, the pre-encoding data corresponding to the allocation data is first shifted. When the shift clock generating circuit is set in the register and the shift clock generating circuit is activated, each time the shift clock is stopped by the first stop signal, the next set of allocation data and pre-encoding data is sequentially set to operate the shift clock. By sequentially setting a set of allocation data and pre-encoding data until the shift clock stops at the second stop signal,
The m-bit data string consisting of a plurality of arrays of data obtained by shortening the uncoded data to the number of bits designated by the allocation data is obtained in the second shift register, and
Is a signal processing device that outputs a stop signal as a ready signal indicating the end of encoding processing, and a second problem solving means of the present invention is a shift clock generation circuit that generates a shift clock, and an encoding An n-bit first shift register for shifting the n-bit encoded data set by the data load pulse in the MSB direction by the shift clock, and bit data overflowed by the shift operation of the first shift register are sequentially transferred to the LSB. A second shift register of m bits which is input and shifted in the MSB direction by the shift clock; a stop signal circuit which inputs the shift clock and outputs a stop signal at the number of clocks set by allocation data; And a clear circuit for clearing the shift register of After setting the allocation data to the stop signal circuit and activating the shift clock generation circuit after the shift signal is stopped by the stop signal, the data of the number of bits designated by the allocation data is converted into the encoded data. And the stop signal is output as a ready signal indicating the end of the decoding process, the data of the second shift register is read out as the decoded data in accordance with the ready signal, and then the second clear circuit is used by the clear circuit. A signal processing device for repeating the operation of clearing the shift register, setting the next allocation data, and obtaining the next decoded data, and the third problem solving means of the present invention generates a shift clock. Set with shift clock generation circuit and data load pulse The n-bit first shift register for shifting the generated n-bit data in the MSB direction by the shift clock and the bit data overflowed by the shift operation of the first shift register are sequentially input to the LSB, and the shift clock is used for the shift clock. The m-bit second shift register that shifts in the MSB direction, the allocation data load pulse and the data load pulse are input, and by the encoding / decoding switching signal,
A load select circuit that outputs a data load pulse during encoding processing and an allocation data load pulse during decoding processing as a start signal to the shift clock generation circuit, and the shift clock are input, and a first clock is set by the number of clocks set by the allocation data. Stop signal is output, and the second signal is output at the number of clocks equal to m during the encoding process.
A stop signal circuit for outputting the stop signal, and a first stop signal as a ready signal at the time of decoding processing, and a second stop signal as a ready signal at the time of encoding processing, which is switched by the encoding / decoding switching signal and output. Ready select circuit and second
Equipped with a clear circuit that clears the shift register, and sets a pair of allocation data and pre-encoded data in the stop signal circuit and the first shift register during the encoding process, and the shift clock is stopped by the first stop signal. Each time, the next set of allocation data and pre-encoding data is set, and when the shift clock is stopped by the second stop signal, the corresponding allocation data is designated from the n-bit pre-encoding data. A plurality of pieces of data shortened to the number of bits are arranged so as to fill the second shift register, and the encoded data is set in the first register during the decoding process, and then the allocation data is set in the stop signal circuit to shift clock. The number of bits specified by the allocation data when the generation circuit is started and the shift is stopped by the stop signal. The data is cut out from the encoded data and arranged in the second shift register, and after the data is read, the second shift register is cleared by the clear circuit, the next allocation data is set, and the ready A signal processing device, in which a signal indicates the end of encoding processing or decoding processing, and a fourth problem solving means of the present invention is a shift clock generation circuit for generating a shift clock, and an encoded data latch pulse. An n-bit latch for temporarily storing encoded data by means of the above, and an n-bit first shift for inputting n-bit encoded data from the n-bit latch by an encoded data load pulse and shifting in the MSB direction by the shift clock. The bit data overflowed by the shift operation of the register and the first shift register are sequentially LSB. An m-bit second shift register for inputting and shifting in the MSB direction by the shift clock; a stop signal circuit for inputting the shift clock and outputting a stop signal at the number of clocks set by allocation data; A stop signal circuit for inputting a clock and including a load signal circuit for generating the encoded data load pulse at n counts and a clear circuit for clearing a second shift register, and for stopping the allocation data by the allocation data load pulse When the shift clock generation circuit is started and the shift clock is stopped, data of the number of bits designated by the allocation data is cut out from the encoded data and arranged in the second shift register, and the stop is performed. Ready signal indicating the completion of signal processing And clears the second shift register from which the data has been read by the clear circuit, and immediately when the load signal circuit counts the shift clock by n, when there is no data in the first shift register, immediately. It is a signal processing device which generates a coded data load pulse and sets the next coded data from the n-bit latch to the first shift register.

[0027]

In the first problem solving means of the present invention, the uncoded data set in the n-bit first shift register is shifted in the MSB direction by the shift clock, and the overflowed bit data is the m-bit second data. Is input to the LSB of the shift register of
Shift in the B direction. Since the number of shift clocks is set in the allocation data by the stop signal circuit, the MSB side allocation data designated number of bit data of the pre-encoding data is transferred to the second shift register and the shift clock is stopped. By setting the pre-encoding data and the allocation data each time the shift clock is stopped, the MSB side data of the pre-encoding data having the number of bits designated by the allocation data are sequentially arranged in the second shift register. By the second stop signal of the stop signal circuit,
When m bit data are arranged in the second shift register, the shift clock is stopped, the arrangement of the encoded data of m bits is completed, and the ready signal is output.

In the second problem solving means, the encoded data set in the n-bit first shift register is shifted in the MSB direction by the shift clock, and the overflowed bit data is the m-bit second shift. It is input to the LSB of the register and the MS
Shift in the B direction. Since the number of shift clocks is set in the allocation data by the stop signal circuit, data of the number of bits designated by the MSB side allocation data in the encoded data is transferred to the second shift register and the shift clock is stopped. By setting the allocation data every time the shift clock is stopped, the MSB side data of the encoded data having the number of bits designated by the allocation data can be obtained in the second shift register. This is the variable length data of the subband corresponding to the allocation data. Also, a ready signal is obtained for each stop signal. This ready signal output indicates the end of processing, and the second shift register whose contents have been read based on it is cleared by the clear circuit.

In the third means for solving the problem, the encoded data set in the n-bit first shift register is shifted in the MSB direction by the shift clock, and the overflowed bit data is the m-bit second shift. The signals are sequentially input to the LSB of the register and are shifted in the MSB direction by the shift clock. The select circuit switches the allocation data load pulse and the encoded data load pulse according to the encoding process and the decoding process and supplies them to the shift clock generation circuit, so that the timing of the shift clock generation start is encoded and decoded. To deal with processing. The operations of the first shift register and the second shift register in the encoding process and the decoding process are the same as those in the first problem solving means and the second problem solving means. The second stop signal in the stop signal circuit is cut off by the encoding / decoding switching signal in the decoding process and does not occur.

In the fourth means for solving the problem, the n-bit latch temporarily latches the encoded data. At that time, when there is no data in the first shift register, the data load pulse immediately loads the encoded data from the latch to the first shift register, and when there is data in the first shift register, latches the data as it is. ing. Each time the allocation data is set by the allocation data load pulse, the shift clock is activated, and the MSB side data of the first shift register shifts to the second shift register by the designated number of bits of the allocation data. The load signal circuit counts the total number of shift clocks, and when the count reaches n, it indicates that all the data in the first shift register has been shifted.
The n-bit detection causes the load pulse generation circuit to generate a load pulse, sets the next encoded data latched in the n-bit latch in the first shift register, and shifts to the next decoding process.

[0031]

(Embodiment 1) A signal processing apparatus according to a first embodiment of the first problem solving means of the present invention will be described below with reference to the drawings.

The first means for solving the problems of the present invention relates to an encoding means for shortening the pre-encoding data of each subband and arranging them to obtain a recording signal. FIG. 1 is a block diagram showing the configuration of the signal processing apparatus of this embodiment. In the figure, 1 is a counter that sets allocation data, which is bit allocation information, at the timing of an allocation data load pulse, and counts down a shift clock that operates from the time of inputting a pre-encoding data load pulse. A stop signal generation circuit that outputs a stop signal for a predetermined period when 3 is reached, 3 is a logical sum circuit, 4 is a shift clock generation that gives a shift clock to the k-bit counter 6, the m-bit shift register 7, and the n-bit shift register 8. The circuit starts operation when the pre-encoding data load pulse is input, and stops operation when the stop signal is input. Reference numeral 5 is an m-bit detection circuit for detecting that the count of the k-bit counter 6 is m, 6 is a k-bit counter for counting the shift clock output from the shift-clock generation circuit 4, and 7 is an overflow of the n-bit shift register 8. An output is input to the LSB side, and an m-bit shift register that shifts in the MSB direction by the shift clock, 8 inputs pre-encoding data at the timing of a pre-encoding data load pulse, and shifts in the MSB direction by the shift clock. It is an n-bit shift register. The pre-encoding data set in the n-bit shift register 8 is the sample data to which the characteristics of the audio signal are applied as described above, and is not the original 24-bit sample data itself, but is specified by the allocation data. It is a signal that should be arranged by rounding down the LSB side to the number of bits. Therefore, the number of bits n of the n-bit shift register
Is to be large enough to store uncoded data.

The interrelationship and operation of the above components will be described below. FIG. 2 is a timing chart showing the operation of the signal processing apparatus of this embodiment. First, the first allocation data, which is bit allocation information, is set in the counter 1 in the 0 count state at the timing of the allocation data load pulse. FIG. 2 shows a state in which the first 5 bits of allocation data are set. At the timing of the pre-encoding data load pulse following that setting,
The first uncoded data is transferred to the n-bit shift register 8
And the shift clock generation circuit 4 starts the shift clock output operation. In this case, the pre-encoding data load pulse is also the start signal of the shift clock generation circuit, that is, the start signal.

The n-bit shift register 8 is sequentially shifted in the MSB direction by the shift clock, the overflow output is sequentially inputted to the LSB side of the m-bit shift register 7, and sequentially shifted in the MSB direction by the shift clock. In this process, when the counter 1 counts down the shift clock and finishes counting the number of counts equal to the first allocation data, that is, when the count reaches 0, a stop signal, that is, a stop signal is sent to the stop signal generation circuit 2. Output to the shift clock generation circuit. This stop signal stops the shift clock of the shift clock generation circuit 4, and at this point, m
The bit shift register 7 stores M of the unencoded data.
Bits corresponding to the first number of allocated bits after SB are stored.

Next, at the end of the stop signal, the next allocation data load pulse is generated, and at that timing, the second allocation data,
In FIG. 2, 6 bits are set in the counter 1, and the next second pre-encoding data is set in the n-bit shift register 8 at the timing of the pre-encoding data load pulse.
By the same shift operation as above, the second allocated bits after the MSB of the second uncoded data are stored on the LSB side of the m-bit shift register.

In the process of continuously performing the above operation, the k-bit counter 6 counts the total number of clocks after the start of the shift clock operation, and the m-bit detection circuit 5 waits for the count to become m. The detected stop signal is output to the shift register generation circuit 4 via the OR circuit 3. The time when the m-bit detection circuit 5 detects the m count is the time when all the m bits of the m-bit shift register 7 are filled with data. If the number of bits m is set to the number of bits in one slot, it means that a data string for one slot in which a plurality of variable-length sample data are arranged is obtained in the m-bit shift register 7. In FIG. 2, m = 8 is shown for simplification of the drawing. In this way, the stop signal of the m-bit counter 5 is also a ready signal that has been encoded for one slot. At the timing of this ready signal, the data of the m-bit shift register 7 is transferred to a predetermined position of a register (not shown) that stores a signal frame.

The control means such as a microcomputer or a digital signal processor detects the ready signal, generates a read signal, reads the data string from the m-bit shift register 7 through the gate buffer 10, and then the clear circuit. M bit shift register 7 by 9
Clear all bits of.

As described above, according to the signal processing apparatus of the first embodiment of the first problem solving means of the present invention, the first shift register for shifting the uncoded data in the MSB direction,
Bit data that overflows due to the shift operation is set to L
A second shift register for sequentially inputting to SB and shifting in the MSB direction is provided, and the number of clocks to be shifted is set by the allocation data corresponding to the pre-encoding data. A data string having the number of bits designated by the allocation data on the MSB side of the data, that is, variable length data is obtained, and a set of pre-encoding data and its allocation data is sequentially set and shifted each time the clock stops, and By providing a signal processing device that stops the clock at the time when the number of clocks becomes the number of bits of the second register and makes it possible to obtain an array of a plurality of variable-length sample data in the second shift register, By implementing an encoding processing device that consists of only hardware and allowing other processes to proceed simultaneously to the control means Miscellaneous signal processing can be made faster.

If all the bits of the m-bit shift register 7 are not filled with data after setting and shifting all the sets of allocation data and pre-encoding data, the remaining bits are bit data "0". The LSB
Shall be entered on the side. In this case, if the maximum value of the number of bits is given to the allocation data and the pre-encoding data with all bits set to "0" is set and the shift is performed, the shift stops while the m-bit shift register is filled.
It is possible to automatically fill the LSB side with "0" regardless of the number of bits in the remaining portion. Further, when the m-bit shift register in which all the bit data is “0” is required, the m-bit shift register 7 can be filled with zero by the clear signal.

(Second Embodiment) A signal processing apparatus according to a second embodiment of the first problem solving means of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram showing the configuration of the signal processing apparatus of this embodiment. The same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. The difference of the present embodiment from the first embodiment is that the stop signal circuit 21 detects the case where the bit number information given by the allocation data has a special meaning and prohibits the generation of variable length data of the allocation data. The stop signal circuit 21 detects the prohibition information, for example, when the allocation data in the first embodiment is 0000 and the generation of the variable length data is prohibited. In FIG. 3, the stop signal circuit 21 includes a prohibition information detection circuit 9 and an AND circuit 10 that stops the shift clock according to the detection signal. Since the bit allocation of 0 bits means that no data is required, this embodiment is a signal processing device corresponding to a means for reducing the number of bits by omitting recording of the data.

In FIG. 3, the allocation data set in the counter 1 is bit allocation information, and
In the case of variable length sample data generation prohibition information, the J detection circuit 11 detects prohibition information and inputs a detection signal to the logical product circuit 12 via the inverter 13. Disconnect the shift clock output. Therefore, the pre-encoding data corresponding to the allocation data is not shifted, and m
The variable length sample data is not input to the bit shift register. Also, since the shift clock is stopped, the next set of allocation data and pre-encoding data is set and the shift operation starts. Other operations are the same as those in the first embodiment.

As described above, according to the signal processing apparatus of the second embodiment of the first problem solving means of the present invention, the shift clock is stopped by detecting that the allocation data is the variable length sample data generation prohibition information. By using the signal processing device having the stop signal circuit provided with the means for outputting the signal, it is possible to generate the encoded data that does not include the variable length data corresponding to the allocation data giving the prohibition information.

(Third Embodiment) A signal processing apparatus according to the first embodiment of the second means for solving the present invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing the configuration of the signal processing apparatus of this embodiment, and FIG. 5 is a timing chart showing the operation of the signal processing apparatus of this embodiment. A second means for solving the problem of the present invention relates to a decoding means for obtaining data of each subband from encoded data of a reproduction signal. The same components as those of the first and second embodiments are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 4, the n-bit shift register 8
1 slot of encoded data is set by the encoded data load pulse. Next, the leading one of the allocation data arranged in the allocation data area of the signal frame is set in the counter 1 by the allocation data load pulse, and the shift operation of the shift clock generation circuit 4 is started. The encoded data of the n-bit shift register 8 is MSB by the shift clock.
Bit data that has been shifted in the direction
The bits are sequentially input to the LSB of the bit shift register 7 and are shifted in the MSB direction by the shift clock. When the counter 1 finishes counting the number of bits given by the allocation data, the stop signal generation circuit outputs a stop signal to the shift clock generation circuit 4, the shift clock stops, and the shift operation stops. At this point, the LSB side of the m-bit shift register is in a state in which the data of the number of bits designated by the allocation data of the encoded data is input. The arrangement order of the variable-length data in the encoded data is the same as the arrangement order of the allocation data, and the number of data bits is also the number of bits specified by the allocation data. Therefore, the data obtained in the m-bit shift register 7 Is nothing but the variable length sample data of the subband corresponding to the allocation data.

Therefore, the stop signal is output as a ready signal indicating that the variable-length sample data of the subband has been obtained, and a control circuit (not shown) by the DSP or the like which has detected it outputs a read signal, and m The data in the bit shift register 7 is read out through the gate buffer 10, and the clearing circuit 9 clears all bits of the m-bit shift register 7 to zero. After reading the variable length sample data, the allocation data of the next array is set in the counter 1, and similarly the variable length sample data of the next subband is obtained. Repeat this operation,
When all the bits of the encoded data for one slot have been divided into variable-length sample data, the next encoded data for one slot is set in the n-bit shift register and the same operation is repeated to encode all the frames. The data can be decoded into variable length sample data.

As described above, according to the signal processing apparatus of the first embodiment of the second problem solving means of the present invention, the n-bit coded data set by the coded data load pulse is MSB by the shift clock. The first shift register of n bits that shifts in the direction and the bit data overflowed by the shift operation of the first shift register are sequentially LSB.
A second shift register of m bits that is input to the shift clock and shifts in the MSB direction by the shift clock, a shift clock generation circuit that generates the shift clock, and the number of clocks set by the allocation data by inputting the shift clock. And a stop signal circuit for outputting a stop signal at the first shift register, and after setting the encoded data in the first shift register, setting allocation data in the stop signal circuit and activating the shift clock generation circuit, Each time the stop signal is stopped, the next allocation data is sequentially set and the shift clock is operated to obtain the decoded data of the number of bits designated by the allocation data in the second shift register, and the stop signal is decoded. Signal to be output as the ready signal of With management device, to achieve decryption processing apparatus configured only by hardware, can speed the complex signal processing by simultaneously another process to the control unit.

(Fourth Embodiment) A signal processing apparatus according to a second embodiment of the second problem solving means of the present invention will be described below with reference to the drawings. FIG. 6 is a block diagram showing the configuration of the signal processing apparatus of this embodiment. The same components as those in the third embodiment are designated by the same reference numerals and the description thereof will be omitted. The present embodiment is a decoding means corresponding to the second embodiment, and is such that when the allocation data gives prohibition information, zero data is output from the second shift register. That is, since the variable length data corresponding to the prohibition information is not included in the encoded data, the shift operation is stopped in that case, and the zero data set by the clear signal is read after the previous reading. in this case,
The prohibition information detection circuit 11 detects the prohibition information of the allocation data, inputs the detection signal to the AND circuit 12, and stops the shift clock output. Also, the OR circuit 13
Inputs a stop signal and a prohibition information detection signal, and outputs a ready signal to both. The other operation is the third embodiment.
The description is omitted here.

As described above, according to the signal processing apparatus of the second embodiment of the second problem solving means of the present invention, the shift clock is stopped by detecting that the allocation data is the variable length sample data generation prohibition information. By using the signal processing device having the stop signal circuit provided with the means for outputting a signal, it is possible to perform a decoding process which does not output the variable length data which is the decoded data corresponding to the allocation data giving the prohibition information.

(Fifth Embodiment) A signal processing circuit according to an embodiment of the third means for solving the problems of the present invention will be described below with reference to the drawings. FIG. 7 is a block diagram showing the configuration of the signal processing apparatus of this embodiment. The present embodiment relates to a signal processing apparatus capable of switching between and executing a coding process of converting uncoded data into variable length data and arranging it, and a decoding process of obtaining subband variable length data from the coded data.

As described in Examples 1 to 4,
The encoding signal processing device and the decoding signal processing device have common components. Therefore, it is possible to realize a signal processing device that can execute the switching between the encoding process and the decoding process by effectively utilizing this common component.

Comparing the encoding signal processing circuit shown in FIG. 1 with the decoding signal processing circuit shown in FIG. 4, the counter 1, the stop signal generating circuit 2, the shift clock generating circuit 4, and the second shift are shown. The register 7, the n-bit shift register 8 and the clear circuit 9 are common constituent elements. on the other hand,
As is clear by comparing the timing chart showing the operation of the encoding process shown in FIG. 2 with the timing chart showing the operation of the decoding process shown in FIG. 5, in the encoding process, the allocation data is first counted. 1 is set, then the uncoded data is set in the n-bit shift register to shift to the shift operation. In the decoding process, the coded data is set in the first shift register first, and the allocation is performed. The shift operation is executed according to the data setting. That is, there is a difference in whether the start timing of the shift operation is the timing of the pre-encoding data load pulse or the timing of the allocation data load pulse.

In the encoding process, the shift clock is stopped by the number of clocks specified by the allocation data and the number of clocks at the time when the second shift register is filled, but in the decoding process, only the stop by the allocation data is required. Further, in the encoding process, the stop signal due to the allocation data is used as the ready signal, and in the decoding process, the m-bit detection signal is used as the ready signal.

Therefore, a device for switching between encoding and decoding by one device is a device for switching the start timing of the shift clock, switching means for the stop signal, and switching the ready signal to the encoding device or the decoding device. It can be realized by providing a means. In FIG. 7, the load select circuit 18 is a switching means for switching between the allocation data load pulse and the data load pulse and inputting them to the shift register. That is, the allocation data load pulse and the data load pulse are input, the pre-encoding data load pulse is connected to the shift register generation circuit in the encoding process by the encoding / decoding switching signal, and the allocation data in the decoding process. The load pulse is connected to the shift register generation circuit. Further, the logical product circuit 19 is the m-bit detection circuit 5
Since the second stop signal due to is unnecessary for the decoding process,
It is a switching means for disconnecting in the case of the decoding process by the encoding / decoding switching signal. The ready select circuit 20 is a switching means for switching between the second stop signal for m-bit detection in the encoding process and the stop signal by the allocation data in the decoding process to obtain a ready signal.

In the above-mentioned structure, the apparatus shown in FIG. 7 performs the switching operation by the encoding / decoding switching signal,
The encoding processing is substantially the same as the signal processing apparatus shown in FIG. 1, and the decoding processing is substantially the same as the signal processing apparatus shown in FIG. The operations of the encoding process and the decoding process have been described in the other embodiments, and thus the description thereof will be omitted.

As described above, according to the signal processing apparatus of the present embodiment, the allocation data load pulse and the pre-encoding data load pulse are switched by the encoding / decoding switching signal and the operation start signal of the shift clock generating circuit is set. Switching means, switching means for preventing a shift clock stop signal when the m-bit shift register is filled with data from being output at the time of decoding, and a stop signal for allocating data and a stop signal for detecting m bits to obtain a ready signal. By using the signal processing device having the stop signal circuit provided with the switching means for switching, it is possible to realize a signal processing device that can perform encoding processing and decoding processing by sharing a large number of common components. It is not necessary to provide each decoding processing device independently, and the configuration of the signal processing device is There is an effect to simplify to.

(Embodiment 6) A signal processing apparatus according to an embodiment of the fourth problem solving means of the present invention will be described below with reference to the drawings. FIG. 8 is a block diagram showing the configuration of the signal processing apparatus of this embodiment. The same components as those in the third embodiment are designated by the same reference numerals and the description thereof will be omitted. This embodiment relates to means for efficiently setting allocation data and encoded data in demodulation means. In the signal processing means for decoding shown in the fourth embodiment, the next encoded data cannot be set in the n-bit shift register 8 until all the encoded data in the n-bit shift register 8 have been shifted. However, depending on the convenience of the processing operation of the control means, for example, DSP, the operation of setting the next encoded data at the completion of the shift operation may be inconvenient in relation to other processing. It is preferable that the encoded data can be set in the n-bit shift register 8 regardless of completion. The present embodiment is means for solving the above problems. The difference between this embodiment and Embodiment 4 is that
An n-bit latch 14 that temporarily stores n-bit encoded data at the timing of an encoded data latch pulse, an n-bit counter 15 that counts shift clocks, and a timing at which the n-bit counter counts n shift clocks A load pulse generation circuit 16 for generating a load pulse for setting the data of the bit latch 14 in the n-bit shift register 8 and a clear signal for clearing the n-bit counter at the timing of generating the load pulse. Clear signal generation circuit 17
It is equipped with and.

The mutual relationship and operation of the above configurations will be described below. The encoded data is temporarily set in the n-bit latch 14 by the encoded data load pulse and temporarily stored. At this time, when there is no data in the n-bit shift register 8, the load pulse generation circuit 16 immediately generates a load pulse at the next clock and loads the data in the latch into the first shift register. However, when there is data in the n-bit shift register 8, the load pulse is not generated and the encoded data data remains held in the latch 14. Next, the allocation data load pulse is counted by the counter 1 to start the shift operation.
And set the allocation data,
It is input to the shift clock generation circuit 4 to generate a shift clock. The n-bit shift register 8 and the m-bit shift register 7 perform the same operation as that of the fourth embodiment to store m-bit variable-length sample data in the m-bit shift register and read it to the data bus by a read signal. By repeating this operation, the n-bit counter 15
When n has counted n shift clocks is the time when all the data in the n-bit shift register 8 have been shifted. At this point, the n-bit counter 15 causes the load pulse generation circuit 16 to generate a load pulse, and the encoded data already stored in the n-bit latch 14 is set in the n-bit shift register 8. Also, at this timing, the n-bit counter 15 is cleared by the clear signal generation circuit 17.

As described above, according to the signal processing device of the fourth embodiment of the present invention, the data in the n-bit latch for temporarily latching the encoded data and the data in the n-bit shift register become empty. And a load pulse generation circuit for generating a load pulse for immediately setting the encoded data latched in the n-bit shift register when the detection result or the n-bit shift register is empty. By using the signal processing device including the above, the encoded data is set in the n-bit latch at an arbitrary timing, and the next encoding is performed at the timing when the shift operation by the allocation data progresses and all bits become empty. The data is automatically set in the n-bit shift register, and the control means sets the next code according to the completion of the shift operation. Data it is not necessary to set the n-bit shift register, is effective in the case of parallel processing of the signal processing.

Although the above embodiment is a case of decoding processing, the pre-encoding data is latched in the n-bit latch and the load pulse is generated every time the n-bit counter 15 counts m shift clocks. If the pre-encoding data of the n-bit latch is set in the first shift register by the load pulse, the timing for setting the pre-encoding data in the first shift register can be simplified by the same operation as above. It is possible to obtain the signal processing device for the encoding process.

[0060]

As is apparent from the above embodiments, according to the signal processing device of the first means for solving the problems of the present invention, the shift clock generating circuit for generating the shift clock and the pre-encoding data load pulse are used. An n-bit first shift register for shifting the set n-bit uncoded data in the MSB direction by the shift clock and bit data overflowed by the shift operation of the first shift register are sequentially input to the LSB. An m-bit second shift register that shifts in the MSB direction by the shift clock and the shift clock are input, a first stop signal is output at the number of clocks set by allocation data, and the number of clocks equal to m And a stop signal circuit for outputting a second stop signal at the stop signal circuit. After the setting, the pre-encoding data corresponding to the allocation data is set in the first shift register and the shift clock generation circuit is activated, and the next allocation data is generated every time the shift clock is stopped by the first stop signal. And the pre-encoding data are sequentially set to operate the shift clock, and the sets of the allocation data and the pre-encoding data are sequentially set until the shift clock is stopped by the second stop signal. While obtaining in the second shift register an m-bit data string consisting of a plurality of arrays of data obtained by shortening the previous data to the number of bits specified by the allocation data,
By using the signal processing device configured to output the second stop signal as the ready signal indicating the end of the encoding process,
It is possible to realize a signal processing circuit for encoding processing with a hardware configuration that does not depend on the program processing of the control device by a DSP or the like, reduce the processing load on the control device, and execute the encoding processing at high speed by sharing the signal processing. There is an effect.

According to the signal processing device of the second means for solving the problems of the present invention, the shift clock generating circuit for generating the shift clock and the n-bit coded data set by the coded data load pulse are stored in the signal processor. An n-bit first shift register that shifts in the MSB direction by a shift clock, and bit data that overflows by the shift operation of the first shift register are sequentially input to the LSB, and an m-bit shift register that shifts in the MSB direction by the shift clock. A second shift register, a stop signal circuit that inputs the shift clock and outputs a stop signal at the number of clocks set by allocation data, and a clear circuit that clears the second shift register are provided. After setting the data in the first shift register, stop the allocation data When the shift clock generation circuit is activated and the shift clock is stopped by the stop signal, the data of the number of bits designated by the allocation data is cut out from the encoded data and obtained in the second shift register. The stop signal is output as a ready signal indicating the end of the decoding process, the data in the second shift register is read out as the decoded data in accordance with the ready signal, and then the second shift register is cleared by the clear circuit to obtain the next allocation data. By setting the signal processing device to repeat the operation of setting and obtaining the next decoded data, it is possible to realize the signal processing circuit of the encoding process of the hardware configuration, which does not depend on the program process of the control device by the DSP, Reducing the processing load of the control device and sharing the signal processing There is an effect that can perform decoding processing at a high speed by the.

According to the signal processing device of the third means for solving the problems of the present invention, the shift clock generating circuit for generating the shift clock and n set by the data load pulse.
An n-bit first shift register for shifting bit data in the MSB direction by the shift clock;
Bit data overflowed by the shift operation of the shift register are sequentially input to the LSB, and an m-bit second shift register for shifting in the MSB direction by the shift clock, an allocation data load pulse and a data load pulse are input, and a code A load select circuit that outputs a data load pulse during encoding processing and an allocation data load pulse during decoding processing as a start signal to the shift clock generation circuit by the encoding / decoding switching signal, and the shift clock are input and set by allocation data. A stop signal circuit that outputs the first stop signal at the number of clocks that are generated and that outputs the second stop signal at the number of clocks that is equal to the number m at the time of encoding processing, and the ready signal at the time of decoding the first stop signal. , Ready for encoding the second stop signal A ready selection circuit for outputting switching by the encoding and decoding switching signal as No.,
A clear circuit for clearing the second shift register,
At the time of encoding processing, a set of allocation data and pre-encoding data is set in the stop signal circuit and the first shift register respectively, and the next allocation data and pre-encoding are set every time the shift clock is stopped by the first stop signal. When a set of data is set and the shift clock is stopped by the second stop signal, a plurality of pieces of data reduced from the n-bit uncoded data to the number of bits designated by the corresponding allocation data are generated. After the second shift register is filled and arranged, the encoded data is set in the first register during the decoding process, the allocation data is set in the stop signal circuit to activate the shift clock generation circuit, and the shift signal is used to shift. At the time of stopping, the data of the number of bits designated by the allocation data is cut out from the encoded data, After the data is read out in the shift register, the second shift register is cleared by the clear circuit, the next allocation data is set, and the ready signal indicates the end of the encoding process or the decoding process. By using the signal processing device
It is possible to realize a signal processing circuit for encoding and decoding with a hardware configuration that does not rely on the program processing of the control device by a DSP or the like, reduce the processing load on the control device, and share the signal processing to perform the encoding and decoding processing. It can run fast,
Furthermore, there is an effect that the configuration of the device can be simplified by performing the encoding process and the decoding process by utilizing common components.

Further, according to the signal processing apparatus of the fourth problem solving means of the present invention, a shift clock generating circuit for generating a shift clock, and an n-bit latch for temporarily storing the encoded data by the encoded data latch pulse. , N-bit encoded data is input from the n-bit latch with an encoded data load pulse, and the MS is output with the shift clock.
An n-bit first shift register that shifts in the B direction, and bit data that overflows due to the shift operation of the first shift register are sequentially input to the LSB, and an m-bit second shift register that shifts in the MSB direction by the shift clock.
Shift register, a stop signal circuit that inputs the shift clock and outputs a stop signal at the number of clocks set by allocation data, and the shift clock that inputs the encoded data load pulse at n counts. A load signal circuit and a clear circuit for clearing a second shift register are provided, and the allocation data load pulse sets the allocation data in the stop signal circuit and activates a shift clock generation circuit to stop the shift clock. At this point, the allocation data is obtained by cutting out the data of the specified number of bits from the encoded data and arranging it in the second shift register, outputting the stop signal as a ready signal indicating the completion of processing, and reading the data. The second shift register is cleared the above times When there is no data in the first shift register when the load signal circuit counts the shift clock by n, an encoded data load pulse is immediately generated to output the next encoded data from the n-bit latch. By using the signal processing device that is set in the first shift register, it is possible to realize a signal processing circuit for encoding with a hardware configuration that does not depend on the program processing of the control device by a DSP or the like, and the processing load of the control device is increased. The encoding process can be executed at a high speed by reducing the number of times, and the signal processing is shared, and it is necessary to match the timing of setting the pre-encoding signal in the n-bit shift register with the timing when the n-bit shift register is just empty. Since it does not exist, the degree of freedom in control is increased, and signal processing can be made more efficient.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a signal processing device according to a first embodiment of a first problem solving means of the present invention.

FIG. 2 is a timing chart showing the operation of the signal processing apparatus of the first embodiment of the first problem solving means of the present invention.

FIG. 3 is a block diagram showing a configuration of a signal processing device according to a second embodiment of the first problem solving means of the present invention.

FIG. 4 is a block diagram showing a configuration of a signal processing device according to a first embodiment of a second problem solving means of the present invention.

FIG. 5 is a timing chart showing the operation of the signal processing apparatus of the first embodiment of the second problem solving means of the present invention.

FIG. 6 is a block diagram showing the configuration of a signal processing device according to a second embodiment of the second problem solving means of the present invention.

FIG. 7 is a block diagram showing a configuration of a signal processing device according to an embodiment of a third problem solving means of the present invention.

FIG. 8 is a block diagram showing a configuration of a signal processing device according to an embodiment of a fourth problem solving means of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional signal processing device.

FIG. 10 is a schematic diagram showing a state in which an audio signal is divided into subband signals.

FIG. 11 is a characteristic diagram showing an example of minimum audibility limit characteristics and bit allocation.

FIG. 12 is a schematic diagram showing the structure of a signal frame.

FIG. 13 is a schematic diagram showing a process of conventional coded signal processing by a digital signal processor.

FIG. 14 is a flowchart showing the operation of conventional coded signal processing by the digital signal processor.

FIG. 15 is a schematic diagram showing a process of conventional decoded signal processing by a digital signal processor.

FIG. 16 is a flowchart showing the operation of conventional decoded signal processing by the digital signal processor.

[Explanation of symbols]

 4 shift clock generation circuit 7 m-bit shift register (second shift register) 8 n-bit shift register (first shift register) 21 stop signal circuit 22 allocation data input terminal 23 allocation data load pulse input terminal 24 pre-encoding data Load pulse input terminal 25 Pre-encoded data input terminal 26 Ready signal output terminal 27 Encoded data output terminal

Claims (11)

[Claims] 1. A shift clock generation circuit for generating a shift clock, and an n-bit first shift for shifting n-bit pre-encoding data set by a pre-encoding data load pulse in the MSB direction by the shift clock. A register, an m-bit second shift register for sequentially inputting bit data overflowed by the shift operation of the first shift register to the LSB, and shifting in the MSB direction by the shift clock, and the shift clock are input, and allocation is performed. A stop signal circuit that outputs a first stop signal at a clock number set by data and a second stop signal at a clock number equal to the m, and the allocation data is set in the stop signal circuit. After that, the pre-encoding data corresponding to the allocation data is set to the first shift register. The shift clock generation circuit is activated and the shift clock generation circuit is activated, and each time the shift clock is stopped by the first stop signal, the next set of allocation data and pre-encoding data is sequentially set to operate the shift clock. A plurality of arrays of data in which the pre-encoding data is shortened to the number of bits designated by the allocation data by sequentially setting a set of allocation data and pre-encoding data until the shift clock is stopped by the second stop signal. A signal processing device configured to obtain an m-bit data string consisting of the following in a second shift register and output a second stop signal as a ready signal indicating the end of encoding processing. 2. A first counter for inputting allocation data as a preset value, and a stop signal generation circuit for outputting a stop signal when the first counter counts the preset value by a shift clock.
A second counter for counting the shift clock;
An m-bit detection circuit that outputs a stop signal when the second counter counts m shift clocks, and the stop signal output from the stop signal generation circuit is the first stop signal and the m-bit detection circuit. The signal processing device according to claim 1, further comprising a stop signal circuit that outputs the stop signal as a second stop signal and a ready signal. 3. A first counter for inputting allocation data as a preset value, and a stop signal generation circuit for outputting a stop signal when the first counter counts the preset value by a shift clock,
A prohibition information detection circuit that outputs a stop signal when the allocation data is prohibition information, a second counter that counts the shift clock, and a stop signal that is output when the second counter counts m shift clocks. And a m-bit detection circuit that outputs a first stop signal by a logical sum of a stop signal output from the stop signal generation circuit and a stop signal output from the prohibition information detection circuit. The signal processing device according to claim 1, further comprising a stop signal circuit that outputs the stop signal as a second stop signal and a ready signal. 4. A shift clock generation circuit for generating a shift clock, and n bits of coded data set by a coded data load pulse are M by the shift clock.
An n-bit first shift register that shifts in the SB direction and bit data that overflows due to the shift operation of the first shift register are sequentially input to the LSB, and the m-bit second shift register that shifts in the MSB direction by the shift clock.
Shift register, a stop signal circuit that inputs the shift clock and outputs a stop signal at the number of clocks set by allocation data, and a clear circuit that clears the second shift register. First
Setting the allocation data in the stop signal circuit and starting the shift clock generation circuit, and when the shift clock is stopped by the stop signal, the data of the number of bits designated by the allocation data is stored in the code register. From the encoded data, obtains it in the second shift register, outputs a stop signal as a ready signal indicating the end of the decoding process, reads the data of the second shift register as the decoded data in accordance with the ready signal, and then uses the clear circuit A signal processing device for repeating the operation of clearing the second shift register, setting the next allocation data, and obtaining the next decoded data. 5. A stop signal stop circuit is provided, comprising: a counter for inputting allocation data as a preset value; and a stop signal generation circuit for outputting a stop signal when the counter counts the preset value by a shift clock. The signal processing device according to claim 4, further comprising a stop signal circuit that outputs a signal and a ready signal. 6. A counter for inputting allocation data as a preset value, a stop signal generating circuit for outputting a stop signal when the counter counts the preset value by a shift clock, and the allocation data for prohibition information. A prohibition information detection circuit that outputs a stop signal at a certain time is provided, and a stop signal is output by a logical sum of the stop signal output by the stop signal generation circuit and the stop signal output by the prohibition information detection circuit, and the prohibition information is output. The signal processing device according to claim 4, wherein the zero data of the second shift register, which is cleared by the clear circuit, is read. 7. A shift clock generation circuit for generating a shift clock, an n-bit first shift register for shifting n-bit data set by a data load pulse in the MSB direction by the shift clock, and a first shift register. Bit data overflowed by the shift operation of the shift register is sequentially input to the LSB and an m-bit second shift register that shifts in the MSB direction by the shift clock, an allocation data load pulse and a data load pulse are input, and encoding is performed.・ A load select circuit that outputs a data load pulse during encoding processing and an allocation data load pulse during decoding processing as a start signal to the shift clock generation circuit by the decoding switching signal, and the shift clock are input and set by allocation data. Ru A stop signal circuit that outputs a first stop signal at the number of clocks and a second stop signal at the number of clocks equal to m at the time of encoding; a ready signal at the time of decoding the first stop signal; A ready select circuit for switching and outputting the stop signal of No. 2 as a ready signal at the time of encoding by the encoding / decoding switching signal, and a clear circuit for clearing the second shift register, and allocation data at the time of encoding. The set of pre-encoding data is set in the stop signal circuit and the first shift register respectively, and each time the shift clock is stopped by the first stop signal, the next set of allocation data and pre-encoding data is set. Then, when the shift clock is stopped by the second stop signal, the n-bit uncoded data is designated by the corresponding allocation data. A plurality of pieces of data shortened to the number of bits are arranged to fill the second shift register, and the encoded data is set in the first register during the decoding process, and then the allocation data is set in the stop signal circuit and shifted. When the clock generation circuit is activated and the shift is stopped by the stop signal, the data of the number of bits designated by the allocation data is cut out from the encoded data and arranged in the second shift register, and the data is read out. After that, the second shift register is cleared by the clear circuit, the next allocation data is set, and the ready signal indicates the end of the encoding process or the decoding process. 8. A first counter that inputs allocation data as a preset value, and a stop signal generation circuit that outputs a stop signal when the first counter counts the preset value by a shift clock.
A second counter for counting the shift clock;
An m-bit detection circuit that outputs a stop signal when the second counter counts m shift clocks, and a stop signal that is output from the m-bit detection circuit is output by an encoding / decoding switching signal only during encoding processing. 8. A stop signal circuit comprising switching means, wherein the stop signal output from said stop signal generating circuit is a first stop signal, and the stop signal output from said switching means is a second stop signal.
The signal processing device described. 9. A stop signal circuit, wherein the stop signal circuit comprises a prohibition information detection circuit for detecting prohibition information indicated by allocation data, and which outputs a first stop signal for the count number and prohibition information designated by the allocation data. The signal processing device according to claim 7, further comprising: 10. A shift clock generation circuit for generating a shift clock, an n-bit latch for temporarily storing encoded data by an encoded data latch pulse, and an n-bit encoding from the n-bit latch by an encoded data load pulse. Input data and MSB by the shift clock
An n-bit first shift register that shifts in the direction,
Bit data overflowed by the shift operation of the first shift register is sequentially input to the LSB and the m-bit second shift register that shifts in the MSB direction by the shift clock and the shift clock are input and set by allocation data. A stop signal circuit that outputs a stop signal at the number of clocks that are input, and the shift clock,
A load signal circuit for generating the encoded data load pulse with n counts and a clear circuit for clearing a second shift register are provided, and the allocation data is set and stopped in the stop signal circuit by the allocation data load pulse. When the clock generation circuit is activated and the shift clock is stopped, data of the number of bits designated by the allocation data is cut out from the encoded data and arranged in the second shift register, and the stop signal is processed. When the second shift register, which is output as a ready signal indicating that the data is read, is cleared by the clear circuit and the load signal circuit counts the shift clock by n, there is no data in the first shift register. Immediately issue a coded data load pulse Signal processing apparatus from the n-bit latch to set the next encoded data into the first shift register with. 11. An n-bit counter for inputting a shift clock to count n bits, and a load pulse generation for immediately generating a data load pulse when there is no data in the first shift register when the n bits are counted. The circuit and the encoded data load pulse
The signal processing device according to claim 10, further comprising a load signal circuit having a clear signal generation circuit that generates a clear signal for the bit counter.