JPH06217580A - Motor control circuit - Google Patents

Abstract

PURPOSE:To improve transient responsiveness during a period from a rotational phase is unlocked until it is locked again. CONSTITUTION:A signal detector 1 separates a phase detection signal and speed detection signal from a rotation detection signal obtained from a speed/ phase detector 12 and outputs a speed detection signal to a speed synchronous measuring unit 5 and to a phase-difference measuring unit 2 as a phase detection signal. The phase-difference measuring unit 2 detects the phase difference between a speed detection signal and vertical synchronous signal, and outputs it to a comparator 3. The comparator 3 prepares a phase error signal by comparing the phase differences with target phases read out of a memory 4 in the generation order of speed detection signals, and outputs the phase error signal to a mixer 8. Thus, the rotational phase of a cylinder motor 11 is controlled by speed detection signals (two or more speed detection signals are generated per rotation of the cylinder motor 11) to improve the transient responsiveness and accuracy of rotational phase control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor control circuit for rotating a cylinder motor for driving a rotating cylinder equipped with a head used in a video tape recorder (VTR).

[0002]

2. Description of the Related Art Conventionally, in a VTR in which a magnetic tape is helically scanned to record and reproduce a video signal, a magnetic head is arranged on the outer periphery of a cylinder, and the cylinder is rotated to run the video on the magnetic tape. It has a configuration for recording / reproducing a signal. The rotation control of the cylinder motor that rotates the cylinder is performed as described below. That is, after separately obtaining the speed detection signal and the phase detection signal of the cylinder motor, the speed detection signal is detected to generate a speed error signal, and the phase detection signal is detected to create a phase error signal. By rotating the cylinder motor according to the control signal obtained by mixing the above, the cylinder motor is driven at a predetermined rotation speed and rotation phase.

In recent years, the speed detection signal and the phase detection signal of the cylinder motor are superimposed and integrated into a single unit as shown in FIG.
The detection signal is as shown in FIG. Figure 3 (B)
In the figure, 31 indicates a phase detection signal, and 32 indicates a speed detection signal. Such a detection signal is obtained from a detector or the like capable of simultaneously detecting the rotation speed and the phase of the motor, and the phase detection signal 31 is 1 for each rotation of the motor.
6 are generated, and 6 speed detection signals 32 are generated between the phase detection signals 31.

By the way, when the rotation phase of the cylinder motor is locked, the vertical synchronizing signal 100 shown in FIG. 3A and the phase detection signal 31 shown in FIG. 3B have the relationship shown in FIG. It is fixed to. However, when the phase lock is deviated due to the switching of the broadcast receiving channel or the switching to the video camera, only one phase detection signal 31 is generated every one rotation of the cylinder motor as described above. There is a drawback that the phase detection is delayed until the phase detection signal 31 arrives, and accordingly, it takes a long time to apply the phase lock. Incidentally, FIG. 3 (C)
Is a phase target value when locking the rotation phase of the cylinder motor.

[0005]

As described above, when the detection signal in which the speed detection signal and the phase detection signal are unified is used for the speed and phase control of the cylinder motor, the phase detection signal is used as the cylinder motor. Since only one is generated for every one rotation, if the rotation phase lock is deviated due to channel switching of the broadcast reception program, phase detection will be delayed until the next phase detection signal arrives, so phase lock will be re-established. However, there is a drawback in that the transient period until it takes a long time becomes long and the transient response is not good.

In view of the above, the present invention eliminates the above-mentioned drawbacks, and even when a detection signal obtained by superimposing a speed detection signal and a phase detection signal and using a single detection signal, the rotation phase lock is shifted until it is locked again. It is an object of the present invention to provide a motor control circuit having a good transient response by minimizing the transient period.

[0007]

According to the present invention, there is provided a speed control system for controlling the rotation speed of a motor based on a speed error signal obtained by speed detection of a speed detection signal corresponding to the rotation speed of the motor, and a motor. In a motor control circuit comprising a phase control system for controlling the rotational phase of the motor based on a phase error signal obtained by phase-detecting a phase detection signal corresponding to the rotational phase of A separation circuit for separating the speed detection signal and the phase detection signal from the detection signal formed by superimposing the measurement signal, a measurement circuit for obtaining the phase difference between the speed detection signal and the reference signal separated by the separation circuit, and this measurement circuit. A determination circuit that determines the order in which the input speed detection signal is generated based on the phase detection signal, and the phase difference obtained by the measurement circuit are separately supplied. To a comparison circuit that creates the phase error signal by comparing the phase target value with a phase target value corresponding to the order determined by the determination circuit of the speed detection signal input to the measurement circuit. And a target value supply circuit for supplying the target value.

[0008]

In the motor control circuit of the present invention, the separation circuit separates the speed detection signal and the phase detection signal from the detection signal formed by superposing the speed detection signal and the phase detection signal. The measurement circuit obtains the phase difference between the speed detection signal separated by the separation circuit and the reference signal. The determination circuit determines the order in which the speed detection signal input to the measurement circuit is generated based on the phase detection signal. The comparator circuit compares the phase difference obtained by the measuring circuit with a phase target value separately supplied to generate the phase error signal. The target value supply circuit supplies a phase target value corresponding to the order in which the speed detection signal input to the measurement circuit is determined by the determination circuit to the comparison circuit. With the above operation, since a plurality of speed detection signals generated during one rotation of the motor are used as the phase detection signals, when the rotation phase lock is deviated, the phase detection is immediately delayed without delaying the phase detection. You will be able to lock in.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a motor control circuit of the present invention. Reference numeral 1 denotes a signal detector that separates the phase detection signal and the speed detection signal from the rotation detection signal of the cylinder motor 11 input from the speed / phase detector 12, and then performs processing for converting the speed detection signal into the phase detection signal. A speed detection signal (used as a phase detection signal) input from the signal detection unit 1 and a vertical synchronization signal 10 separately input
A phase difference measuring unit 3 for measuring a phase difference from 0, and a comparing unit 4 for comparing the phase difference input from the phase difference measuring unit 2 with a phase target value given from the memory unit 4 to obtain a phase error signal. Is a memory unit that stores a different phase target value for each speed detection signal output from the signal detection unit 1, 5 is a speed cycle measurement unit that measures the cycle of the speed detection signal input from the signal detection unit 1, 6 Is a comparison unit that compares the speed cycle input from the speed cycle measurement unit 5 with a target value to obtain a speed error signal, 7 is a gain compensation filter unit that compensates the gain of the input speed error signal, and 8 is a speed A mixing unit that mixes an error signal and a phase error signal to generate an error signal, 9
Is a DC compensation filter unit for compensating the DC component of the input error signal, and 10 is a mode for outputting a motor control signal (PWM) whose pulse width is modulated so that the input error signal becomes zero to the cylinder motor 11. Control signal output section, 11
Is a cylinder motor for rotating a cylinder (not shown),
Reference numeral 12 is a speed / phase detector that detects the rotation speed and the rotation phase of the cylinder motor 11. Each function of the signal detection unit 1 to the motor control signal output unit 10 is built in the microcomputer.

Next, the operation of this embodiment will be described. When the cylinder motor 11 is rotating, the speed / phase detector 12 inputs a detection signal as shown in FIG. This detection signal is composed of one phase detection signal PG generated every one rotation of the cylinder motor 11 and six speed detection signals FG generated each rotation as shown in FIG. 2B. . The signal detector 1 detects the speed detection signal FG and the phase detection signal P from the input detection signals.
G is separated, and the speed detection signal FG is output to the speed cycle measuring unit 5. At the same time, the signal detection unit 1 uses the phase detection signal PG generated at the timing shown in FIG. 2B as a reference, and the speed detection signal FG coming next as the first phase detection signal, The speed detection signals FG sequentially input thereafter are regarded as the second to sixth phase detection signals, and the first to sixth speed detection signals are output to the phase difference measuring unit 2. At this time, the signal detection unit 1 informs the memory unit 4 of which speed detection signal is currently output to the phase difference measurement unit 2.

The phase difference measuring section 2 receives a speed detection signal (used as a phase detection signal) sequentially input from the signal detection section 1 and a vertical synchronization signal 100 separately input as shown in FIG. And the obtained phase difference is output to the comparison unit 3. The comparison unit 3 compares the input phase difference with the phase target value supplied from the memory unit 4 at that time,
The phase error signal obtained as a result is output to the mixing unit 8. Here, the phase difference measuring unit 2 is connected to the signal detecting unit 1 from FIG.
When the first speed detection signal shown in (B) is input as the phase detection signal, the phase target value (1) shown in FIG. 2D is supplied from the memory unit 4 to the comparison unit 3. . Therefore, the comparison unit 3 compares the first speed detection signal with that shown in FIG.
When the phase difference with the vertical synchronizing signal 100 shown in (A) is input from the phase difference measuring unit 2, the difference between this phase difference and the phase target value (1) is obtained and mixed as a phase error signal. Output to the unit 8. Next, when the second speed detection signal is output from the signal detection unit 1 to the phase difference measurement unit 2, the comparison unit 3 receives the phase target value (2) shown in FIG. Since it is supplied, the phase error signal is obtained in the comparison section 3 in the same manner as described above. Similarly in other cases, when the signal detection unit 1 outputs the third to sixth speed detection signals to the phase difference measurement unit 2, the memory unit 4 outputs the phase target values (3) to (6) to the comparison unit. 3 and the phase error signal is output from the comparing section 3 to the mixing section 8 each time.

On the other hand, the speed cycle measuring section 5 measures the rotation cycle of the cylinder motor 11 from the input speed detection signal,
The obtained rotation cycle is output to the comparison unit 6. The speed cycle measuring unit 5 measures the rotation cycle of the cylinder motor 11 by measuring the input interval of the speed detection signal FG as shown in FIG. 2 (C). Therefore, the comparison unit 6 compares this rotation cycle with a target value (target time / pulse number of one rotation), and as a result, if the rotation cycle is long, the cylinder motor 11 is accelerated, and if it is short, the cylinder motor 11 is decelerated. The speed error signal is generated and output to the mixing unit 8 via the gain compensation filter unit 7. The mixing unit 8 mixes the speed error signal and the phase error signal input from the comparison unit 3 to create an error signal, and outputs this to the motor control signal output unit 10 via the DC compensation filter unit 9. The motor control signal output unit 10 outputs to the cylinder motor 11 a motor control signal composed of a pulse signal modulated so that the input error signal becomes zero. Cylinder motor 1
1 rotates at a rotation speed and a rotation phase according to this motor control signal.

Now, a method of obtaining the phase target value stored in the memory section 4 will be described. Phase target values (1) to (6) shown in FIG. 2D corresponding to the first to sixth speed detection signals (used as phase detection signals) shown in FIG. 2B are not shown. Switching pulse for switching heads and vertical sync signal 1 shown in FIG.
00 and a unique value of a cylinder (not shown). Alternatively, the cylinder motor 11
When the rotation speed and the phase of the are locked, the detection signal generated from the speed / phase detector 12 is actually measured, and the phase target values (1) to ( 6) can be obtained. It is assumed that the phase target values (1) to (6) are obtained immediately after the assembly of the set and are written in the memory (nonvolatile memory) 4.

According to this embodiment, six speed detection signals FG generated from the speed / phase detector 12 during one rotation of the cylinder motor 11 are used as phase detection signals, and the phase detection signals are phase-detected. The obtained phase error signal is mixed with the mixing unit 8
Since it is input to the servo system of the cylinder motor 11 via the, the phase detection signal arrives immediately even if the rotation phase lock of the cylinder motor is deviated due to the switching of the broadcast receiving channel, the disturbance input, etc. The detection is not delayed, and the transient response can be improved. Further, as compared with the conventional phase detection that is performed once for each rotation of the cylinder motor 11, in this example, the phase detection is performed six times for one rotation, so that the accuracy of phase error detection is increased.
The accuracy of the rotation phase control of the cylinder motor 11 can be improved.

[0015]

As described above, according to the motor control circuit of the present invention, even if the detection signal integrated by superimposing the speed detection signal and the phase detection signal is used and the rotation phase lock is shifted, the rotation control is again performed. It is possible to improve the transient response and control accuracy by minimizing the transition period until locked.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a motor control circuit of the present invention.

FIG. 2 is a time chart explaining a rotation phase control operation of a cylinder motor in the circuit shown in FIG.

FIG. 3 is a time chart explaining a rotation phase control operation of a cylinder motor in a conventional VTR.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Signal detection part 2 ... Phase difference measurement part 3 ... Comparison part 4 ... Memory part 5 ... Speed period measurement part 6 ... Comparison part 7 ... Gain compensation filter part 8 ... Mixing part 9 ... DC compensation filter part 10 ... Motor control signal Output unit 11 ... Cylinder motor 12 ... Speed / phase detector

Claims (1)

[Claims] 1. A speed control system for controlling the rotation speed of the motor based on a speed error signal obtained by speed detection of a speed detection signal corresponding to the rotation speed of the motor, and a phase detection corresponding to the rotation phase of the motor. In a motor control circuit comprising a phase control system for controlling the rotation phase of the motor based on a phase error signal obtained by phase-detecting a signal,
A separation circuit for separating the speed detection signal and the phase detection signal from a detection signal formed by superposing the speed detection signal and the phase detection signal, and a phase difference between the speed detection signal and the reference signal separated by the separation circuit. A measurement circuit to be obtained, a determination circuit for determining the order in which the speed detection signal input to this measurement circuit is generated with reference to the phase detection signal, and the phase difference obtained by the measurement circuit are separately supplied. A comparison circuit that compares the phase target value with the phase error signal to generate the phase error signal, and a phase target value corresponding to the order of judgment of the speed detection signal input to the measurement circuit by the judgment circuit is supplied to the comparison circuit. And a target value supply circuit for controlling the motor.