JPH06216960A - Synchronous detection circuit - Google Patents

Abstract

PURPOSE:To improve the transmission efficiency of a burst signal after multiplying an input signal by a carrier wave reproduced from this signal, and subjecting the resultant signal to A/D conversion, inputting this converted signal and discrimination symbol series candidates of a discrimination circuit and selecting and outputting a maximum likelihood value from among prepared remodulated signal series candidates. CONSTITUTION:The signal obtained by multiplying the signal of an input terminal 1 at which a burst signal arrives, by the carrier frequency signal, which a carrier frequency reproducing circuit 8 reproduced from this signal, in a multiplier 3 is outputted through an LPF 4. This signal is converted by an A/D conversion circuit 11 and is inputted to a branch metric operation circuit 12, and series candidates of a discrimination symbol are branched and inputted to the circuit 12 from a discriminating circuit 5. The circuit 5 uses a Viterbi algorithm to select and output the symbol series candidate for which the output power of the circuit 12 is minimum, as a maximum likelihood value from remodulated signal series candidates which the circuit 12 prepares by operation based on both inputs. Thus, the transmission efficiency of the burst signal is improved, and the phase synchronizing circuit of a reception equipment is unnecessary.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention is used for digital wireless communication. Especially, time division multiple access (TDMA, Time Divi
sion multiple access) technology for improving signal transmission efficiency. The present invention relates to a prior application (Japanese Patent Application No.
No. 293359, unpublished at the time of filing of the present application).

[0002]

2. Description of the Related Art Synchronous detection is widely known as one of reception and demodulation techniques for digital communication signals. A conventional example will be described with reference to FIG. FIG. 5 is a block diagram of a conventional device and a burst signal configuration diagram. As shown in FIG. 5A, the received wave down-converted to the IF (intermediate frequency) band is input from the input terminal 1. The carrier wave synchronization circuit 2 extracts a carrier wave component from the received wave. The multiplier 3 multiplies the received wave and the carrier wave component, and the low-pass filter 4
To enter. The low-pass filter 4 removes unnecessary high-frequency components and extracts baseband modulated wave components. The determination circuit 5 is
This baseband modulated wave component is used as an input for signal determination, and a signal determination value is output from the output terminal 6.

On the other hand, TD is used as a communication system for digital communication.
MA is widely known. The burst structure of TDMA is shown in FIG. At the beginning of the burst, a carrier recovery signal and a timing clock recovery signal are inserted for carrier synchronization and clock synchronization. The carrier wave synchronizing circuit 2 extracts a carrier wave component based on the received wave corresponding to the carrier wave reproducing signal. The unique word is a burst synchronization signal, which is followed by information bits.

[0004]

When the above-described carrier wave reproduction signal becomes long, the information bit that can be substantially sent becomes short and the transmission efficiency deteriorates. In the conventional synchronous detection circuit, CN
Even if R (Carrier Noise Ratio) is poor, the carrier reproduction signal must be lengthened in order to perform carrier synchronization with high accuracy, and the transmission efficiency will be reduced.

The present invention has been made against such a background and does not require carrier synchronization in the device on the receiving side, and does not require a carrier recovery signal for the burst signal used for this purpose, thus improving the transmission efficiency. An object of the present invention is to provide a synchronous detection circuit that can be used.

FIG. 6 shows a block diagram of an arithmetic circuit of a coherent detection circuit of the prior application which has solved this object. As shown in FIG. 6, the prior application has a configuration using three systems of inverse modulation circuits 40, 20, and 21.

[0007]

According to the present invention, an input terminal to which a burst signal arrives, a means for reproducing a carrier frequency from the signal of the input terminal, a carrier frequency signal reproduced by the means and the input terminal are provided. Synchronous detection provided with a multiplier that multiplies the output signal of the multiplier, a low-pass filter through which the output signal of the multiplier passes, and a determination circuit that determines the modulation signal based on the output signal of the low-pass filter. Circuit.

Here, the feature of the present invention resides in that an analog / digital conversion circuit for converting the output signal of the low-pass filter into a digital signal and an output of the analog / digital conversion circuit are used for the determination. And a calculation circuit including means for branching and inputting a sequence candidate of the determination symbol of the circuit to generate a remodulated signal sequence candidate, the determination circuit comprising:
The configuration is such that the determination output is selected so that the output power of this arithmetic circuit becomes small. The determination circuit is a determination circuit based on a Viterbi algorithm, and it is preferable that the determination circuit includes means for maximizing the symbol sequence candidate having the minimum output power.

The arithmetic circuit inversely modulates the output of the analog-to-digital conversion circuit at the past time point one or several timings before with the symbol sequence candidate at the past time point one or several timings before, and the inverse modulation circuit. A modulation circuit for modulating the output of the circuit with the current symbol sequence candidate to generate the remodulation signal sequence candidate, and a linear combination of the generated remodulation signal sequence candidate from the output of the analog-digital conversion circuit at the current time. It is desirable to include a subtraction circuit for subtraction and a circuit for squaring the output of the subtraction circuit, and to use the output of the squaring circuit as a signal representing the output power.

Further, the arithmetic circuit outputs the output of the analog-to-digital conversion circuit at the past time point one or several timings before the phase angle between the symbol sequence candidate at the past time point one or several timings before and the current symbol sequence candidate. A re-modulation circuit that re-modulates with a difference signal sequence candidate to generate the re-modulation signal sequence candidate, and a subtraction circuit that subtracts a linear combination of the generated re-modulation signal sequence candidates from the current output of the analog-digital conversion circuit. And a circuit for squaring the output of the subtraction circuit, and the output of the squaring circuit may be a signal representing the output power.

The present invention has the same purpose as the invention of the prior application and is an invention that can replace the invention of the prior application.

[0012]

The carrier component is extracted from the input signal, the carrier frequency regenerating circuit is activated at that frequency, and the signal generated by this carrier frequency regenerating circuit is multiplied by the received signal. At this time, the frequency of the reproduced carrier wave is synchronized with the received carrier wave, but the phase is indeterminate.

A high-frequency component is removed by a low-pass filter to extract a baseband modulated wave component, which is input to a decision circuit using a Viterbi algorithm to output a complex symbol sequence candidate and a signal decision value.

This baseband modulated wave component is analog
The signal is branched and input to the digital circuit, and is sampled at the sampling period T which is the symbol period of the modulated wave. This is for performing digital processing in the subsequent stage.

The sampled signal is inversely modulated by the complex symbol sequence candidate corresponding to the state transition of the Viterbi algorithm of the decision circuit. In this inverse modulation, past sampled signals such as T periods and 2T periods from the present time are inversely modulated by complex symbol sequence candidates corresponding to respective state transitions such as T period before and 2T period before of the Viterbi algorithm. The inversely modulated signal is further modulated with the current complex symbol sequence candidate to generate a remodulated signal sequence candidate.

In this remodulated signal sequence candidate, signals sampled in the past such as T period and 2T period from the present time are T period before and 2T period of the Viterbi algorithm, respectively.
It can also be generated using the phase angle difference signal sequence candidate corresponding to each state transition such as before the cycle.

Next, the linear combination of the re-modulated signals is subtracted from the current sampling value, and if the difference is close to zero, it means that the complex symbol sequence candidate corresponding to the state transition matches the transmission symbol sequence candidate. On the contrary, the larger the difference is, the more different the complex symbol sequence candidate corresponding to the state transition is from the transmission symbol sequence candidate.

Therefore, this difference is squared to obtain a value proportional to the output power, which is always input to the determination circuit as a positive value.
This signal serves as an index indicating the likelihood in the Viterbi algorithm, and the decision circuit refers to this signal and selects the complex symbol sequence candidate with the maximum cumulative value of this signal as the maximum likelihood.

With this, since the signal can be determined by the maximum likelihood determination even if the reproduced carrier wave is not synchronized, it is possible to use a signal that does not need carrier wave synchronization information for the transmission signal and to synchronize the carrier wave phase of the receiver. No circuit is needed.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of the first embodiment of the present invention.

According to the present invention, an input terminal 1 to which a burst signal arrives, a carrier frequency reproducing circuit 8 as means for reproducing a carrier frequency from the signal of the input terminal 1, and a carrier frequency reproduced by the carrier frequency reproducing circuit 8. Of the input terminal 1 and a low-pass filter 4 through which the output signal of the multiplier 3 passes, and a modulation signal based on the output signal of the low-pass filter 4. This is a synchronous detection circuit including a determination circuit 5 that makes determination using a Viterbi algorithm.

Here, the feature of the present invention is that the analog-digital conversion circuit 11 for converting the output signal of the low-pass filter 4 into a digital signal and the output of the analog-digital conversion circuit 11 are: A branch metric operation circuit 12 which is an operation circuit including means for branching and inputting the decision symbol sequence candidates of the decision circuit 5 to generate re-modulated signal sequence candidates, and the decision circuit 5 outputs the branch metric operation circuit 12 The configuration is such that the determination output is selected so that the electric power becomes small. The symbol sequence candidate having the smallest output power is set as the maximum likelihood.

Next, the operation of the first embodiment of the present invention will be described with reference to FIG. A received wave down-converted to the IF (intermediate frequency) band is input from the input terminal 1. The carrier frequency reproduction circuit 8 extracts a carrier frequency component from the received wave. Since the carrier wave phase may be indeterminate, no special signal such as a carrier wave synchronizing signal is required to operate the carrier wave frequency reproducing circuit 8. The multiplier 3 multiplies the received wave and the carrier frequency component and inputs the result to the low pass filter 4. The low-pass filter 4 removes an unnecessary high frequency component from the output of the multiplier 3 and extracts a baseband modulated wave component. The analog-digital conversion circuit 11 samples this baseband modulation component at the symbol period T of the modulated wave, converts it into a digital signal, and inputs it to the branch metric calculation circuit 12. Here, the carrier frequency reproducing circuit 8, the multiplier 3 and the low-pass filter 4 are components of the quasi-synchronous detection circuit 9, and the output signal of the analog-digital conversion circuit 11 corresponds to the sampling value of the quasi-synchronous detection signal. . The branch metric operation circuit 12 inputs the sampling value sequence candidate of the quasi-synchronized detection signal and the complex symbol sequence candidate corresponding to the state transition output from the determination circuit 5 via the bus 7, and estimates the carrier synchronization error. Output a signal.
The determination circuit 5 receives the square of the estimation error signal as an input, performs state estimation, and determines that the complex symbol sequence candidate corresponds to the above-mentioned state transition determined by the baseband modulated wave signal from the quasi-synchronous detection circuit 9. Output the output. The signal determination value is output from the output terminal 6.

FIG. 2 shows a block configuration of the branch metric operation circuit 12. FIG. 2 is a block diagram of the branch metric calculation circuit 12. The sampling value y _s (k) of the quasi-synchronous detection signal is input from the input terminal 16. In the following, all signals are represented in complex representation, where the in-phase component corresponds to the real part and the quadrature component corresponds to the imaginary number. y _s (k) can be expressed as y _s (k) = a (k) h (k) + n (k) when the transmitted complex symbol is a (k). Here, the modulation method is QAM (Quadrature Am
plitude Modulation) method. h (k) is a carrier signal component, n (k) is a noise component, and is white noise that has passed through the low-pass filter 4.

Y _s (k) is input to the shift register 19 including the delay elements 17 and 18, and the sampling value of the quasi-synchronous detection signal delayed by T is output from the shift register 19. Sampling sequence candidates {y _s (i)} of the quasi-coherent detection signal past the present time as k are input to the inverse modulation circuits 20 and 21 and complex symbol sequence candidates corresponding to the state transition input from the input terminal 29. {A
It is inversely modulated by _m (i)}. Here, L is the number of stages of the shift register 19. FIG. 2 shows the case where L = 2.
When a reverse modulated wave signal and _{{z m (i)},} z m (i) = y s (i) / a m (i) = (h (i) a (i) / a m (i)) + n the _{s (i) / a m (} i). The noise component level is small and a _m (i) is a
When it coincides with (i), z _m (i) almost coincides with the carrier signal component h (i). The modulation circuits 22 and 23 modulate the inverse modulated wave signal sequence candidate with the current complex symbol sequence candidate a _m (k) and re-modulate signal sequence candidate {y.
_es (i)} is generated. {Y _es (i)} becomes _{y es (i) = z m} (i) a m (k) = y s (i) a m (k) / a m (i). The linear combination of remodulation signal sequence candidates is performed by the multiplier 24.
And 25 and the adder circuit 26. The linear combination constant W ₁ set in the multipliers 24 and 25,
W ₂ is fixed and does not change with time. The linear combination here is equivalent to performing linear predictive filtering of the carrier signal component at the present time, modulating this predicted value with the candidate complex symbol sequence at the present time, and predicting the quasi-coherent detection signal at the present time. For example, assuming that the carrier signal component h (k) does not change with time, the multipliers 24 and 2
All constants set to 5 are set to 1 / L. That is, the quasi-coherent detection signal at the present time is predicted by averaging the past re-modulated wave signals. When the carrier signal component h (k) fluctuates with time, the weighting of the re-modulated signal in the past is reduced so that it can be averaged to follow the fluctuation.
For example, the weighting constant of y _es (k−k ₁ ) is set to λ ^k1-1 / (1
-Λ) is also available. However, 0 <λ ≦ 1. The subtraction circuit 27 uses the current quasi-synchronous detection signal y _s (k).
To subtract the linear combination of the re-modulated signals and output the estimation error signal. The square calculation circuit 28 calculates the square of the estimation error signal and always outputs it as a positive value from the output terminal 30.

Next, the operation of the decision circuit 5 will be described. The decision circuit 5 uses the maximum likelihood sequence estimation (Maximum Likelihood Sequence
(Estimation: MLSE) to estimate the state and judge the signal. The MLSE is an estimation method in which the likelihood is calculated for all possible symbol sequence candidates and the code sequence having the largest value is used as the signal determination value. As the transmitted complex symbol sequence candidates become longer, the number of all possible complex symbol sequence candidates increases by a specified function. Therefore, the Viterbi algorithm is known as an algorithm that reduces the number of candidates and suppresses the calculation amount. The determination circuit 5 performs MLSE by the Viterbi algorithm.

Next, referring to FIG. 3, the Viterbi algorithm in the first embodiment of the present invention will be described.
ase Shift Keying) Modulation will be described as an example. FIG. 3 is a trellis diagram showing state transitions. First, the state will be described. The complex symbol to be considered is currently kT to (k−L)
Since it is up to T, {a _m (i) | k−L ≦ i ≦ k−1} is called a state. In this case, the number of states is 2 ^L, that is, 2 ² = 4.
Becomes The complex symbol sequence candidate can be described using this state. Let _{s be the} sth state at time k
(K). Here, 0 ≦ s ≦ 3, and the time point is k.
The state transitions when going from to k + 1. The state transition is a
Complex symbol sequence candidate a _m (k + 1) for (k + 1)
Since it depends on the value of 1), two transitions occur from one state. As shown in FIG. 3, it branches from one state to two states and merges from two states to one state. A transition metric J _{K + 1} [σ _S (k + 1), σ corresponding to the transition from the state σ _{S ′} (k) to σ _S (k + 1) in order to select one transition from two transitions that merge at the transition destination.
_{S '} (k)] is used. From the state σ _{S '} (k), σ _S (k +
The transition metric in the transition to 1) is the branch metric BR [σ _S (k + 1), σ _{S ′} (k)] for each transition.
By using J _{K + 1} [σ _S (k + 1), σ _{S ′} (k)] = J _K [σ _{S ′} (k)] + BR [σ _S (k + 1), σ _{S ′} (k)] To be done. However,

[0028]

[Equation 1] Is. J _K [σ _{S ′} (k)] is a path metric at time k and corresponds to the likelihood. State transition σ
The transition signal sequence in _{S ′} (k) → σ _S (k + 1) is {a
_{m (k-1), a} m (k), represented by _{a m (k + 1)}} . In the Viterbi algorithm, J _{K + 1} [σ _S (k + 1), σ _{S ′} (k)] corresponding to two merging transitions are compared, the larger transition is selected, and the transition metric of the selected transition is selected. Is the path metric J _{K + 1} at time k _{+ 1}
[Σ _S (k + 1)]. Then, only the time series and the path in the state linked to the selected transition are left as the maximum likelihood series candidates. If this operation is repeated thereafter, as many paths as the number of states survive. This pass is called the survival pass. If all surviving paths meet at some point in the past, the state at that point can be determined, and signal determination is performed. However, if they do not merge, the signal determination is postponed. The above operation is repeated. Note that due to memory limitations, the time series of states is stored only up to the past (D-L + 1) T, and if the surviving paths do not merge at the time of the past (D-L + 1) T, the path with the maximum likelihood at the present time, That is, the signal determination is performed based on the path with the maximum path metric. The signal judged at this time is DT delayed from the present time, and this DT is called judgment delay time (G, Ungerboeck, "Adaptive ma
ximum likelihood receiver for carrier-modulated da
ta-transmission systems, "IEEE Trans, Commun, vol, CO
M-22, pp, 624-636, 1974). However, D ≧ L. As described above, the Viterbi algorithm expresses a symbol sequence candidate by using a state, and performs signal estimation by performing state estimation. The initial state of the Viterbi algorithm is shown in FIG.
It is determined based on the unique word shown in (b).

As described above, according to the present invention, the signal determination is performed based on the Viterbi algorithm, and the carrier signal component is predicted based on the state transition of the Viterbi algorithm. Therefore, carrier phase synchronization need not be performed. That is, it is possible to improve burst transmission efficiency without requiring a carrier synchronization signal.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram of the branch metric operation circuit of the second embodiment device of the present invention. In the device of the second embodiment of the present invention, the configuration of the branch metric operation circuit 12 in the device of the first embodiment of the present invention is different from the signal sequence input to the branch metric operation circuit 12 by the determination circuit 5.

As shown in FIG. 4, the branch metric operation circuit 12 of the device of the second embodiment of the present invention receives the sampling value y _s (k) of the quasi-coherent detection signal from the input terminal 16. y _s (k) is input to the shift register 19 including the delay elements 17 and 18, and the sampling value of the quasi-synchronous detection signal delayed by T is output from the shift register 19. The sampling sequence candidates {y _s (i)} of the quasi-coherent detection signal past the present time k are remodulation circuits 35 and 36.
And is re-modulated with the phase angle difference signal sequence candidate {b _m (i)} corresponding to the state transition input from the input terminal 29. This phase angle difference signal will be described by taking differential coding PSK modulation as an example. At this time, the amplitude of the complex symbol a (k) is “1”, and the phase angle difference b (k) = a of the complex symbol is
Information is included in (k) / a (k-1). If the re-modulated signal y _es (ki) is expressed using the phase angle difference b _m (k) corresponding to the complex symbol sequence candidate,

[0032]

[Equation 2] Becomes Remodulation circuits 35 and 36 generate remodulation signal sequence candidates according to the above equation. The linear combination of the modulated wave signal sequence candidates is obtained by the multipliers 24 and 25 and the adder circuit 26. The linear coupling constants w1 and w2 set in the multipliers 24 and 25 are fixed and are not changed with time. The linear combination here is equivalent to performing linear predictive filtering of the carrier signal component at the present time, modulating this predicted value with the candidate complex symbol sequence at the present time, and predicting the quasi-coherent detection signal at the present time. For example, assuming that the carrier signal component h (k) does not change with time, all the constants set in the multipliers 24 and 25 are set to 1 / L. That is, the quasi-coherent detection signal at the present time is predicted by averaging the past re-modulated signals. When the carrier signal component h (k) fluctuates with time, the weighting of the re-modulated signal in the past is reduced so that the fluctuation can be averaged to follow the fluctuation. For example, y _es (k−k ₁ )
There is also a method of setting the weighting constant of λ ^k1-1 / (1-λ). However, 0 <λ ≦ 1. The subtraction circuit 27 subtracts the linear combination of the re-modulated signals from the current quasi-coherent detection signal y _s (k) and outputs an estimation error signal. The square calculation circuit 28 calculates the square of the estimated error signal and outputs it from the output terminal 30.

As a result, similarly to the first embodiment of the present invention, the carrier wave synchronizing signal is not required and the burst transmission efficiency can be improved. In addition, by using the phase angle difference signal, the number of states of the Viterbi algorithm can be reduced as compared with the first embodiment of the present invention, and the circuit scale of the determination circuit 5 can be reduced. More specifically, in the second embodiment of the present invention, the phase difference signal to be considered is from the current kT to (k−L).
Since it is up to +1) T, {b _m (i) | k−L + 1 ≦ i ≦
k-1} becomes a state. In the differential coded BPSK modulation, the number of states is 2 ^{L-1 and} can be halved as compared with the first embodiment of the present invention.

[0034]

As described above, according to the present invention, since the carrier phase is predicted in accordance with the signal judgment, it is not necessary to synchronize the carrier phase. That is, since the carrier wave synchronization information is not required for the burst signal used for communication, the transmission efficiency of the burst signal can be improved and the phase synchronization circuit of the receiving device can be eliminated.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a branch metric operation circuit according to the first embodiment of the present invention.

FIG. 3 is a trellis diagram showing a state transition diagram.

FIG. 4 is a block configuration diagram of a branch metric operation circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a conventional device and a block diagram of a burst signal.

FIG. 6 is a block diagram of an arithmetic circuit of the prior application.

[Explanation of symbols]

 1, 16, 29 Input terminal 2 Carrier wave synchronization circuit 3 Multiplier 4 Low-pass filter 5 Judgment circuit 6, 30 Output terminal 7 Bus 8 Carrier wave frequency reproduction circuit 9 Quasi-synchronous detection circuit 11 Analog-digital conversion circuit 12 Branch metric arithmetic circuit 17, 18 Delay element 19 Shift register 20, 21, 40 Inverse modulation circuit 22, 23 Modulation circuit 24, 25 Multiplier 26 Adder circuit 27 Subtraction circuit 28 Square operation circuit 35, 36 Remodulation circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H04L 27/22 B 9297-5K D 9297-5K

Claims (4)

[Claims] 1. An input terminal to which a burst signal arrives, and means for reproducing a carrier frequency from the signal of this input terminal,
A multiplier for multiplying the carrier frequency signal reproduced by this means by the signal at the input terminal, a low-pass filter through which the output signal of this multiplier passes, and an output signal of this low-pass filter In a synchronous detection circuit including a determination circuit for determining a modulation signal, an analog-digital conversion circuit for converting the output signal of the low-pass filter into a digital signal, and an output of this analog-digital conversion circuit An operation circuit including means for branching and inputting the decision symbol sequence candidates of the decision circuit to generate remodulated signal sequence candidates, wherein the decision circuit outputs a decision output so that the output power of the operation circuit becomes small. A synchronous detection circuit having a configuration for selection. 2. The synchronous detection circuit according to claim 1, wherein the determination circuit is a determination circuit based on a Viterbi algorithm, and includes means for maximizing a symbol sequence candidate having the minimum output power. 3. The inverse modulation circuit, wherein the arithmetic circuit inversely modulates the output of the analog-to-digital conversion circuit at the past time point one or several timings before with the symbol sequence candidate at the past time point one or several timings before, A modulation circuit that modulates the output of the inverse modulation circuit with the current symbol sequence candidate to generate the re-modulated signal sequence candidate, and a linear combination of the generated re-modulated signal sequence candidate of the current analog-digital conversion circuit. 3. The synchronous detection circuit according to claim 1, further comprising a subtraction circuit for subtracting the output from the output, and a circuit for squaring the output of the subtraction circuit, wherein the output of the squaring circuit is a signal representing the output power. 4. The arithmetic circuit outputs the output of the analog-to-digital conversion circuit at the past time point one or several timings before the phase angle between the symbol sequence candidate at the past time point one or several timings before and the current symbol sequence candidate. A re-modulation circuit that re-modulates with a difference signal sequence candidate to generate the re-modulation signal sequence candidate, and a subtraction circuit that subtracts a linear combination of the generated re-modulation signal sequence candidates from the current output of the analog-digital conversion circuit. 3. The synchronous detection circuit according to claim 1, further comprising: a circuit for squaring the output of the subtraction circuit, wherein the output of the squaring circuit is a signal representing the output power.