JP2938297B2 - Synchronous detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used for digital radio communication. In particular, time division multiple access (TDMA, Time Divi
and the technology for improving the signal transmission efficiency in multiplexing multiple access. The present invention is based on the prior application (Japanese Patent Application No.
-293359, which has not been published at the time of filing the present application).

[0002]

2. Description of the Related Art Synchronous detection is widely known as one of the techniques for receiving and demodulating digital communication signals. The conventional example will be described with reference to FIG. FIG. 5 is a block diagram of a conventional device and a block diagram of a burst signal. As shown in FIG. 5A, a received wave down-converted to an IF (intermediate frequency) band is input from an input terminal 1. The carrier synchronization circuit 2 extracts a carrier component from the received wave. The multiplier 3 multiplies the received wave by the carrier wave component, and forms a low-pass filter 4.
To enter. The low-pass filter 4 removes unnecessary high-frequency components and extracts baseband modulated wave components. The determination circuit 5
The signal determination is performed using the baseband modulated wave component as an input, and a signal determination value is output from the output terminal 6.

On the other hand, TD is used as a communication system for digital communication.
MA is widely known. FIG. 5B shows the burst configuration of TDMA. At the beginning of the burst, a carrier signal and a timing clock signal for carrier and clock synchronization are inserted. The carrier synchronization circuit 2 extracts a carrier component based on the received wave corresponding to the carrier reproduction signal. The unique word is a signal for burst synchronization, followed by information bits.

[0004]

When the length of the carrier reproduction signal becomes longer, the number of information bits that can be transmitted becomes substantially shorter and the transmission efficiency becomes worse. In a conventional synchronous detection circuit, CN
Even when R (Carrier-to-Noise Ratio, Carrier Noise Ratio) is poor, the carrier recovery signal must be lengthened in order to carry out carrier synchronization with high accuracy, and the transmission efficiency is reduced.

The present invention has been made in view of such a background, and does not require carrier synchronization in a receiving-side device, does not require a carrier recovery signal in a burst signal used therefor, and improves transmission efficiency. It is an object of the present invention to provide a synchronous detection circuit that can perform the detection.

FIG. 6 shows a block diagram of an arithmetic circuit of the synchronous detection circuit of the prior application which solves this object. As shown in FIG. 6, the prior application has a configuration using three systems of inverse modulation circuits 40, 20, and 21.

[0007]

According to the present invention, there is provided an input terminal from which a burst signal arrives, a means for reproducing a carrier frequency from a signal at the input terminal, a carrier frequency signal reproduced by the means, and the input terminal. , A low-pass filter through which the output signal of the multiplier passes, and a determination circuit for determining a modulation signal based on the output signal of the low-pass filter. Circuit.

Here, the features of the present invention are: an analog-to-digital conversion circuit for converting the output signal of the low-pass filter into a digital signal; Circuit state transition
Signal system using complex symbol sequence candidates corresponding to
Generate column candidates and determine whether the remodulated signal sequence candidates are linear combinations.
And an arithmetic circuit which generates the al estimated error signal and outputs the square value, the decision circuit, when the output of the arithmetic circuit is configured to select a decision output such that small <br/> fence It is in. The determination circuit is a judgment circuit according to the Viterbi algorithm, it is desirable to include a means for said complex <br/> symbol sequence candidates maximum likelihood sequence output of the arithmetic circuit is minimized.

The arithmetic circuit includes an inverse modulation circuit for inversely modulating an output at one or several timings before the analog-to-digital conversion circuit at a past time point with a symbol sequence candidate at one or several timings before the current time. A modulation circuit for modulating the output of the circuit with the current symbol sequence candidate to generate the re-modulated signal sequence candidate; and a linear combination of the generated re-modulated signal sequence candidate from the current output of the analog-to-digital conversion circuit. It is preferable that a subtraction circuit for subtraction and a circuit for squaring the output of the subtraction circuit as the estimated error signal be provided, and the output of the squaring circuit be used as the output of the arithmetic circuit .

The arithmetic circuit may output an output at a past time one or several timings before the analog-digital conversion circuit to a phase angle between a symbol sequence candidate at a past time one or several timings earlier and a current symbol sequence candidate. A remodulation circuit for remodulating with the difference signal sequence candidate to generate the remodulation signal sequence candidate, and a subtraction circuit for subtracting a linear combination of the generated remodulation signal sequence candidate from the current output of the analog / digital conversion circuit And the output of this subtraction circuit
A circuit for squaring as the estimation error signal, and an output of the squaring circuit may be used as an output of the arithmetic circuit .

The present invention has the same purpose as the invention of the prior application, and is an invention which can replace the invention of the prior application.

[0012]

A carrier wave component is extracted from an input signal, a carrier wave frequency recovery circuit is started at that frequency, and a signal generated by the carrier wave frequency recovery circuit is multiplied by a received signal. At this time, the frequency of the recovered carrier is synchronized with the received carrier, but the phase is uncertain.

A low-pass filter removes a high-frequency component to extract a baseband modulated wave component, which is input to a determination circuit using a Viterbi algorithm to output a complex symbol sequence candidate and a signal determination value.

The baseband modulated wave component is analog
The signal is branched and input to the digital circuit, and is sampled at a sampling period T which is a symbol period of the modulated wave. This is for performing digital processing later.

The sampled signal is inversely modulated by a complex symbol sequence candidate corresponding to the state transition of the Viterbi algorithm of the decision circuit. In this inverse modulation, a signal sampled in the past, such as the T cycle and the 2T cycle from the present time, is inversely modulated by a complex symbol sequence candidate corresponding to each state transition such as a T cycle before and a 2T cycle before the Viterbi algorithm, respectively. This inversely modulated signal is further modulated with the current complex symbol sequence candidate to generate a remodulated signal sequence candidate.

This remodulated signal sequence candidate is obtained by comparing a sampled signal such as T period and 2T period before the present time with T period before the Viterbi algorithm and 2T period.
It can also be generated using a phase angle difference signal sequence candidate corresponding to each state transition such as before the cycle.

Next, the linear combination of the re-modulated signal is subtracted from the current sampling value, and if the difference is close to zero, the complex symbol sequence candidate corresponding to the state transition matches the transmission symbol sequence candidate. Conversely, the larger the difference is, the more the complex symbol sequence candidate corresponding to the state transition is different from the transmission symbol sequence candidate.

Therefore, this difference is squared to obtain a value proportional to the output power, and is always input to the determination circuit as a positive value.
This signal serves as an index indicating the likelihood in the Viterbi algorithm, and the determination circuit refers to this signal and selects a complex symbol sequence candidate with the maximum likelihood when the cumulative value of this signal is the minimum.

Thus, signal determination based on maximum likelihood determination can be performed without synchronization of a reproduced carrier, so that a signal that does not require carrier synchronization information can be used as a transmission signal, and a signal for synchronizing the carrier phase of a receiving apparatus can be used. No circuit is required.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a first embodiment of the present invention.

The present invention relates to an input terminal 1 from which a burst signal arrives, a carrier frequency reproducing circuit 8 as means for reproducing a carrier frequency from the signal of the input terminal 1, and a carrier frequency reproduced by the carrier frequency reproducing circuit 8. , A low-pass filter 4 through which the output signal of the multiplier 3 passes, and a modulation signal based on the output signal of the low-pass filter 4. A synchronous detection circuit including a determination circuit 5 for determining using a Viterbi algorithm.

Here, the feature of the present invention is that an analog-to-digital conversion circuit 11 for converting an output signal of the low-pass filter 4 into a digital signal, and an output of the analog-to-digital conversion circuit 11 A branch metric calculation circuit 12 which is a calculation circuit including means for branching and inputting a determination symbol sequence candidate of the determination circuit 5 to generate a re-modulated signal sequence candidate; In this configuration, the determination output is selected so that the power is reduced. The symbol sequence candidate with the minimum output power is the maximum likelihood.

Next, the operation of the first embodiment of the present invention will be described with reference to FIG. From an input terminal 1, a received wave down-converted to an IF (intermediate frequency) band is input. The carrier frequency regeneration circuit 8 extracts a carrier frequency component from the received wave. Since the carrier phase may be uncertain, a special signal such as a carrier synchronization signal is not required to operate the carrier frequency recovery circuit 8. The multiplier 3 multiplies the received wave by the carrier frequency component and inputs the result to the low-pass filter 4. The low-pass filter 4 removes unnecessary high-frequency components from the output of the multiplier 3 and extracts a baseband modulated wave component. The analog / digital conversion circuit 11 samples this baseband modulation component at the symbol period T of the modulation wave, converts it into a digital signal, and inputs the digital signal to the branch metric calculation circuit 12. Here, the carrier frequency reproduction circuit 8, the multiplier 3, and the low-pass filter 4 are components of the quasi-synchronous detection circuit 9, and the output signal of the analog-to-digital conversion circuit 11 corresponds to a sampling value of the quasi-synchronous detection signal. . The branch metric calculation circuit 12 inputs via the bus 7 a sampling value sequence candidate of the quasi-synchronous detection signal and a complex symbol sequence candidate corresponding to the state transition output from the determination circuit 5, and estimates an estimation error as an index of carrier synchronization. Output a signal.
The determination circuit 5 performs state estimation using the square of the estimated error signal as an input, and determines a complex symbol sequence candidate corresponding to the above-described state transition determined by the signal based on the baseband modulated wave signal from the quasi-synchronous detection circuit 9. Output the output. The signal determination value is output from the output terminal 6.

FIG. 2 shows a block configuration of the branch metric calculation circuit 12. FIG. 2 is a block diagram of the branch metric operation circuit 12. The sampling value y _s (k) of the quasi-synchronous detection signal is input from the input terminal 16. In the following, all signals are represented by a complex representation in which the in-phase component corresponds to the real part and the quadrature component corresponds to the imaginary number. y _s (k) is when the transmission complex symbol and a (k), can be expressed as _{y s (k) = a (} k) h (k) + n (k). Here, the modulation method is QAM (Quadrature Am
(Plitude Modulation) method. h (k) is a carrier signal component and n (k) is a noise component, which is white noise that has passed through the low-pass filter 4.

The signal y _s (k) is input to a shift register 19 composed of delay elements 17 and 18, and a sampled value of the quasi-synchronous detection signal delayed every T is output from the shift register 19. This than the sampling sequence candidate {y _s (i)} of the past quasi-synchronized detection signal as k the current is input to the inverse modulation circuits 20 and 21, the complex symbol sequence candidate corresponding to the state transition is input from the input terminal 29 ｛A
_m (i) is inversely modulated. Here, L is the number of stages of the shift register 19. FIG. 2 shows the case where L = 2.
When a reverse modulated wave signal and _{{z m (i)},} z m (i) = y s (i) / a m (i) = (h (i) a (i) / a m (i)) + n the _{s (i) / a m (} i). The level of the noise component is small, and a _m (i) is a
When (i) coincides, z _m (i) substantially coincides with the carrier signal component h (i). Modulating circuits 22 and 23 modulate the inversely modulated wave signal sequence candidate with the current complex symbol sequence candidate a _m (k) and remodulate signal sequence candidate ｛y
_es (i) is generated. {Y _es (i)} becomes _{y es (i) = z m} (i) a m (k) = y s (i) a m (k) / a m (i). The linear combination of the remodulated signal sequence candidates is
And 25 and an adder 26. The linear combination constant W ₁ set in the multipliers 24 and 25,
W ₂ is fixed and does not change over time. Here, the linear combination is equivalent to performing linear prediction filtering of the current carrier signal component, modulating this prediction value with the current complex symbol sequence candidate, and predicting the current quasi-synchronous detection signal. For example, when assuming that the carrier signal component h (k) does not change with time, the multipliers 24 and 2
Set all the constants set to 5 to 1 / L. That is, the quasi-synchronous detection signal at the present time is predicted by averaging the past remodulation wave signals. When the carrier signal component h (k) fluctuates with time, it is possible to follow the fluctuation by averaging the past remodulated signal so as to reduce the weight.
For example, the weighting constant of y _es (k−k ₁ ) is λ ^k1-1 / (1
-Λ). However, 0 <λ ≦ 1. The subtraction circuit 27 outputs the current quasi-synchronous detection signal y _s (k)
, A linear combination of the re-modulated signals is subtracted from the output to output an estimation error signal. The square operation circuit 28 calculates the square of the estimated error signal, and always outputs the squared value from the output terminal 30 as a positive value.

Next, the operation of the decision circuit 5 will be described. The determination circuit 5 determines the maximum likelihood sequence (Maximum Likelihood Sequence).
Estimation: MLSE) to estimate the state and determine the signal. The MLSE is an estimation method in which likelihood is calculated for all possible symbol sequence candidates, and a code sequence having the largest value is used as a signal determination value. As the transmission complex symbol sequence candidates become longer, the number of all possible complex symbol sequence candidates increases in a designated function. Therefore, a Viterbi algorithm is known as an algorithm for reducing the number of candidates and suppressing the calculation amount. The determination circuit 5 performs MLSE using the Viterbi algorithm.

Next, with reference to FIG. 3, the BPSK (Binary Ph.D.) of the Viterbi algorithm in the first embodiment of the present invention will be described.
ase Shift Keying) Modulation will be described as an example. FIG. 3 is a trellis diagram showing a state transition. First, the state will be described. The complex symbol to be considered is from the current kT to (kL)
Since T a _{to, {a m (i) |} k-L ≦ i ≦ k-1} is called a state. In this case, the number of states is 2 ^L, that is, 2 ² = 4.
Becomes Complex symbol sequence candidates can be described using this state. Let the _s- th state at time k be σ _s
(K). Here, 0 ≦ s ≦ 3 and the time point is k
The state transitions when going from to k + 1. The state transition is a
complex symbol sequence candidate a _m (k + 1) for (k + 1)
Since it depends on the value of 1), two transitions occur from one state. As shown in FIG. 3, the state branches from one state to two states, and merges from two states to one state. A transition metric J _{K + 1} [σ _S (k + 1), σ corresponding to a transition from the state σ _{S ′} (k) to σ _S (k + 1) in order to select one transition from two transitions that merge at the transition destination
_{S '} (k)]. From the state σ _{S ′} (k) to σ _S (k +
The transition metric for the transition to 1) is a branch metric BR [σ _S (k + 1), σ _{S ′} (k)] for each transition.
Is calculated using the following equation: J _{K + 1} [σ _S (k + 1), σ _{S ′} (k)] = J _K [σ _{S ′} (k)] + BR [σ _S (k + 1), σ _{S ′} (k)] Is done. However,

[0028]

(Equation 1) It is. Explaining the meaning of this equation,
Estimate the synchronous detection signal by linear combination of the past remodulated signal,
The estimated error signal is the content of the absolute value on the right side. Complex
If the symbol sequence candidate is correct, this estimated error signal
The absolute square of the noise signal becomes smaller,
You. J _K [σ _{S ′} (k)] is a path metric at time point k and corresponds to likelihood. State transition σ _{S '} (k) →
Transition signal sequence in σ _S (k + 1) is {a _m (k-
1), a _m (k), a _m (k + 1)}. In Viterbi algorithm, J corresponding to two transitions
_{K + 1} [σ _S (k + 1), σ _{S ′} (k)] is compared and the larger transition is selected, and the transition metric of the selected transition is determined by the path metric J _{K + 1} [σ at the time point k + 1.
_S (k + 1)]. Then, only the time series and the path of the state linked to the selected transition are left as the maximum likelihood sequence candidates. When this operation is repeated thereafter, the paths survive the number of states. This pass is called the surviving pass. If all surviving paths merge at some point in the past,
Since the state at that time can be determined, signal determination is performed. However, if they do not merge, the signal determination is postponed. This operation is repeated. Note that, due to memory limitations, the time series of states only stores up to the past (DL + 1) T,
If the surviving paths do not merge at the point of +1) T, the signal is determined based on the path having the maximum likelihood at the present time, that is, the path with the maximum path metric. The signal determined at this time is a signal delayed by DT from the present time, and this DT is referred to as a determination delay time (G, Ungerboeck, "Adaptive maximum li
kelihood receiver for carrier-modulated data-trans
mission systems, "IEEE Trans, Commun, vol, COM-22, pp,
624-636, 1974). However, D ≧ L. As described above, the Viterbi algorithm expresses a symbol sequence candidate using a state, and performs signal estimation by performing state estimation. The initial state of the Viterbi algorithm is determined based on the unique word shown in FIG.

As described above, according to the present invention, the signal determination is performed based on the Viterbi algorithm, and the carrier signal component is predicted based on the state transition of the Viterbi algorithm. Therefore, there is no need to perform carrier phase synchronization. That is, the transmission efficiency of the burst can be increased without the need for the carrier synchronization signal.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram of a branch metric operation circuit of the second embodiment of the present invention. In the device of the second embodiment of the present invention, the configuration of the branch metric operation circuit 12 in the device of the first embodiment of the present invention is different from the signal sequence input to the branch metric operation circuit 12 by the decision circuit 5.

As shown in FIG. 4, the sampling value y _s (k) of the quasi-synchronous detection signal is input from the input terminal 16 to the branch metric calculation circuit 12 of the second embodiment of the present invention. y _s (k) is input to the shift register 19 including the delay elements 17 and 18, and the sampling value of the quasi-synchronous detection signal delayed every T is output from the shift register 19. The sampling sequence candidate {y _s (i)} of the quasi-synchronous detection signal before the present time k is determined by the re-modulation circuits 35 and 36.
, And re-modulated with the phase angle difference signal sequence candidate {b _m (i)} corresponding to the state transition input from the input terminal 29. This phase angle difference signal will be described using differentially encoded PSK modulation as an example. At this time, the amplitude of the complex symbol a (k) is “1”, and the phase angle difference of the complex symbol b (k) = a
The information is included in (k) / a (k-1). If the phase angle difference corresponding to the complex symbol sequence candidate is b _m (k), and this b _m (k) is used to represent the remodulated signal y _es (ki),

[0032]

(Equation 2) Becomes The remodulation circuits 35 and 36 generate remodulation signal sequence candidates according to the above equation, and re-modulate signal sequences y _es (k−1) and
y _es (k−2) is output . The linear combination of the modulated wave signal sequence candidates is obtained by the multipliers 24 and 25 and the adding circuit 26. The constants w1 and w2 of the linear combination set in the multipliers 24 and 25 are fixed and are not changed with time. Here, the linear combination is equivalent to performing linear prediction filtering of the current carrier signal component, modulating this prediction value with the current complex symbol sequence candidate, and predicting the current quasi-synchronous detection signal. For example,
When assuming that the carrier signal component h (k) does not change with time, the constants set in the multipliers 24 and 25 are all set to 1 / L. That is, the quasi-synchronous detection signal at the current time is predicted by averaging the past remodulated signals.
When the carrier signal component h (k) varies with time,
It is possible to follow the fluctuation by averaging so that the weight of the past remodulated signal is reduced. For example, y _es (k−k
There is also a method of setting the weighting constant of ₁ ) as λ ^k1-1 / (1−λ). However, 0 <λ ≦ 1. Subtraction circuit 27
Subtracts the linear combination of the remodulated signal from the current quasi-synchronous detection signal y _s (k) and outputs an estimation error signal. The squaring operation circuit 28 calculates the square of the estimated error signal and outputs it from the output terminal 30.

As a result, similarly to the first embodiment of the present invention, the transmission efficiency of the burst can be increased without the need for the carrier synchronization signal. In addition, by using the phase angle difference signal, the number of states of the Viterbi algorithm can be reduced as compared with the first embodiment of the present invention, and the circuit scale of the determination circuit 5 can be reduced. More specifically, in the second embodiment of the present invention, the phase difference signal to be considered is from the current time kT to (k−L).
+1) T, then ｛b _m (i) | k−L + 1 ≦ i ≦
k-1} becomes the state. In differentially encoded BPSK modulation, the number of states is 2 ^L−1 , and the number of states can be reduced to １ ／ compared to the first embodiment of the present invention.

[0034]

As described above, according to the present invention, since the carrier phase is predicted in accordance with the signal judgment, there is no need to perform carrier phase synchronization. That is, since carrier wave synchronization information is not required for a burst signal used for communication, transmission efficiency of the burst signal can be increased, and a phase synchronization circuit of a receiving device can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram of a device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a branch metric operation circuit according to the first embodiment of the present invention.

FIG. 3 is a trellis diagram showing a state transition diagram.

FIG. 4 is a block diagram of a branch metric operation circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a conventional device and a block diagram of a burst signal.

FIG. 6 is a block diagram of the arithmetic circuit of the prior application.

[Explanation of symbols]

 1, 16, 29 Input terminal 2 Carrier synchronization circuit 3 Multiplier 4 Low-pass filter 5 Judgment circuit 6, 30 Output terminal 7 Bus 8 Carrier frequency regeneration circuit 9 Semi-synchronous detection circuit 11 Analog / digital conversion circuit 12 Branch metric calculation circuit 17, 18 delay element 19 shift register 20, 21, 40 inverse modulation circuit 22, 23 modulation circuit 24, 25 multiplier 26 addition circuit 27 subtraction circuit 28 square operation circuit 35, 36 remodulation circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 27/00-27/38 H03L 7/095

Claims (4)

(57) [Claims] 1. An input terminal from which a burst signal arrives, means for recovering a carrier frequency from a signal at the input terminal,
A multiplier for multiplying the signal at the input terminal by the signal of the carrier frequency reproduced by this means, a low-pass filter through which the output signal of the multiplier passes, and an output signal of the low-pass filter A synchronizing detection circuit having a judgment circuit for judging a modulation signal, an analog-to-digital conversion circuit for converting an output signal of the low-pass filter into a digital signal, and an output of the analog-to-digital conversion circuit. Complex symbol sequence candidate corresponding to state transition of the decision circuit
Is used to generate a remodulated signal sequence candidate.
An estimation error signal is generated from a linear combination of
And an arithmetic circuit for outputting a multiplication value, the decision circuit, the synchronous detection circuit, characterized in that the arrangement for selecting the decision output as the output of the arithmetic circuit is reduced. Wherein said judging circuit is a judgment circuit according to the Viterbi algorithm, the output of the arithmetic circuit is minimized
2. The synchronous detection circuit according to claim 1, further comprising means for setting said complex symbol sequence candidate to a maximum likelihood sequence . 3. An inverse modulation circuit for inversely modulating an output at a past time one or several timings before the analog-to-digital conversion circuit with a symbol sequence candidate at a past time one or several times before the analog / digital conversion circuit. A modulation circuit that modulates the output of the inverse modulation circuit with the current symbol sequence candidate to generate the re-modulated signal sequence candidate; and a linear combination of the generated re-modulated signal sequence candidate with the current analog-to-digital conversion circuit. 3. A subtraction circuit for subtracting from an output, and a circuit for squaring an output of the subtraction circuit as the estimated error signal , wherein an output of the squaring circuit is an output of the arithmetic circuit . Synchronous detection circuit. 4. The arithmetic circuit according to claim 1, wherein the output of the analog-to-digital conversion circuit at one or several previous timings is a phase angle between a symbol sequence candidate at one or several previous timings and a current symbol sequence candidate. A remodulation circuit for remodulating with the difference signal sequence candidate to generate the remodulation signal sequence candidate, and a subtraction circuit for subtracting a linear combination of the generated remodulation signal sequence candidate from the current output of the analog / digital conversion circuit When the output of the subtraction circuit and the
3. The synchronous detection circuit according to claim 1, further comprising a circuit for squaring as an estimation error signal , wherein an output of the squaring circuit is used as an output of the arithmetic circuit.