JPH06216885A - Diversity type synchronization detection circuit - Google Patents

Abstract

PURPOSE:To make the size of the detection circuit small and to simplify the detection circuit by applying inverse modulation to outputs of plural A/D converter circuits respectively by a discrimination symbol series object and selecting the discrimination output so as to reduce the sum of output powers. CONSTITUTION:Carrier frequency synchronization circuits 2, 9 recover a carrier frequency from signals at input terminals 1, 8 receiving a burst signal respectively and multipliers 3, 10 multiply the recovered signal with a signal at the input terminal. Then A/D converter circuits 6, 13 convert an output signal of low pass filters 4, 11 through which the result of multiplication passes into a digital signal, and branch metric arithmetic operation circuits 31, 33 apply respectively inverse modulation to the result of A/D conversion by a series object of a discrimination symbol of a Viterbi algorithm circuit 35. Furthermore, the Viterbi algorithm circuit 35 selects a discrimination output in a way that the sum of output powers of the branch metric arithmetic operation circuits 31, 33 is decreased. Thus, the detection circuit having the same error rate characteristic as that by a maximum ratio synthesis without use of the least square method is made small and simplified.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention is used for digital wireless communication. In particular, it relates to a technology for downsizing and simplifying a detection circuit in a diversity reception system.

[0002]

2. Description of the Related Art In digital radio communication, received power drops due to fading, and error rate characteristics deteriorate significantly. As a technique for overcoming this deterioration, there is a diversity reception system. A conventional apparatus combining maximum ratio combining, which is a kind of diversity receiving method, and synchronous detection will be described with reference to FIG. FIG. 5 is a block diagram of a conventional device. In the conventional example, a case where the number of diversity branches is 2 will be described.

From the input terminal 1, the received wave of the first branch down-converted to the IF band is input. The carrier frequency synchronization circuit 2 extracts a carrier frequency component from this received wave. Since the carrier phase may be indefinite, no special signal such as a carrier synchronizing signal for operating the carrier frequency synchronizing circuit 2 is required. Multiplier 3
Is multiplied by the received wave and the carrier frequency component and input to the low-pass filter 4. The low-pass filter 4 removes unnecessary high-frequency components and extracts baseband modulated wave components. The AD conversion circuit 6 samples this baseband modulation component at the symbol period T of the modulated wave, converts it into a digital signal, and inputs it to the multiplier 7. Here, the carrier frequency synchronizing circuit 2, the multiplier 3, and the low-pass filter 4 are components of the quasi-synchronous detection circuit 5, and the output signal of the AD conversion circuit 6 is a sampling value of the quasi-synchronous detection signal of the first branch. Equivalent to. The received wave of the second branch down-converted from the input terminal 8 to the IF band is also processed in the quasi-synchronous detection circuit 12 in the same manner as the quasi-synchronous detection circuit 5, and the output signal of the AD conversion circuit 13 is the second signal. It corresponds to the quasi-synchronous detection signal sampling value of the branch.

In the multiplier 7, the sampling value of the quasi-coherent detection signal of the first branch includes a phase for removing the carrier phase of the first branch, and the amplitude is proportional to √ (S / N). Is multiplied by. Similarly, the multiplier 14
Then, the sampling value of the quasi-coherent detection signal of the second branch is multiplied by a weighting coefficient including a phase for removing the carrier phase of the second branch and having an amplitude proportional to √ (S / N). The adder circuit 16 adds the output signals of the multiplier 7 and the multiplier 14, and inputs them to the determination circuit 17. The decision circuit 17 makes a signal decision by hard decision and outputs a decision output from the output terminal 19. The subtraction circuit 18 subtracts the determination output from the output signal of the addition circuit 16 and outputs a determination error signal. The weighting coefficient control circuit 15 uses the least squares method so that the square of the decision error signal is minimized.
And the weighting coefficient of the multiplier 14 is estimated and output.

[0005]

Since the weighting coefficient control circuit 15 uses the least squares method for weighting coefficient estimation, it has a drawback that the amount of calculation is large and the circuit scale is large. Further, although there is selective combining or the like as a diversity receiving system which does not include weighting coefficient estimation, the error rate characteristic is deteriorated as compared with the maximum ratio combining.

The present invention has been made against such a background, has the same error rate characteristic as the maximum ratio combining without using a complicated operation such as the least square method, and makes the detection circuit compact and simple. An object of the present invention is to provide a diversity type synchronous detection circuit that can be realized. It is another object of the present invention to provide a diversity-type synchronous detection circuit that can perform signal determination by maximum likelihood determination even if the reproduced carrier wave is not synchronized and can use a signal that does not require carrier wave synchronization information as a transmission signal.

[0007]

SUMMARY OF THE INVENTION The present invention is directed to a plurality of input terminals to which burst signals arrive, means for regenerating carrier wave frequencies from the signals of the plurality of input terminals, and respective carrier waves regenerated by this means. A plurality of multipliers for multiplying the frequency signal and the signals at the plurality of input terminals respectively; a plurality of low-pass filters through which the output signals of the plurality of multipliers pass; and a plurality of low-pass filters of the plurality of low-pass filters. It is a diversity type synchronous detection circuit provided with one judgment circuit which judges a modulation signal based on an output signal.

Here, a feature of the present invention is that a plurality of analog / digital conversion circuits for converting the respective output signals of the plurality of low-pass filters into digital signals, and the plurality of analog / digital conversion circuits. A plurality of arithmetic circuits each including an inverse modulation circuit that performs inverse modulation with each of the determination symbol sequence candidates of the determination circuit, and the determination circuit is a sum of output powers of the plurality of arithmetic circuits. The configuration is such that the judgment output is selected so that becomes smaller.

The determination circuit is a determination circuit based on a Viterbi algorithm, and it is preferable that the determination circuit includes means for maximizing the likelihood of a symbol candidate having the smallest sum of the output powers.

The arithmetic circuit includes an inverse modulation circuit for the current output of the analog-digital conversion circuit, an inverse modulation circuit for the past output of one or several timings before, and an inverse modulation circuit for the past output. A subtraction circuit for subtracting the linear combination of the outputs from the output of the inverse modulation circuit with respect to the current output; and a circuit for squaring the output of the subtraction circuit, wherein the output of the squaring circuit is the signal representing the output power. Is desirable.

[0011]

The carrier component is extracted from the input signal, the carrier frequency regenerating circuit is activated at that frequency, and the signal generated by this carrier frequency regenerating circuit is multiplied by the received signal. At this time, the frequency of the reproduced carrier wave is synchronized with the received carrier wave, but the phase is indeterminate.

A high-frequency component is removed by a low-pass filter to extract a baseband modulated wave component. This baseband modulated wave component is input to the analog / digital circuit and is sampled at the sampling period T which is the symbol period of the modulated wave. This is for performing digital processing in the subsequent stage.

The sampled signal is inversely modulated by the complex symbol sequence corresponding to the state transition of the Viterbi algorithm of the decision circuit. Furthermore, past sampled signals such as T period and 2T period from the present time are also used for T period before and 2T period in the Viterbi algorithm, respectively.
It is inversely modulated by a complex symbol sequence corresponding to each state transition such as before the period.

The difference between the present inverse modulation signal and the linear combination of past inverse modulation signals is taken. If the difference is close to zero, the complex symbol sequence corresponding to the state transition matches the transmitted symbol sequence. On the contrary, the larger the difference is, the more different the complex symbol sequence corresponding to the state transition is from the transmission symbol sequence.

Therefore, this difference is squared to obtain a value proportional to the output power, and the sum is always input to the determination circuit as a positive value. This signal serves as an index indicating the likelihood in the Viterbi algorithm, and the decision circuit refers to this signal and selects the symbol candidate with the maximum cumulative value of this signal as the maximum likelihood. That is, the estimated error signal for each diversity branch is generated by subtracting the linear combination of the past inverse modulated wave signal from the current inverse modulated wave signal, and the sum of squares of the estimated error signals obtained by adding for each diversity branch is input. As a result, the state is estimated by the Viterbi algorithm to determine the signal.

With this, the signal can be determined by the maximum likelihood determination even if the reproduced carrier wave is not synchronized. Therefore, a signal that does not require carrier wave synchronization information can be used as the transmission signal, and the carrier wave phase synchronization of the receiver can be performed. No circuit is needed. Further, since a complicated calculation means such as the least square method is not used, the circuit can be downsized and simplified.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

According to the present invention, two input terminals 1 and 8 to which a burst signal arrives, and the two input terminals 1 and 8
Carrier frequency synchronizing circuits 2 and 9 as means for reproducing the carrier frequency from the respective signals, the respective carrier frequency signals reproduced by the carrier frequency synchronizing circuits 2 and 9, and the signals at the two input terminals 1 and 8. Two multipliers 3 and 10 for respectively multiplying and
, Two low-pass filters 4 and 11 through which the output signals of the two multipliers 3 and 10 pass, respectively, and a modulation signal is determined based on the output signals of the two low-pass filters 4 and 11. This is a diversity type synchronous detection circuit including a Viterbi algorithm circuit 35 as one determination circuit.

Here, the feature of the present invention is that two AD conversion circuits 6 and 1 for converting the output signals of the two low-pass filters 4 and 11 into digital signals, respectively.
3 and a branch metric operation circuit 31 as two operation circuits including an inverse modulation circuit that performs inverse modulation on the respective outputs of the two AD conversion circuits 6 and 13 with the decision symbol sequence candidates of the Viterbi algorithm circuit 35. And 33, and the Viterbi algorithm circuit 35 is configured to select the judgment output so that the sum of the output powers of the two branch metric operation circuits 31 and 33 becomes small.

Next, the operation of the embodiment of the present invention will be described. The received wave of the first branch down-converted to the IF band is input from the input terminal 1. The carrier frequency synchronization circuit 2 extracts a carrier frequency component from this received wave.
The multiplier 3 multiplies the received wave by the carrier frequency component and inputs the product into the low-pass filter 4. The low-pass filter 4 removes unnecessary high-frequency components and extracts baseband modulated wave components. AD
The conversion circuit 6 samples this baseband modulated wave component at the symbol period T of the modulated wave, converts it into a digital signal, and inputs it to the branch metric calculation circuit 31. Here, the carrier frequency synchronizing circuit 2, the multiplier 3, and the low-pass filter 4 are components of the quasi-synchronous detection circuit 5, and the output signal of the AD conversion circuit 6 is the quasi-synchronous detection signal sampling value of the first branch. Equivalent to. The received wave of the second branch down-converted to the IF band input from the input terminal 8 is also processed in the quasi-synchronous detection circuit 12 in the same manner as the quasi-synchronous detection circuit 5, and the output signal of the AD conversion circuit 13 is
It corresponds to the quasi-coherent detection signal sampling value of the second branch.

Branch metric calculation circuits 31 and 3
3 receives the quasi-coherent detection signal sampling sequence of each diversity branch and the complex symbol sequence candidate corresponding to the state transition output from the Viterbi algorithm circuit 35 as an input and outputs the square of the estimation error signal of each diversity branch. The adder circuit 16 inputs the square of the estimated error signal of each diversity branch, and outputs the sum of squares of the estimated error signal obtained by adding for each diversity branch.
The Viterbi algorithm circuit 35 uses the estimated error signal 2
State estimation is performed using the sum of multiplications as an input, and a complex symbol sequence candidate corresponding to the above-described state transition and a determination output are output. The determination output is output from the output terminal 19.

The branch metric operation circuits 31 and 33 will be described with reference to FIG. FIG. 2 is a block diagram of the branch metric operation circuits 31 and 33. The quasi-synchronous detection signal sampling value y _s (k) of the diversity branch is input from the input terminal 37. In the following, all signals are represented in complex representation, where the in-phase component corresponds to the real part and the quadrature component corresponds to the imaginary number. y _s (k) is the transmitted complex symbol a
(K) can be expressed as y _s (k) = h (k) a (k) + n (k) (1). Here, the modulation method is QAM (Quadrature
Amplitude Modulation) method. h (k) is a carrier signal component, n (k) is a noise component, and the low-pass filter 4
And white noise that has passed 11 and 11.

Y _s (k) is input to the shift register 40 including the delay element 38 and the delay element 39, and the quasi-synchronous detection signal sampling value delayed for each T is output from the shift register 40. The quasi-coherent detection signal sampling sequence {y _s (i)} is input to the inverse modulation circuits 41, 42 and 43 and is inverted by the complex symbol sequence candidate {a _m (i)} corresponding to the state transition input from the input terminal 49. Is modulated. Here, L is the number of stages of the shift register 40. In FIG. 2, L
= 2 is shown. When a reverse modulated wave signal and _{{z m (i)},} z m (i) = y s (i) / a m (i) = [(h (i) a (i )) / a m (i) ] + to become _{[n s (i) / a m} (i) ] ... (2). The noise component level is small and a _m (i) is a
When it matches with (i), z _m (i) is the carrier component h
It almost matches with (i). The linear combination of the inverse modulated wave signal sequence from the present time to the past is performed by the multipliers 44 and 45 and the addition circuit 4
6 is required. The linear coupling constants w1 and w2 set in the multipliers 44 and 45 are fixed and do not change with time. The linear combination here is equivalent to the linear predictive filtering of the current carrier component. For example, assuming that the carrier component h (k) does not change with time, all the constants set in the multipliers 44 and 45 are 1 / L.
To That is, the current inverse modulated wave signal is predicted by averaging the past inverse modulated wave signals. When the carrier component h (k) temporally fluctuates, the weighting of the inverse modulated wave signal in the past is reduced so as to follow the fluctuation by averaging it. For example, there is a method of setting the weighting constant of y _s (k−k ₁ ) as λ ^k1-1 / (1−λ).
However, 0 <λ ≦ 1. The subtraction circuit 47 subtracts the linear combination of the inverse modulated wave signal series from the present time to the past from the present semi-synchronous detection signal sampling value y _s (k) and outputs an estimation error signal. The square calculation circuit 48 calculates the square of the estimated error signal and outputs it from the output terminal 50.

Next, the operation of the Viterbi algorithm circuit 35 will be described. The Viterbi algorithm circuit 35 uses Maximum Likelihood Sequence Estimation:
MLSE) estimates the state and judges the signal. MLSE
Is an estimation method in which the likelihood is calculated for all possible complex symbol sequence candidates and the complex symbol sequence candidate having the largest value is used as the signal determination value. As the complex symbol sequence becomes longer, the number of possible sequences increases by a specified function. Therefore, the Viterbi algorithm is known as an algorithm that reduces the number of sequences to reduce the calculation amount. The Viterbi algorithm circuit 35 performs MLSE by the Viterbi algorithm.

Next, referring to FIG. 3, regarding the Viterbi algorithm in the embodiment of the present invention, a BPSK (Binary Phase)
Shift Keying) An example of modulation will be described. FIG. 3 is a trellis diagram showing state transitions. First, the state will be described. Since the complex symbols to be considered are from the current k to (k−L), {a _m (i) | k−L ≦ i ≦ k−1} is called a state. In this case, the number of states is 2 ^L. Complex symbol sequences can be described using this state. The sth state at time point k is σ _s (k). Here, 0 ≦
When s ≦ 3, the state transitions when the time point advances from k to k + 1. Since the state transition depends on the value of the complex symbol candidate a _m (k + 1) for a (k + 1), two transitions occur from one state. As shown in FIG. 3, it branches from one state to two states and merges from two states to one state. 1 out of 2 transitions that merge at the transition destination
States σ _s' (k) to σ _s (k
Transition metric J _{k + 1} [σ _s corresponding to the transition to (+1)
(K + 1), σ _{s ′} (k)] is used. The transition metric at the transition from the state σ _{s ′} (k) to σ _s (k + 1) is
Branch metric BR [σ _s (k + 1),
σ _{s ′} (k)], J _{k + 1} [σ _s (k + 1), σ _{s ′} (k)] = J _k [σ _{s ′} (k)] + BR [σ _s (k + 1), σ _{s '} (K)] ... (3) is calculated. However,

[0026]

[Equation 1] Is. Here, b is a subscript indicating a diversity branch, and Z _mb (k) is an inverse modulation signal of the b-th diversity branch. J _k (σ _{s ′} (k)) is the path metric at the time point k and corresponds to the likelihood. State transition σ _s' (k) → σ transition signal sequence in _s (k + 1) is _{{a m (k-1)} , a m (k), a m (k + 1)} represented by. In the Viterbi algorithm, J _{k + 1} [σ _s (k + 1), σ _{s ′} (k)] corresponding to two merging transitions are compared, the larger transition is selected, and the transition metric of the selected transition is selected. Is the path metric J at time k + 1
_{k + 1} [σ _s (k + 1)]. Then, only the time series (path) in a state linked to the selected transition is left as the maximum likelihood series candidate. After that, when this operation is repeated, as many paths as the number of states survive. This pass is called the survival pass. If all surviving paths meet at some point in the past, the state at that point can be determined, and signal determination is performed. However, if they do not merge, the signal determination is postponed. The above operation is repeated. Note that due to memory restrictions,
The time series of states is stored only up to the past (D-L + 1) T, and if the surviving paths do not merge at the time of the past (D-L + 1) T, the path with the maximum likelihood at this point, that is, the path with the maximum path metric, is selected. Based on this, signal determination is performed. The signal judged at this time is DT delayed from the present time, and this DT is called a judgment delay time (G, Ungerboeck, "Ada
ptive maximum likelihood receiver for carrier-modu
lated data-transmission systems, "IEEE Trans, Commu
n, vol, COM-22, pp, 624-636,1974). However, D ≧ L.

A computer simulation was conducted to confirm the effect of the present invention. The result is shown in FIG. Figure 4
FIG. 4 is a diagram showing a result of computer simulation. Note that the number of branches is 2, L = 4, the modulation method is QPSK modulation with roll-off 0.5, the transmission line is Rayleigh fading, and the maximum Doppler frequency f ₀ is 0 Hz. The dotted line in FIG. 4 is the theoretical value of the maximum ratio combination, and the simulation result almost agrees with this theoretical value.

[0028]

As described above, according to the present invention,
It has the same error rate characteristics as maximum ratio combining without using complicated operations such as the least squares method, and the detection circuit can be miniaturized and simplified. Further, since signal determination by maximum likelihood determination can be performed even if the reproduced carrier wave is not synchronized, a signal that does not require carrier wave synchronization information can be used for the transmission signal, and a circuit for carrier wave phase synchronization of the receiving device is unnecessary. Become.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of a branch metric operation circuit.

FIG. 3 is a trellis diagram showing state transitions.

FIG. 4 is a diagram showing a result of computer simulation.

FIG. 5 is a block diagram of a conventional device.

[Explanation of symbols]

 1, 8, 37, 49 Input terminals 2, 9 Carrier frequency synchronization circuit 3, 10, 7, 14, 44, 45 Multiplier 4, 11 Low-pass filter 5, 12 Quasi-synchronous detection circuit 6, 13 AD conversion circuit 15 Weighting coefficient control circuit 16, 46, 20 Adder circuit 17 Judgment circuit 18, 47 Subtractor circuit 19, 50 Output terminal 31, 33 Branch metric operation circuit 35 Viterbi algorithm circuit 38, 39 Delay element 40 Shift register 41, 42, 43 Inverse modulation Circuit 48 Square arithmetic circuit

Claims (3)

[Claims] 1. A plurality of input terminals to which a burst signal arrives, a means for reproducing a carrier frequency from each of the signals at the plurality of input terminals, a signal of each carrier frequency reproduced by the means, and the plurality of inputs. A plurality of multipliers that respectively multiply the signals at the terminals, a plurality of low-pass filters through which the output signals of the multipliers pass, and a modulation signal based on the output signals of the plurality of low-pass filters. In the diversity type synchronous detection circuit having one judgment circuit for judging the above, a plurality of analog-digital conversion circuits for converting the respective output signals of the plurality of low-pass filters into digital signals, and the plurality of analog A plurality of arithmetic circuits each including an inverse modulation circuit for inversely modulating each output of the digital conversion circuit with a sequence candidate of the determination symbol of the determination circuit. For example, the determination circuit, diversity synchronous detection circuit, wherein the sum of the output power of the plurality of arithmetic circuits are configured to select a decision output to be smaller. 2. The diversity type synchronous detection circuit according to claim 1, wherein the decision circuit is a decision circuit based on a Viterbi algorithm, and includes means for maximizing a symbol candidate having the smallest output power. 3. The operation circuit includes an inverse modulation circuit for the current output of the analog-digital conversion circuit, and 1
Alternatively, a subtraction circuit for subtracting a linear combination of the output of the inverse modulation circuit with respect to the output of the past time point and the output of the inverse modulation circuit with respect to the output of the past time point from the output of the inverse modulation circuit for the output at the present time point, and this subtraction circuit 3. A diversity type synchronous detection circuit according to claim 1, further comprising a circuit for squaring an output, wherein the output of the squaring circuit is a signal representing the output power.