JPH06216237A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the electrostatic breakdown of a very thin insulating film which is caused in a process wherein charged particles are used. CONSTITUTION:A method for manufacturing a semiconductor device wherein many device chips are formed on a substrate 36, a region separating process is included wherein a region where many device chips are formed is separated into several parts 32, 33 and an insulator 35 is formed between the two adjacent parts to electrically separate the parts.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor in which an object to be processed is exposed to charged particles or a gas atmosphere containing the charged particles for processing.

[0002]

2. Description of the Related Art FIG. 10 is a sectional view of a schematic structure of an etching apparatus that has been widely used conventionally in microfabrication in a semiconductor element manufacturing process. In FIG. 10, the reactive gas is supplied from the inlet 4 into the reaction container 1. High frequency power is applied to the cathode 2 by the high frequency power source 5,
Plasma 15 is generated in the reaction container 1. Cathode 2
The wafer 3 is arranged above. The reactive ions in the plasma 15 are accelerated by the self-bias electric field 10 induced on the surface of the cathode 2 or the wafer 3.
The accelerated reactive ions impact the wafer 3 and the etching reaction proceeds. The self-bias electric field 10 changes according to conditions such as gas and RF power, the shape of the electrode, the cathode or anode electrode area ratio, and the like. In a practical device, an accelerating voltage due to the self-bias electric field 10 of about 100 eV to 500 eV is usually induced.

[0003]

As is well known, the so-called reactive ion etching apparatus described above has made a great contribution to the fine processing of semiconductors. However, miniaturization of semiconductor devices has progressed remarkably, and even such an excellent device has the following problems in future device fabrication.

It is a problem with radiation damage. In processing a gate portion which is an active portion of the device or a portion electrically connected to the gate electrode, various damages are caused by bombarding the active portion of the device with high energy ions. For example, the metal on the inner wall of the reaction container is released into the gas phase by the sputtering action, and the metal is injected into the gate portion or the substrate. As a result, a new impurity level is formed and the operating characteristics of the device change.
Further, during the etching, the wafer is in a floating state because it is not galvanically connected to anything. As shown in FIG. 13, when the gate electrode of the transistor is formed, the electrode pattern 114 under the mask 113 is left and the conductor film of the other portion is etched. Both sides of the thin insulating film 115 are thick oxide films 1 for element isolation.
It is connected to 17. At the time of over-etching, the resist mask 113 and the etched pattern 114 on the thin insulating film 115 are in a floating state with respect to the substrate 116 and are charged, and a potential difference is generated between the resist mask 113 and the substrate. This charging occurs because the amount of charge accumulated in the gate electrode 114 is different from that on the substrate side due to the emission of electrons, ions or secondary electrons from the plasma. When such charging is remarkable, the gate insulating film 115 is destroyed.
In recent years, an extremely thin insulating film 115 has been used in order to obtain a large capacitance with a small area. For example, a 50 angstrom SiO ₂ film may be destroyed only by applying a potential of about 5V. All such destructions occur due to the method itself of performing etching by irradiating charged particles, and are inevitable in principle.

Such problems occur not only in the etching technique but also in other processes using charged particles. For example, in plasma CVD (chemical vapor deposition) in which a substrate is exposed to charged particles in the process of forming a thin film, when an insulating film is formed on an already formed wiring or electrode, destruction occurs at the initial stage. It is known that this breakdown causes a large variation in the characteristics of the device. Also in the ion implantation technique, the electrode in a floating state is charged and the underlying thin insulating film is destroyed. Thus, breakdown due to charging is a serious problem in any charged particle utilization process. On the other hand, with the progress of miniaturization, the directional process using charged particles is becoming more and more essential.

As described above, in the conventional treatment using charged particles, when at least a part of the conductor electrode in contact with the thin insulating film or the wiring electrically connected to the electrode is exposed to plasma, the thin insulating film is exposed. In some cases, an electric field is generated in the insulating film, electrons and holes are formed in the insulating film, deteriorating the device characteristics, and further causing dielectric breakdown. If it is destroyed,
It is completely impossible to recover by subsequent processing, and even if it is compared with other radiation damage, it is a fatal damage to the device. Further, even in the case where the above breakdown does not occur, the element characteristics are greatly affected such as the phenomenon that the threshold value of the transistor characteristics varies and the reliability decreases over a long period of time.

Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art, and when processing a semiconductor device using charged particles, damage such as device capacitance, gate portion dielectric breakdown, breakdown voltage deterioration, and the like. It is an object of the present invention to provide a method for manufacturing a semiconductor device that does not involve the above. [Structure of Invention]

[0008]

In order to achieve the above object, the present invention provides a semiconductor device manufacturing method for manufacturing a large number of device chips on a substrate, wherein a plurality of regions in which the large number of device chips are formed are provided. The method is characterized by including a region dividing step of forming an insulator that divides into regions and electrically separates these adjacent regions.

Here, in this region dividing step, the object to be processed having the conductor film on the dielectric film formed on the semiconductor substrate is exposed to charged particles or a gas atmosphere containing the charged particles to partially expose the conductor film. Before the charging treatment step of etching to expose the dielectric film to the surface of the object to be processed, or having a conductor pattern on the first dielectric film formed on the semiconductor substrate and forming a second conductor pattern on the conductor pattern. A charging treatment step of exposing the object having the dielectric film to charged particles or a gas atmosphere containing the charged particles to etch a part of the second dielectric film to expose the conductor pattern on the surface of the object. Better to do it before.

Further, according to the present invention, an object to be processed having a conductor film on a dielectric film formed on a semiconductor substrate is exposed to charged particles or a gas atmosphere containing the charged particles to etch a part of the conductor film. Before the charging processing step of exposing the dielectric film to the surface of the object to be processed, a conduction processing step of exposing the semiconductor substrate or a conductor electrically connected to the semiconductor substrate to the surface of the object to be processed is provided. Is characterized by.

Further, according to the present invention, an object to be processed having a conductor pattern on a first dielectric film formed on a semiconductor substrate and a second dielectric film on the conductor pattern is charged particles or charged particles. Before a charging treatment step of exposing a portion of the second dielectric film to a surface of the object to be exposed by exposing the conductor pattern to a gas atmosphere containing
It is characterized by comprising a conduction treatment step of exposing the semiconductor substrate or a conductor electrically connected to the semiconductor substrate to the surface of the object to be treated.

Further, according to the present invention, an object to be processed having a conductor film on a dielectric film formed on a semiconductor substrate is exposed to charged particles or a gas atmosphere containing the charged particles to etch a part of the conductor film. The charging treatment step of exposing the dielectric film to the surface of the object to be processed is stopped before the dielectric film is exposed to the surface of the object to be processed, and thereafter the dielectric film is exposed to the object to be processed without using charged particles. It is characterized by comprising an exposing step of exposing the surface.

Further, according to the present invention, the object to be processed having the conductor pattern on the first dielectric film formed on the semiconductor substrate and the second dielectric film on the conductor pattern is charged particles or charged particles. Before exposing the conductor pattern to the surface of the object to be processed, exposing the surface of the object to be processed by etching a part of the second dielectric film by exposing it to a gas atmosphere containing The method is characterized by further comprising an exposing step of exposing the conductor pattern to the surface of the object to be processed without using charged particles.

[0014]

According to the present invention, the region where a large number of chips of the semiconductor substrate are formed is divided into a plurality of regions, and the indigo is divided by an insulator to prevent the nonuniformity of the plasma distribution in each region. Can be reduced.

Further, according to the present invention, before the charging treatment step of exposing the object to be processed to charged particles or a gas atmosphere containing the charged particles to expose the dielectric film or the conductor pattern on the surface of the object to be processed, By performing the conduction treatment step of exposing the conductor electrically connected to the substrate or the semiconductor substrate to the surface of the object to be treated, it is possible to make the conductor pattern and the semiconductor substrate and the like have substantially the same potential during the charging treatment step. it can. That is, when some voltage is generated between the surface of the object to be processed and the semiconductor substrate while the object to be processed is exposed to the charged particles or a gas atmosphere containing the charged particles, the conductivity on the thin insulating film on the semiconductor substrate is reduced. An electric field is prevented from being applied to the insulating film by setting the electrodes such as the film and the semiconductor substrate itself to substantially the same potential. This prevents potential difference from occurring on both sides of the gate oxide film, for example. Therefore, there is no deterioration of the insulating film, and devices can be formed with a high yield.

Furthermore, according to the present invention, the dielectric film is subjected to a charging treatment step in which the object to be processed is exposed to a gas atmosphere containing charged particles or home electric particles to expose the dielectric film or the conductor pattern on the surface of the object to be processed. Since the exposure process is stopped before the conductor pattern is exposed on the surface of the object to be processed, and the exposure step is performed without using charged particles after that, no voltage is generated between the conductor pattern and the semiconductor substrate during the exposure.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. An example of an apparatus for carrying out the embodiment of the present invention is shown in FIG. In FIG. 10, the reactive gas is supplied into the reaction container 1 through the inlet valve 4. Radio frequency (RF) power source for exciting plasma (eg frequency 13.56 MH
High frequency power is applied to the susceptor 2 forming the cathode by z) 5, and plasma 13 is generated in the reaction container 1. A wafer 3 is arranged on the susceptor 2. The reactive ions in the plasma 13 are self-bias electric field 1 induced on the surface of the susceptor 2 or the wafer 3.
Accelerated by zero. The accelerated reactive ions impact the wafer 3 and the etching reaction proceeds. The self-bias electric field 10 changes according to conditions such as gas and RF power, the shape of the electrode, the cathode or anode electrode area ratio, and the like. In a practical device, typically 100 eV to 5
An acceleration voltage due to the self-bias electric field 10 of about 00 eV is induced. The coolant is circulated through the pipe 6,
The temperature (wafer temperature) of the susceptor 2 is controlled. Reference numeral 7 is an insulating material for insulating the susceptor 2 from the vacuum container 1 (ground potential), and reference numeral 11 shows a direction in which gas is exhausted by a vacuum pump (not shown).

By the RF power applied to the susceptor 2,
Plasma of the reactive gas used for etching is excited in the vacuum container 1. At this time, on the surface of the wafer 3 or the susceptor 2 exposed to the plasma, a self-bias voltage 10, which is a negative voltage called self-bias, is induced in the direction of the arrow in the drawing between the wafer 3 and the susceptor 2. The self-bias voltage 10 accelerates the ions in the plasma toward the wafer 3. Due to this ion bombardment, etching proceeds in the vertical direction. This self-bias voltage 10 plays an essentially important role in promoting etching. However, on the other hand, it is also a cause of the electrostatic breakdown that the present invention is trying to solve. For example, in the surface of a large diameter wafer, the value Vdc of the self-bias voltage 10 may vary depending on the location due to the non-uniformity of the plasma distribution, and the variation in the value Vdc is one of the damages such as electrostatic breakdown. Probably the cause.

Next, referring to FIG. 11, a simplified model of the mechanism of occurrence of damage such as electrostatic breakdown described above is shown. FIG. 11 is a cross-sectional view of the upper portion of the vacuum chamber 1 in FIG. 10, that is, the anode 12, the patterned wafer 3, the susceptor 2 serving as a cathode, and a central portion 13 and a peripheral portion 14 of the wafer 3 in detail. It was
The dimensions in the drawing are arbitrarily set and shown for easy description.

In FIG. 11, a plasma portion 15 is one in which the gas is ionized, and a portion 16 called a positive column thereof.
There are almost the same amount of ions and electrons in. Therefore, since the positive column portion 16 has high electrical conductivity and an electric field is hard to be generated inside, the so-called plasma potential (Vp) which is the potential of this portion is settled to a substantially constant amount. The positive column portion 16 is connected to the wafer 3 via a sheath portion 17 in which an electric field E18 due to self-bias (Vdc) exists.
Will be in contact with. Here, consider the MOS capacitors A and B formed at two points having different self-bias voltages. The self-bias voltages Vdc _A and Vdc _{B on} the electrode surfaces of the MOS capacitors A and B are the positive column and MO, respectively.
It can be considered by replacing with the power supplies V _A 18 and V _B 19 connected between the S capacitors. The positive column portion 16 has a resistance Rplasma 2 between the central portion 13 and the peripheral portion 14 of the wafer 3.
It can be considered as a conductor having 0, and the Si substrate on which the MOS capacitor is formed can also be considered as a conductor having the resistance Rsub 21. When considering the equivalent circuit between the actual plasma and the substrate, it is necessary to further consider the diode and the capacitance component, but this does not matter because a transient phenomenon is not dealt with here.

Further, when the capacitances of the gate oxide films 22 and 23 of the MOS capacitors A and B are replaced with C _A and CB, the equivalent circuit can be further simplified and can be shown as shown in FIG. Further, if only static characteristics are considered, it can be shown as shown in FIG. That is, it is understood that when a bias potential on the substrate surface varies within the plane of the wafer 3, the potential difference is applied to the thin gate oxide films 22 and 23 via the substrate and plasma. In FIG. 11, a model was considered by taking two capacities of the wafer central portion 13 and the peripheral portion 14. However, in reality, many MOS capacitors exist at different Vdc values. Therefore, it is assumed that the surface potential is roughly divided into a Vdc _A portion and a Vdc _B portion, and the ratio of the number of capacitors belonging to each portion is n: 1. This is
Corresponding to C _A = nC _B in (b), the potential difference V _A −V _B (= ΔV) is distributed between the two parts at a rate inversely proportional to the value of the capacitance, resulting in Narrow V
The voltage applied to the MOS capacitor in the part of dc _B is Vdc _A
Is n times the voltage applied to the part. Therefore, when the potential distribution on the surface changes sharply, the high voltage is M
It can be seen that it is applied to the gate oxide film of the OS capacitance, and electrostatic breakdown easily occurs.

A first embodiment of the present invention will be described with reference to FIG. Before advancing a charging treatment step of exposing a target object having a large number of MOS capacitors 39 formed on a semiconductor substrate, for example, a silicon substrate 31 to charged particles or a gas atmosphere containing the charged particles to expose the surface of the target object, Many MO
The region where the S capacitor 39 is formed is divided into a plurality of regions 32 and 33, and an insulating region 35 that electrically divides these adjacent regions is formed. As a result, above the Si substrate 31, the element formation region 3 including many MOS capacitors 39 is formed.
2, 33 are formed. An insulating region 35 for electrically insulating these is formed between the element forming regions 32 and 33.
Are formed. The presence of the insulating region 35 electrically separates the element regions 32 and 33. As a result, for example, the in-plane of the large diameter wafer is divided into fine regions by the insulating region 35. By selecting the size of the divided region so that the non-uniformity of the plasma distribution in this region is sufficiently small, the value Vd of the self-bias voltage 10
It is possible to reduce the variation of c and prevent damage such as electrostatic breakdown.

For the insulating region 35, specifically, a SiO ₂ film or a so-called SIO (Silicon On Insulator) substrate is used, and an insulating material such as sapphire may be used. In this case, this insulating film is also present in the lower portion 36 of the element formation region. Note that a similar structure can be formed by using a substrate having a very high specific resistance to which impurities are not added. That is, the shaded portions 35 and 36 in FIG.
It is also possible to add a predetermined impurity to the 7,38 portion.

In these structures, the insulating region 35
The width of may be fine if it is insulated. Also,
A space for cutting the completed wafer into individual chips and a dicing line may be used as this area. The effective width of the element formation portion depends on the distribution of Vdc generated during surface treatment using plasma.
If the change of c is about 2 cm, it is considered that there is no voltage difference enough to destroy the MOS capacitance. Therefore, it is not necessary to form the insulating region 35 in the chip, and as described above, the insulating region is not formed on the dicing line. It was confirmed experimentally that the formation of the

Next, a second embodiment will be described with reference to FIG. As shown in FIG. 2, holes 51 and 52 are formed in the insulating films 22 and 23 near the MOS capacitors A and B, respectively. After that, the object to be processed is exposed to the charged particles or a gas atmosphere containing the charged particles to process the object to be processed.

In FIG. 2, the plasma 16 is electrically connected to the substrate 3 through the sheath 17 through the holes 51 and 52 formed in the insulating films 22 and 23. As a result, as shown in the equivalent circuit in FIG. 2, the upper electrodes of the MOS capacitors A and B have substantially the same potential as the lower parts of the gate oxide films 22 and 23 in the vicinity of the MOS capacitors A and B, respectively, and the gate oxide films are not affected by the voltage. It can be seen that is not applied. Further, the voltage due to the difference in self-bias Vdc is simply applied between two points on the surface of the substrate, and as a result of the current flowing through the substrate, a potential gradient is generated and electrostatic breakdown of the gate oxide film does not occur.

It should be noted that such holes 51 and 52 are formed in individual M
It is not necessary for the OS capacitance, and in practice, at least one insulating region 35 may be provided in a certain area, as in the case where the insulating region 35 is provided. Specifically, ΔV
It suffices to make holes 51, 52, etc. so that the holes 51, 52, etc. are divided into regions where destruction does not occur. Therefore, depending on the individual device and process conditions, it is sufficient to provide at least one chip in each chip having a size of several mm square. Further, it can be provided in a gap between complicated elements, but it is more preferable if it is formed in a dicing line portion having a sufficient gap.

Further, in forming the hole, it is not necessary to add a step of forming the hole in advance, and it is sufficient that the hole is formed before the upper electrode of the MOS capacitor is directly exposed to plasma and applied with a potential. That is, in the case of the etching process, holes for preventing electrostatic breakdown can be simultaneously formed in the process.

Next, a third embodiment will be described with reference to FIG. In FIG. 3A, a thin gate oxide film 62 is formed on the semiconductor substrate 3. Element isolation oxide films 63 are formed on both sides of the thin gate oxide film 62. A polycrystalline Si layer serving as a gate electrode 61 is formed on the gate oxide film 62 and the element isolation oxide film 63.
A resist mask 64 is formed on the polycrystalline Si layer to be formed. A hole 65 is formed in the element isolation oxide film 63, a conductor forming the electrode 61 extends through the hole 65, and a part of the semiconductor substrate 3 is electrically connected to the semiconductor substrate 3, for example, at a position 66.

After the treatment as described above, as shown in FIG. 3B, the object to be treated is exposed to charged particles or a gas atmosphere containing the charged particles to perform an etching treatment. The shape of the electrode 61 after etching is as shown in FIG. 68 (b).

Although Vdc is applied to the electrode 61 during etching, the same voltage is also applied to the substrate 3, and as a result, no potential difference is generated above and below the gate oxide film 62, and electrostatic breakdown does not occur. confirmed. The portion that is electrically connected to the substrate 3 is not limited to the element isolation region 63 as in this example, and may be designed according to each element.

The method of establishing electrical connection with the semiconductor substrate in this way has restrictions on circuit design. In addition, eventually the substrate 3
Since it is necessary to cut off the MOS capacitor upper electrode, it is easier to apply to a device that uses a relatively large element, as compared to a VLSI or the like in which elements are densely packed.

Next, a fourth embodiment will be described with reference to FIG. This embodiment is similar to the third embodiment. Figure 4
In the figure, reference numeral 71 indicates a conductive etching mask, and reference numeral 72 indicates an interlayer insulating film, which is a film to be etched here. A hole 74, which is a so-called via, is formed in the film to be etched 72 in order to connect the MOS capacitor 73 and the metal wiring formed in the upper layer.

In order to open this hole 74, it is exposed to a gas atmosphere containing charged particles to proceed with etching. When the MOS capacitor surface 75 is exposed to plasma, there is a risk of electrostatic breakdown of the gate oxide film 62.

However, in this embodiment, the conductive mask 71 is used.
The conductive mask 71 is electrically connected to the substrate 3 at an appropriate position 76 on the semiconductor substrate 3. For this reason,
The substrate 3 and the gate electrode 61 have the same potential, and no voltage is applied to the gate oxide film.

The position 76 where the mask 71 and the substrate 3 are connected may be a dicing line as in the above-described embodiments. In the case of this example, the film to be etched in the dicing line portion needs to be etched in advance, but since there is no need to finely control the dimensions here, wet etching, neutral active gas such as radicals, etc. It is sufficient to perform isotropic etching without damage. In addition, after the etching process, the semiconductor device is manufactured by the same process as the normal process.

Next, a fifth embodiment will be described with reference to FIG. This embodiment is an example for reducing electrostatic breakdown by using an insulating mask. In FIG. 5, the damage that occurs when the MOS capacitor 81 is etched occurs when a voltage of ΔV indicated by reference numeral 85 is applied to the gate oxide film 84 between the MOS upper electrode 82 and the underlying Si substrate 83. To do. When the capacitance of the gate oxide film 84 is C _G and the capacitance of the etching mask 86 is C _R , the voltage of ΔV is V _G and V
_It is divided into _R. At this time, V _G = C _R · V _R / C _G. Therefore, C _R is small, i.e., to use a low dielectric constant mask material, or by decreasing the capacitance C _R by increasing the thickness of the mask material, reducing the stress applied to the gate oxide film 84 You can

It is also conceivable that a voltage may be applied not only from the upper portion of the MOS capacitor but also from the side surface of the pattern, but it has been found that the influence is extremely small compared to the upper surface. Furthermore, by using an insulating mask, damage can be reduced by lowering the tunnel current flowing even with a slight electric field. For example, even when an electric field that causes destruction is not applied to the gate oxide film,
A minute tunnel current due to the tunnel effect flows through the gate oxide film. This current weakens the Si—O bond in the oxide film or the Si—OH bond existing by the impurity hydrogen, and an electron or hole trap is formed there. These traps not only change the device characteristics, but also increase the effective electric field applied to the gate oxide film due to trap formation during processing, which may cause electrostatic breakdown. Even in such a case, the leak current can be reduced and damage can be reduced by using the insulating mask according to the present embodiment.

Next, a sixth embodiment will be described with reference to FIG. This embodiment is a further application of the fifth embodiment. In the actual etching process, as in the case of FIG. 4, when the MOS capacitor is exposed to plasma, there is often no mask above it. For example, as shown in FIG. 6, an insulating film 92 such as a silicon nitride film is once deposited on the entire surface in order to leave the side wall, and the entire surface of the wafer is exposed to the reactive gas plasma without a mask, and finally the film shown in FIG. This is the case where the spacer 91 is left on the side surface of the MOS capacitor upper electrode 61 as in (c).

In such a case, the insulating film 92 is slightly left before the MOS capacitor is directly exposed to the plasma (see FIG. 6).
(B)) Stop the etching once. After that, the remaining film is removed by using an etching method that does not use charged particles, and finally the spacer 91 is replaced with a MOS as shown in FIG. 6C.
It is left only on the side surface of the capacitor upper electrode 61. Specific examples of the etching method that does not use charged particles include a process using an aqueous solution, or a method in which an electrically neutral active gas (for example, fluorine atom or chlorine atom) is sent into a vacuum container for processing (chemical dry process). Etching: CDE). Since these methods do not require charged particles and the wafer surface is not charged, there is no need to worry about electrostatic damage. However, since the processed shape is isotropic, it cannot be generally used for fine processing. However, this is not so problematic because the process which does not require these charged particles is only used for a short time after the most part is already processed in consideration of the directionality. Further, even if there is an etching mask or the like, if the remaining etching is performed after removing the mask, it becomes a substitute for pretreatment in the subsequent steps, and the number of steps hardly increases. The present embodiment is also effective in the case shown in FIG. 4, and etching may be stopped immediately before the electrode 61 in FIG. 4 is exposed.

In the above example, the material to be etched is slightly left before the surface of the MOS upper electrode is exposed. However, another insulating material or a thin film that effectively acts as an insulating film is previously formed on the surface of the MOS capacitor. It may be formed and used as a stopper for etching. In this case, it is preferable to select a material having a thin film etching rate higher than that of the upper insulating film in the thin film removing step. For example, a thin Si nitride film is deposited on the polycrystalline Si electrode, and then an Si oxide film to be an interlayer insulating film is deposited. Si oxide
The film may be etched, stopped once at the surface of the nitride film layer, and then the nitride film layer may be processed by a method like CDE which does not use charged particles. In the etching of the oxide film, there is a condition that a selection ratio can be obtained with respect to the nitride film.
Even when etching with E, it is relatively easy to obtain a selection ratio with respect to the oxide film, so this method is considered to be extremely effective. This removal of the nitride film may be performed in the initial stage of thin film formation for drawing out the wiring from the MOS capacitor which is to be formed later. If peeling is carried out at the same time in the step of cleaning the surface of the MOS upper electrode, this embodiment can be carried out without increasing the number of steps.

Further, this material may be a material that changes into an insulating film by being exposed to the gas used during this etching. For example, if the etching gas contains oxygen, it is easily oxidized, such as aluminum or copper. The metal is effective.

Furthermore, the method described above can be applied not only to the formation of the above-mentioned connection hole but also to the process of processing a gate electrode made of polysilicon or the like. For example, after performing etching with charged particles such as reactive etching using a gas containing fluorine atoms or chlorine atoms, etching without using charged particles (CDE, etc.) is also performed by supplying the above atoms in a radical state. Good.

Next, a seventh embodiment will be described with reference to FIG. FIG. 7 shows an apparatus for performing high-performance etching at high speed by using a magnetic field to increase the density of plasma. The basic configuration of this apparatus is the same as that of the reactive ion etching apparatus shown in FIG. 10, but a magnet 8 is arranged outside the anode electrode to form a magnetic field 9 parallel to the wafer 3 near the surface of the wafer 3. The electric field E10 due to the self-bias voltage Vdc orthogonal to the magnetic field 9 causes electrons to drift in the vector direction of E × B. Then, the electrons are bound until they escape to the wall and collide with each other, and it becomes difficult for the electrons to escape to the outside of the plasma, so that the plasma density increases.

Conventionally, the self-bias voltage Vdc is higher in the peripheral portion of the wafer 3 near the magnetic poles 1101 on both ends of the yoke 1102 of the magnet 8 than in the central portion of the wafer, which causes electrostatic breakdown. Therefore, when the magnetic field vector of the wafer is examined, as shown in FIG. 8, the magnetic flux vector 1103 is oblique in the peripheral portion of the wafer 3. It was found that the vertical magnetic field component indicated by reference numeral 1106 increased Vdc in that portion as indicated by reference numeral 1105. This is because the mobility of electrons increases in the direction along the magnetic field, and the electrons easily fly to the wafer surface in the part where the vertical component of the magnetic field exists, while the ions are almost unaffected by this level of magnetic field and remain constant. It was found that the self-bias voltage increases in the portion where the longitudinal magnetic field exists because of the difference in the supply amount of positive and negative charges.

In this embodiment, when a substrate including a MOS capacitor is processed in a plasma device that causes electron drift in a lateral magnetic field, a longitudinal magnetic field is applied in order to make the self-bias uniform in the wafer surface. I'm losing. The results are shown by broken lines in each graph of FIG. As a result of suppressing the vertical component of the magnetic field as indicated by the broken line, a uniform Vdc distribution is achieved as indicated by reference numeral 1108, and electrostatic damage damage is reduced.

Next, a ninth embodiment will be described with reference to FIG. The phenomenon that the self-bias voltage on the wafer surface is different due to the imbalance of the distribution of positive and negative charges is also observed in the device mainly using the vertical magnetic field as shown in FIG.
This device draws plasma from the discharge part or the plasma generation part 1205 to the etching chamber 1206, and applies RF power from the RF power supply 5 to the substrate via the susceptor to bias the substrate, thereby drawing out ions and advancing the etching. is there. The plasma generator 1205 includes a main coil 1201, an antenna 1202, a matching unit 1203, and the like. A sub coil 1204 is wound around the outside of the etching chamber 1206.

In the apparatus of this system, when the wafer diameter of the material to be etched is larger than that of the discharge part 1205, a magnetic field 1207 diverging between the discharge part 1205 and the etching chamber 1206 (in FIG. 9, the divergent magnetic field is shown in the left half). Is formed and the plasma is drawn out, and at the same time, the plasma is expanded to ensure uniformity. However, when such a divergent magnetic field is used, magnetic field components parallel and perpendicular to the wafer are mixed around the wafer. As a result, a distribution is generated in Vdc on the surface of the wafer. Therefore, it is necessary to make all the directions uniform with respect to the magnetic field crossing the wafer 3.
Also in this case, it is effective to make the magnetic field uniform at least in the vertical direction. Therefore, the diameter of the discharge part itself is made equal to or larger than that of the wafer to make the original plasma itself uniform, and the uniformity of the plasma transported from the discharge part 1205 is improved. Then, the magnetic field component parallel or perpendicular to the wafer is unified to either one on the wafer surface so that both components are not mixed. In the example of FIG. 9, it is also possible to correct the non-uniformity of the self-bias voltage generated by factors other than the magnetic field by appropriately changing the strength of the vertical magnetic field.

The embodiments of the present invention for preventing electrostatic breakdown are mainly described above, mainly by etching. However, the present invention is not limited to this, and the treatment is performed by exposing to charged particles or a gas atmosphere containing charged particles. It may be any step. For example,
Appropriate materials, configurations, etc. for all processes using electrostatically charged particles, such as plasma CVD, ion implantation, annealing by electron beam irradiation, surface modification by plasma irradiation, etc., in which electrostatic breakdown due to substrate charging occurs. It can be applied while changing.

[0050]

As described above, according to the structure of the present invention, deterioration and destruction of the insulator can be prevented, and devices can be formed with a high yield.

[Brief description of drawings]

FIG. 1 is a sectional view showing an object to be processed according to a first embodiment of the present invention.

FIG. 2 is an explanatory circuit diagram illustrating a second embodiment according to the present invention.

FIG. 3 is a cross-sectional view showing an object to be processed before (a) and after (b) the etching step of the third embodiment of the present invention.

FIG. 4 is a sectional view showing an object to be processed according to a fourth embodiment of the present invention.

FIG. 5 is an explanatory view explaining a fifth embodiment according to the present invention.

FIG. 6 is a sectional view showing an object to be processed in each processing step of a sixth embodiment according to the present invention.

FIG. 7 is a sectional view showing a plasma etching apparatus used in a seventh embodiment of the present invention.

FIG. 8 is an explanatory diagram illustrating a seventh embodiment.

FIG. 9 is a sectional view showing a plasma etching apparatus used in an eighth embodiment according to the present invention.

FIG. 10 is a sectional view showing a schematic configuration of a general plasma etching apparatus.

FIG. 11 is an explanatory circuit diagram illustrating a mechanism of electrostatic breakdown.

FIG. 12 is an explanatory circuit diagram illustrating a mechanism of electrostatic breakdown.

FIG. 13 is a diagram for explaining a problem of the conventional technique.

[Explanation of symbols]

 1 Reaction Container 2 Susceptor 3 Wafer 5 High Frequency Power Supply 6 Cooling Pipe 35 Insulator 37 Element Area 38 Element Area 39 MOS Capacitance 61 Insulation Electrode 62 Dielectric Film 65 Hole

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Isao Hasegawa 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device for manufacturing a large number of device chips on a substrate, wherein a region where the large number of device chips are formed is divided into a plurality of regions, and these adjacent regions are electrically separated from each other. A method of manufacturing a semiconductor device, comprising a region dividing step of forming an insulator. 2. A dielectric film formed on a semiconductor substrate is exposed to an object to be processed having a conductor film on a charged particle or a gas atmosphere containing the charged particle to etch a part of the conductor film to form the dielectric film. Before the charging treatment step of exposing the surface of the object to be processed, a conduction treatment step of exposing the semiconductor substrate or a conductor electrically connected to the semiconductor substrate to the surface of the object to be processed is provided. Manufacturing method of semiconductor device. 3. An object to be processed having a conductor pattern on a first dielectric film formed on a semiconductor substrate and a second dielectric film on the conductor pattern is charged particles or a gas atmosphere containing the charged particles. The semiconductor substrate or a conductor electrically connected to the semiconductor substrate before the charging treatment step of exposing a portion of the second dielectric film to the surface of the object to be treated by exposing the conductor pattern to the surface of the object to be treated. A method of manufacturing a semiconductor device, comprising: a conduction treatment step of exposing a substrate to a surface of the object to be treated. 4. An object to be processed having a conductor film on a dielectric film formed on a semiconductor substrate is exposed to charged particles or a gas atmosphere containing the charged particles to etch a part of the conductor film to form the dielectric film. The charging treatment step of exposing the surface of the object to be processed is stopped before the dielectric film is exposed to the surface of the object to be processed,
A method of manufacturing a semiconductor device, further comprising an exposing step of exposing the dielectric film to a surface of an object to be processed without using charged particles. 5. An object to be processed having a conductor pattern on a first dielectric film formed on a semiconductor substrate and a second dielectric film on the conductor pattern is charged particles or a gas atmosphere containing the charged particles. The step of exposing the conductor pattern to the surface of the object to be processed by exposing a part of the second dielectric film to the surface of the object to be processed is stopped before the conductor pattern is exposed to the surface of the object. A method of manufacturing a semiconductor device, comprising: an exposing step of exposing the conductor pattern to a surface of an object to be processed without using charged particles.