JPH06216209A - Inspection of epitaxial wafer - Google Patents

Inspection of epitaxial wafer

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Publication number
JPH06216209A
JPH06216209A JP441393A JP441393A JPH06216209A JP H06216209 A JPH06216209 A JP H06216209A JP 441393 A JP441393 A JP 441393A JP 441393 A JP441393 A JP 441393A JP H06216209 A JPH06216209 A JP H06216209A
Authority
JP
Japan
Prior art keywords
epitaxial wafer
layer
mobility
hemt
ingaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP441393A
Other languages
Japanese (ja)
Inventor
Mitsuro Kawano
充郎 川野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP441393A priority Critical patent/JPH06216209A/en
Publication of JPH06216209A publication Critical patent/JPH06216209A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To provide an inspection method of an epitaxial wafer which enables improvement of yield of a semiconductor element manufacturing by checking a product of a sheet carrier concentration and mobility of a two-dimensional electron. CONSTITUTION:In an inspection process of an epitaxial wafer wherein a hetero junction is formed and a two-dimensional electronic layer is provided on a hetero junction interface, a sheet carrier concentration Ns and mobility mu of the two-dimensional electronic layer of the epitaxial wafer are measured, and a constant (a) of a=NsXmu is obtained by using the sheet carrier concentration and mobility. An epitaxial wafer is inspected by judging whether or not the epitaxial wafer is approved based on the constant (a).

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はヘテロ接合が形成され、
該ヘテロ接合界面に2次元電子層を有するエピタキシャ
ルウエハの検査方法に関する。
The present invention relates to the formation of a heterojunction,
The present invention relates to a method for inspecting an epitaxial wafer having a two-dimensional electron layer at the heterojunction interface.

【0002】[0002]

【従来の技術】近年、AlGaAsとGaAsとの接合
を用いた高電子移動度トランジスタ(High Ele
ctron Mobility Transisto
r;以下、HEMTと略称する)など、バンドギャップ
の相異なる半導体の接合を形成して、高性能な半導体装
置の開発・実用化が盛んに行われている。また、より高
性能な半導体装置を目指し、AlGaAsとInGaA
sとの接合を用いた歪格子型HEMTやInP基板上に
InAlAs/InGaAsを成長させたHEMTの開
発も行われている。
2. Description of the Related Art Recently, a high electron mobility transistor (High Ele) using a junction of AlGaAs and GaAs is used.
ctron Mobility Transist
r; hereinafter abbreviated as HEMT), and the like, and the development and practical application of high-performance semiconductor devices by actively forming junctions of semiconductors having different band gaps. In addition, aiming at higher performance semiconductor devices, AlGaAs and InGaA
A strained-lattice HEMT using a junction with s and a HEMT in which InAlAs / InGaAs is grown on an InP substrate are also being developed.

【0003】図3に、InGaAsをチャネル層としA
lGaAsを電子供給層とする歪格子型HEMTの断面
図を示す。半絶縁性GaAs基板1の上にバッファ層と
してアンドープGaAs層2、チャネル層としてアンド
ープInGaAs層3、アンドープAlGaAsスペー
サ層4、電子供給層である例えばSiをドープしたn型
AlGaAs層5、Siをドープしたn型GaAs層6
を順次、例えば分子線結晶成長法(Molecular
Beam Epitaxy法;以下、MBE法と略称
する)や有機金属気相成長法(Metal Organ
ic Chemical Vapor Deposit
ion法;以下、MOCVD法と略称する)を用いて結
晶成長させる。GaAs層6上の所望の領域には、オー
ミック電極7が設けられ、それらの間にGaAs層6を
エッチングしてn型AlGaAs層5上にゲート電極8
が設けられている。
In FIG. 3, InGaAs is used as a channel layer A
A cross-sectional view of a strained-lattice HEMT using 1 GaAs as an electron supply layer is shown. On the semi-insulating GaAs substrate 1, an undoped GaAs layer 2 as a buffer layer, an undoped InGaAs layer 3 as a channel layer, an undoped AlGaAs spacer layer 4, an n-type AlGaAs layer 5 doped with Si, which is an electron supply layer, and Si are doped. N-type GaAs layer 6
Sequentially, for example, molecular beam crystal growth method (Molecular
Beam Epitaxy method; hereinafter abbreviated as MBE method) and metalorganic vapor phase epitaxy method (Metal Organ)
ic Chemical Vapor Deposit
Ion method; hereinafter referred to as MOCVD method) for crystal growth. Ohmic electrodes 7 are provided in desired regions on the GaAs layer 6, and the GaAs layer 6 is etched between them to form a gate electrode 8 on the n-type AlGaAs layer 5.
Is provided.

【0004】図4に、InP基板上に成長させたInG
aAsをチャネル層としInAlAsを電子供給層とす
るHEMTの断面図を示す。半絶縁性InP基板11の
上にバッファ層としてアンドープInAlAs層12、
チャネル層としてアンドープInGaAs層13、アン
ドープInAlAsスペーサ層14、電子供給層である
例えばSiをドープしたn型InAlAs層15、アン
ドープInAlAsショットキコンタクト層19、Si
をドープしたn型InGaAs層16を順次、やはりM
BE法やMOCVD法を用いて結晶成長させる。InG
aAs層16上の所望の領域には、オーミック電極17
が設けられ、それらの間にInGaAs層16をエッチ
ングしてn型InAlAs層15上にゲート電極18が
設けられている。
FIG. 4 shows InG grown on an InP substrate.
A cross-sectional view of a HEMT in which aAs is a channel layer and InAlAs is an electron supply layer is shown. An undoped InAlAs layer 12 as a buffer layer on the semi-insulating InP substrate 11,
An undoped InGaAs layer 13, an undoped InAlAs spacer layer 14 as a channel layer, an n-type InAlAs layer 15 doped with, for example, Si which is an electron supply layer, an undoped InAlAs Schottky contact layer 19, Si
The n-type InGaAs layer 16 doped with
Crystal growth is performed using the BE method or the MOCVD method. InG
The ohmic electrode 17 is formed in a desired region on the aAs layer 16.
, The InGaAs layer 16 is etched between them, and the gate electrode 18 is provided on the n-type InAlAs layer 15.

【0005】[0005]

【発明が解決しようとする課題】図3、図4に示される
HEMTの特性は各々結晶層の結晶性やAlGaAs/
InGaAs、InGaAs/GaAs、InAlAs
/InGaAs、InAlAs/InP等のヘテロ接合
の界面急峻性に強く影響される。そのために、まず各結
晶毎に適切な結晶成長条件を見出だすことが重要であ
り、その条件にしたがって所望のHEMT特性が得られ
るエピタキシャルウエハであることを確認することが必
要である。
The characteristics of the HEMT shown in FIGS. 3 and 4 are the crystallinity of the crystal layer and AlGaAs /
InGaAs, InGaAs / GaAs, InAlAs
The interface steepness of a heterojunction such as / InGaAs or InAlAs / InP is strongly affected. For that purpose, it is important to first find out suitable crystal growth conditions for each crystal, and it is necessary to confirm that the epitaxial wafer can obtain desired HEMT characteristics according to the conditions.

【0006】HEMTではエピタキシャルウエハの特性
を調べる方法として、チャネル層3、13内に形成され
る2次元電子のシートキャリア濃度と移動度を測定する
方法が知られている。例えば、電子供給層5、15中の
Siのドーピング濃度を高くするとシートキャリア濃度
は増加し、またスペーサ層4、14が厚くなれば移動度
は高くなることが知られている。
As a method for examining the characteristics of the epitaxial wafer in HEMT, a method of measuring the sheet carrier concentration and mobility of two-dimensional electrons formed in the channel layers 3 and 13 is known. For example, it is known that when the doping concentration of Si in the electron supply layers 5 and 15 is increased, the sheet carrier concentration is increased, and when the spacer layers 4 and 14 are thick, the mobility is increased.

【0007】結晶層の結晶性が悪かったり、AlGaA
s/InGaAs、InGaAs/GaAs、InAl
As/InGaAs、InAlAs/InP等のヘテロ
接合の界面に「だれ」があったり、また基板1、11と
結晶層の界面に不純物があるなどすると、2次元電子の
シートキャリア濃度や移動度が低下する。このように、
明らかに結晶品質に問題のあるエピタキシャルウエハを
用いてHEMTを試作したところHEMTの特性、例え
ば伝達コンダクタンス(gm)が低下することが判明し
た。従ってエピタキシャルウエハの結晶性が半導体の特
性歩留りに強く影響し、エピタキシャルウエハの検査は
極めて重要な問題となる。
The crystallinity of the crystal layer is poor, or AlGaA
s / InGaAs, InGaAs / GaAs, InAl
If there is a "drip" at the interface of a heterojunction such as As / InGaAs or InAlAs / InP, or if there is an impurity at the interface between the substrates 1 and 11 and the crystal layer, the sheet carrier concentration and mobility of two-dimensional electrons will decrease. To do. in this way,
When an HEMT was experimentally manufactured using an epitaxial wafer having a problem of crystal quality, it was found that the characteristics of the HEMT, for example, the transfer conductance (gm) were deteriorated. Therefore, the crystallinity of the epitaxial wafer strongly affects the characteristic yield of the semiconductor, and the inspection of the epitaxial wafer becomes a very important problem.

【0008】従来、エピタキシャルウエハの成長後、H
all測定により2次元電子のシートキャリア濃度や移
動度を測定し、エピタキシャルウエハの合否判定を行っ
ていた。シートキャリア濃度や移動度が著しく低下した
ものについては除くことができるが、その他のエピタキ
シャルウエハについては、充分なシートキャリア濃度が
あるのにHEMT特性が良くないなど、素子を製作し、
DCやRF特性を測定するまで特性の良否が分からない
ことが多かった。このため、半導体装置の歩留りは安定
せず、また製造コストの増加につながっていた。
Conventionally, after the growth of the epitaxial wafer, H
The sheet carrier concentration and the mobility of two-dimensional electrons were measured by the all measurement, and the acceptance / rejection of the epitaxial wafer was determined. Although it is possible to exclude those in which the sheet carrier concentration or mobility is remarkably reduced, for other epitaxial wafers, the device is manufactured such that the HEMT characteristics are not good even though the sheet carrier concentration is sufficient.
In many cases, the quality of the characteristics was unknown until the DC or RF characteristics were measured. Therefore, the yield of the semiconductor device is not stable, and the manufacturing cost is increased.

【0009】本発明者は、2次元電子のシートキャリア
濃度や移動度が異なるHEMTを試作しDC及びRF特
性との対応関係を調べた結果シートキャリア濃度Nsと
移動度μとの積Ns×μとHEMT特性との間には強い
相関があることを見出だし、本発明を案出するに至っ
た。
The inventor of the present invention prototyped HEMTs having different two-dimensional electron sheet carrier concentrations and mobilities, and examined the correspondence with DC and RF characteristics. As a result, the product Ns × μ of sheet carrier concentrations Ns and mobilities μ. It was found that there is a strong correlation between the and HEMT characteristics, and the present invention was devised.

【0010】本発明は、ヘテロ接合が形成され、該ヘテ
ロ接合界面に2次元電子層を有するエピタキシャルウエ
ハの検査工程において、2次元電子のシートキャリア濃
度と移動度との積を調べることにより、半導体素子製造
の歩留りを向上させることのできるエピタキシャルウエ
ハの検査方法を提供することを目的とする。
According to the present invention, in a process of inspecting an epitaxial wafer having a heterojunction formed and having a two-dimensional electron layer at the heterojunction interface, the product of the sheet carrier concentration and the mobility of the two-dimensional electron is examined to obtain a semiconductor. An object of the present invention is to provide an epitaxial wafer inspection method capable of improving the yield of device manufacturing.

【0011】[0011]

【課題を解決するための手段】本発明に係るエピタキシ
ャルウエハの検査方法は、ヘテロ接合が形成され、該ヘ
テロ接合界面に2次元電子層を有するエピタキシャルウ
エハの検査工程において、該エピタキシャルウエハの前
記2次元電子層のシートキャリア濃度Nsと移動度μを
測定し、該シートキャリア濃度と該移動度を用いて、a
=Ns×μなる定数aを求め、この定数aにより、前記
エピタキシャルウエハの合否を判定することを特徴とす
る。
According to a method of inspecting an epitaxial wafer according to the present invention, in the step of inspecting an epitaxial wafer in which a heterojunction is formed and a two-dimensional electron layer is formed at the heterojunction interface, The sheet carrier concentration Ns and the mobility μ of the three-dimensional electron layer are measured, and using the sheet carrier concentration and the mobility, a
= Ns × μ is obtained, and the acceptance / rejection of the epitaxial wafer is determined by this constant a.

【0012】また、エピタキシャルウエハがAlGaA
s/InGaAs/GaAs接合よりなる歪格子型HE
MTにおいて、室温の測定により得られる定数aが8.
0×1015-1-1以上を合格と判定することを特徴と
する。
Further, the epitaxial wafer is made of AlGaA.
Strained lattice HE with s / InGaAs / GaAs junction
In MT, the constant a obtained by measuring the room temperature is 8.
It is characterized in that 0 × 10 15 V −1 s −1 or more is judged as a pass.

【0013】さらに、エピタキシャルウエハがInAl
As/InGaAs/InAlAs接合よりなるHEM
Tにおいて、室温の測定により得られる定数aが3.5
×1016-1-1以上を合格と判定することを特徴とす
る。
Further, the epitaxial wafer is InAl
HEM with As / InGaAs / InAlAs junction
At T, the constant a obtained by measuring the room temperature is 3.5.
It is characterized by determining that the result is × 10 16 V -1 s -1 or more.

【0014】[0014]

【作用】本発明にかかる、ヘテロ接合が形成され、該ヘ
テロ接合界面に2次元電子層を有するエピタキシャルウ
エハの検査方法を用いることにより、半導体装置の製造
コストの低減と歩留りの向上を図ることができる。
By using the method for inspecting an epitaxial wafer in which a heterojunction is formed and a two-dimensional electron layer is formed at the heterojunction interface according to the present invention, the manufacturing cost of semiconductor devices can be reduced and the yield can be improved. it can.

【0015】[0015]

【実施例】以下、本発明に係る一実施例につき図面を参
照して説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0016】図1は、図3に断面図を示したInGaA
sチャネル層をもつ歪格子型HEMTについて、エピタ
キシャルウエハの室温における2次元電子のシートキャ
リア濃度Nsと移動度μを測定し、a=Ns×μにおけ
る定数aの値と、HEMTの相互コンダクタンスgmと
の関係を示した図である。この図から明らかなように、
相互コンダクタンスgmとNs×μの値は強い正の相関
を示しており、aが8.0×1015-1-1を下回る
と、gmは〜500mS/mmから300〜400mS
/mmへと急激に低下している。この結果をもとに、a
の値が8.0×1015-1-1以上であったHEMTの
RF特性の歩留りは、本検査を行っていないときの従来
の歩留り45%から90%へと大幅に向上した。
FIG. 1 shows InGaA whose sectional view is shown in FIG.
For the strained-lattice HEMT having an s-channel layer, the sheet carrier concentration Ns of two-dimensional electrons and the mobility μ of the epitaxial wafer at room temperature were measured, and the value of the constant a at a = Ns × μ and the transconductance gm of the HEMT were measured. It is the figure which showed the relationship of. As you can see from this figure,
The transconductance gm and the value of Ns × μ show a strong positive correlation, and when a is below 8.0 × 10 15 V −1 s −1 , gm is ˜500 mS / mm to 300 to 400 mS.
/ Mm sharply decreases. Based on this result, a
The yield of the RF characteristics of the HEMT having the value of ≧ 8.0 × 10 15 V −1 s −1 was significantly improved from the conventional yield of 45% when the inspection was not performed to 90%.

【0017】図2は、図4に断面図を示したInP基板
上に成長させたInGaAsをチャネル層としInAl
Asを電子供給層とするHEMTについて、エピタキシ
ャルウエハの室温における2次元電子のシートキャリア
濃度Nsと移動度μを測定し、a=Ns×μにおける定
数aの値と、HEMTの相互コンダクタンスgmとの関
係を示した図である。図3のInGaAsチャネル層を
もつ歪格子HEMTの場合と同様に、相互コンダクタン
スgmとNs×μの値との間に強い正の相関があること
がわかる。本例では、aの値が3.5×1016-1-1
以上では、〜800mS/mm以上という高いgmが得
られ、aの値が3.5×1016-1-1以上であったH
EMTのRF特性の歩留りは、本検査を行っていないと
きの従来の歩留り35%から95%へと大幅に向上し
た。
FIG. 2 shows InAl used as a channel layer of InGaAs grown on an InP substrate whose sectional view is shown in FIG.
For a HEMT having an electron supply layer of As, the sheet carrier concentration Ns of two-dimensional electrons and the mobility μ of the epitaxial wafer at room temperature were measured, and the value of the constant a at a = Ns × μ and the transconductance gm of the HEMT were measured. It is the figure which showed the relationship. It can be seen that there is a strong positive correlation between the transconductance gm and the value of Ns × μ, as in the case of the strained grating HEMT having the InGaAs channel layer of FIG. In this example, the value of a is 3.5 × 10 16 V −1 s −1
Above, a high gm of ˜800 mS / mm or more was obtained, and the value of a was 3.5 × 10 16 V −1 s −1 or more.
The yield of the RF characteristics of the EMT is significantly improved from the conventional yield of 35% when the inspection is not performed to 95%.

【0018】なお、実施例ではAlGaAs/InGa
As/GaAsのヘテロ接合を有するHEMTやInA
lAs/InGaAs/InAlAsのHEMTの場合
について述べたが、例えばInGaP/GaAsなどヘ
テロ接合により量子井戸層を有するエピタキシャルウエ
ハを用いた半導体装置においても、エピタキシャルウエ
ハの検査方法としてa=Ns×μの値を合否判定基準と
することにより同様の効果が得られる。
In the embodiment, AlGaAs / InGa is used.
HEMT and InA having a heterojunction of As / GaAs
Although the case of HEMT of 1As / InGaAs / InAlAs has been described, a value of a = Ns × μ is used as a method for inspecting an epitaxial wafer even in a semiconductor device using an epitaxial wafer having a quantum well layer by a heterojunction such as InGaP / GaAs. The same effect can be obtained by using as a pass / fail criterion.

【0019】[0019]

【発明の効果】以上述べたように本発明によれば、ヘテ
ロ接合が形成され、該ヘテロ接合の界面に2次元電子層
を有するエピタキシャルウエハの検査工程において、そ
のウエハの2次元電子のシートキャリア濃度と移動度を
測定し、両者の積の値に検査基準値を設ける検査方法を
用いることにより、半導体装置の製造コストの低減と歩
留りの向上を図ることができる。
As described above, according to the present invention, in the inspection process of an epitaxial wafer having a heterojunction and having a two-dimensional electron layer at the interface of the heterojunction, a sheet carrier of the two-dimensional electron of the wafer is inspected. By using the inspection method in which the concentration and the mobility are measured and the inspection reference value is set to the value of the product of both, the manufacturing cost of the semiconductor device can be reduced and the yield can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明にかかる第一のHEMTの定数aとg
mとの相関を示す線図。
FIG. 1 is a first HEMT constant a and g according to the present invention.
The diagram which shows the correlation with m.

【図2】 本発明にかかる第二のHEMTの定数aとg
mとの相関を示す線図。
FIG. 2 is a second HEMT constant a and g according to the present invention.
The diagram which shows the correlation with m.

【図3】 InGaAsチャネル層をもつ歪格子型HE
MTの断面図。
FIG. 3 is a strained lattice HE having an InGaAs channel layer.
Sectional drawing of MT.

【図4】 InP基板に成長させたInGaAsをチャ
ネル層としInAlAsを電子供給層とするHEMTの
断面図。
FIG. 4 is a cross-sectional view of a HEMT in which InGaAs grown on an InP substrate is used as a channel layer and InAlAs is used as an electron supply layer.

【符号の説明】[Explanation of symbols]

1…半絶縁性GaAs基板 2…アンドープGaAs層 3…InGaAsチャネル層 4…アンドープAlGaAsスペーサ層 5…SiドープAlGaAs層 6…SiドープGaAs層 7…オーミック電極 8…ゲート電極 11…半絶縁性InP基板 12…アンドープInAlAs層 13…InGaAsチャネル層 14…アンドープInAlAsスペーサ層 15…SiドープInAlAs層 16…SiドープInGaAs層 17…オーミック電極 18…ゲート電極 19…アンドープInAlAsショットキコンタクト層 DESCRIPTION OF SYMBOLS 1 ... Semi-insulating GaAs substrate 2 ... Undoped GaAs layer 3 ... InGaAs channel layer 4 ... Undoped AlGaAs spacer layer 5 ... Si-doped AlGaAs layer 6 ... Si-doped GaAs layer 7 ... Ohmic electrode 8 ... Gate electrode 11 ... Semi-insulating InP substrate 12 ... Undoped InAlAs layer 13 ... InGaAs channel layer 14 ... Undoped InAlAs spacer layer 15 ... Si-doped InAlAs layer 16 ... Si-doped InGaAs layer 17 ... Ohmic electrode 18 ... Gate electrode 19 ... Undoped InAlAs Schottky contact layer

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 ヘテロ接合が形成され、該ヘテロ接合界
面に2次元電子層を有するエピタキシャルウエハの検査
工程において、該エピタキシャルウエハの前記2次元電
子層のシートキャリア濃度Nsと移動度μを測定し、該
シートキャリア濃度と該移動度を用いて、a=Ns×μ
なる定数aを求め、この定数aにより、前記エピタキシ
ャルウエハの合否を判定することを特徴とするエピタキ
シャルウエハの検査方法。
1. A sheet carrier concentration Ns and a mobility μ of the two-dimensional electron layer of the epitaxial wafer are measured in a step of inspecting an epitaxial wafer having a two-dimensional electron layer formed at a heterojunction interface. , A = Ns × μ using the sheet carrier concentration and the mobility
The method for inspecting an epitaxial wafer is characterized in that the pass / fail of the epitaxial wafer is determined based on the constant a.
【請求項2】 エピタキシャルウエハがAlGaAs/
InGaAs/GaAs接合よりなる歪格子型HEMT
において、室温の測定により得られる定数aが8.0×
1015-1-1以上を合格と判定することを特徴とする
請求項1記載のエピタキシャルウエハの検査方法。
2. The epitaxial wafer is AlGaAs /
Strained lattice HEMT with InGaAs / GaAs junction
In, the constant a obtained by measuring the room temperature is 8.0 ×
The method for inspecting an epitaxial wafer according to claim 1, wherein a value of 10 15 V -1 s -1 or more is determined to be acceptable.
【請求項3】 エピタキシャルウエハがInAlAs/
InGaAs/InAlAs接合よりなるHEMTにお
いて、室温の測定により得られる定数aが3.5×10
16-1-1以上を合格と判定することを特徴とする請求
項1記載のエピタキシャルウエハの検査方法。
3. The epitaxial wafer is InAlAs /
In a HEMT including an InGaAs / InAlAs junction, the constant a obtained at room temperature is 3.5 × 10 5.
The method for inspecting an epitaxial wafer according to claim 1, wherein a value of 16 V -1 s -1 or more is determined to be acceptable.
JP441393A 1993-01-14 1993-01-14 Inspection of epitaxial wafer Pending JPH06216209A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
JP441393A JPH06216209A (en) 1993-01-14 1993-01-14 Inspection of epitaxial wafer

Publications (1)

Publication Number Publication Date
JPH06216209A true JPH06216209A (en) 1994-08-05

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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6051506A (en) * 1996-06-29 2000-04-18 Hyundai Electronics Industries Co., Ltd. Method of fabrication ultra-frequency semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6051506A (en) * 1996-06-29 2000-04-18 Hyundai Electronics Industries Co., Ltd. Method of fabrication ultra-frequency semiconductor device

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