JPH06215135A - Picture processor - Google Patents

Abstract

PURPOSE:To operate the area measurement of a picture by a picture processing at a high speed in a simple constitution. CONSTITUTION:The logical product of a video signal binarized into a picture element group corresponding to the picture to be measured and the picture element group corresponding to the picture not to be measured, a reproduction enable signal E which indicates the valid section of the video signal, and a clock signal C is operated by a logical product circuit 1. In this case, an incrimenter 2 counts the clock signal C outputted from the logical product circuit 1 only in the picture area to be measured. Then, the result counted within one vertical scanning period is fetched into a latch circuit 3, and the area of the picture to be measured is computed based on both the fetched counted result and a reproduction standard.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more specifically, it is possible to measure the length and area of an image easily and at high speed by using a composite video signal composed of a video signal and a reproduction timing signal. The present invention relates to an image processing device.

[0002]

2. Description of the Related Art Conventionally, as image processing, there is one which aims to measure the area and length of an image. The measurement of the area and length of the image has been performed by software processing by a CPU in the past. For example, a certain threshold value is compared with the signal level of each pixel read from the image memory, and the image is brighter than the threshold value. It is known that the area and length are measured by counting the number of pixels determined to be (or dark) on an image memory.

Further, in a CAD or the like in which a straight line or a fixed curve is combined to create a figure, the area of a drawn image is
There are some that are calculated by a calculation formula according to the line used.

[0004]

However, in the area measurement by the software processing by the CPU as described above, the processing load of the CPU is large and a long processing time is required. Therefore, it is necessary to successively measure the area of the image that changes sequentially. However, there is a problem that the area using the calculation formula cannot be applied to an image to which the calculation formula cannot be applied, for example, the area of an image drawn by freehand cannot be measured.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an image processing apparatus capable of measuring the area and length of an image at high speed without selecting the shape of the image.

[0006]

Therefore, an image processing apparatus according to the present invention has at least a binarized video signal in a pixel group corresponding to an image to be measured and a pixel group corresponding to an image to be non-measured. An image processing apparatus for measuring a length or an area of an image of the measurement target by using a composite video signal including a reproduction timing signal for the video signal including a clock signal, the reproduction timing signal and the Two
A logical operation circuit for performing a logical operation with the video signal of the value to output a clock signal in the image area of the measurement target; and a counter for counting the clock signal output from the logical operation circuit. The length or area of the image of the measurement target is measured based on the count value of the counter.

Here, a latch circuit for fetching the count value of the counter for each vertical scanning period based on the vertical synchronizing signal included in the reproduction timing signal is provided, and the latch circuit for fetching the count value by the latch circuit is used. The area of the image to be measured is 1
The measurement may be performed for each vertical scanning period. Further, the logical operation circuit performs a logical product operation of a clock signal included in the reproduction timing signal, a reproduction enable signal indicating an effective section within a scanning period, and the binary video signal to obtain the measurement target. It is preferable that the clock signal is output in the image area.

[0008]

According to the image processing apparatus having such a configuration, since the binarized video signal is used for the pixel group corresponding to the image of the measurement target and the pixel group corresponding to the image of the non-measurement target, it is based on the video signal level. It is possible to determine whether or not the pixel is a pixel corresponding to the measurement target image, and the area or length can be measured by counting the number of pixels in the target region.

Here, in the present invention, a logical operation circuit is caused to perform a logical operation between the binarized video signal and a reproduction timing signal for the video signal, and the logical operation circuit is operated in the target area. The number of pixels in the target region is counted by outputting a clock signal and counting the clock signal. Therefore, the area (or length) within one vertical scanning period
The number of pixels, which is an equivalent value, is obtained, and even if the shape of the image region to be measured is complicated, the area and length can be measured without any influence.

[0010]

EXAMPLES Examples of the present invention will be described below. An example of an image to be measured in this embodiment is shown in FIG. Figure 3
The image shown in (a) is a line image showing a house with a chimney protruding from the roof, and a video signal for reproducing the image,
A state in which the image is displayed on a display device such as a CRT based on a composite video signal including a reproduction timing signal for assembling the image is shown.

As shown in FIG. 2, the reproduction timing signal includes a vertical synchronizing signal V, a horizontal synchronizing signal H, a reproduction enable signal E indicating a valid section in the scanning period, and a clock signal C. Here, it is assumed that the area of the roof portion including the chimney of the image of the house shown in FIG. 3A is measured.

First, as preprocessing, a roof portion including a chimney, which is an image region (measurement target image) in which the area of the video signal of the house shown in FIG. 3A is measured, and other region portions are measured. The image is decomposed (see FIG. 3B), and binarization processing is performed to assign different values to the pixels included in the measurement region and the pixels included in the non-measurement region. Non-measurement area (non-measurement area pixel group)
The binarized video signal is set for area measurement.

The measurement area may be specified by allowing an operator to operate the man-machine interface while visually observing the display screen, and according to the specification of the measurement area, for example, pixels included in the measurement area can be specified. Is assigned a signal value of “1”, and pixels included in other non-measurement areas are assigned a signal value of “0”.

FIG. 3B shows an example in which the binarized video signal is displayed. In this example, the measurement area (the roof portion including the chimney) is filled. Is displayed. Next, the area measurement using the video signal binarized as described above will be described in detail.

First, in the reproduction timing signal shown in FIG. 2, during the period in which an image is actually reproduced, the clock signal is output as the calculation result when the logical product of the reproduction enable signal E and the clock signal C is calculated. When the clock signal output by the AND operation is counted in one cycle of the normal vertical synchronizing signal V, the counted value becomes a value corresponding to the screen size actually reproduced.

Further, as described above, when performing binarization for dividing the measurement target region and the non-measurement target region, "1" is assigned to the pixel of the measurement region and the pixel of the non-measurement region is assigned. "0" is assigned to this, and this binarized video signal
The configuration is such that the logical product of three signals of Video and the above-described reproduction enable signal E and clock signal C is calculated.

Then, the clock signal is output from the AND circuit only in the measurement region while reproducing the video signal at the normal image reproduction timing. Therefore, the value obtained by counting the clock signal from the AND circuit in one vertical scanning period becomes a value indicating the number of pixels included in the measurement region, and the area of the counting target region is obtained based on the count value and the scale. You can

As described above, FIG. 1 shows a concrete example for measuring the area of the image region to be measured based on the logical product operation of the binarized video signal Video, the clock signal C and the reproduction enable signal E. 2 shows a typical circuit configuration.
In FIG. 1, the AND circuit 1 includes a binarized video signal Video, a clock signal C, and a reproduction enable signal E.
And are input respectively. The output of the AND circuit (logical operation circuit) 1 is an incrementer (counter) 2
And the number of output pulses from the AND operation circuit 1 is counted by the incrementer 2.

A latch circuit 3 for latching the counting result of the incrementer 2 is provided, and the data latched by the latch circuit 3 is transferred to the C bus via the CPU bus 4.
It is designed to be sent to PU5. The incrementer 2 is cleared in synchronization with the falling edge of the vertical synchronizing signal V, and the latch circuit 3 takes in the counting result of the incrementer 2 in synchronization with the rising edge of the vertical synchronizing signal V. Therefore, when the vertical scanning is completed, first, the result counted by the incrementer 2 in the one vertical scanning cycle is taken into the latch circuit 3, and thereafter, the counting is newly performed in the next one vertical scanning cycle. Incrementer 2 is cleared in order to make it.

According to the configuration shown in FIG. 1, from the AND circuit 1, the measurement target area in the effective image area (see FIG.
The clock signal C is output only in the (b) roof portion (see FIG. 2), and the clock signal C output from the AND circuit 1 is counted by the incrementer 2.
The count result of the incrementer 2 during one vertical scanning cycle corresponds to the number of pixels included in the image area of the measurement target to which “1” is assigned in the binarized video signal.

Therefore, the CPU 5 is based on the number of clock signals counted in one vertical scanning cycle and taken in by the latch circuit 3 and the scale of image reproduction, and is shown in FIG.
The area of the counting target area shown in is calculated. CPU 5
In the above, since the process of actually calculating the area from the counting result of the clock signal C can be realized by simple software, it is possible to sufficiently finish the calculation at least by the end of the next vertical scanning cycle. hand,
The area can be measured for each normal vertical scanning cycle, and the calculation load on the CPU 5 is small. If the area can be measured for each normal vertical scanning cycle as described above, the area of an image that sequentially changes can also be sequentially measured.

Further, since the number of pixels contained in the image area of the measurement object is counted, even if the image of the measurement object is complicated, the area can be measured in exactly the same manner as in the case of an image of a simple shape. You can Although the area measurement has been described above, the clock signal C output from the AND circuit 1
The line length or the maximum width in the horizontal direction of the measurement target region can be obtained in the same manner by making a change such that the counting result of (1) is taken in every horizontal scanning.

Further, by changing the image reproduction magnification, the area measurement cycle can be changed without changing the area measurement cycle.
It is also possible to change the length measurement accuracy. Further, even when there are a plurality of image regions to be measured in the same image, if these plural regions are arranged at intervals in the vertical direction, each area is scanned by one vertical scan. It can also be measured within the period.

In the structure shown in FIG. 1, the logical operation circuit for inputting the three signals of the binarized video signal Video, the clock signal C and the reproduction enable signal E is used. Using two AND circuits as signals, for example, the reproduction enable signal E and the binarized video signal Vide
The logical product with o is calculated by the first logical product circuit
The output of the AND circuit and the clock signal C may be input to the second AND circuit.

[0025]

As described above, according to the present invention, the area / length of a predetermined image to be measured is a complex-shaped image by using a composite video signal including a video signal and a reproduction timing signal. However, there is an effect that the measurement can be performed at high speed with a simple configuration.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a time chart showing signal characteristics in the example.

FIG. 3 is a diagram showing an example of an image targeted by the embodiment.

[Explanation of symbols]

 1 AND circuit (logical operation circuit) 2 Incrementer (counter) 3 Latch circuit 4 CPU bus 5 CPU

Claims (3)

[Claims] 1. A reproduction timing signal for the video signal, comprising a binarized video signal into a pixel group corresponding to an image to be measured and a pixel group corresponding to an image to be non-measured, and at least a clock signal. An image processing device for measuring a length or an area of an image to be measured by using a composite video signal consisting of: and performing the logical operation of the reproduction timing signal and the binary video signal to perform the measurement. The measurement target is configured to include a logical operation circuit that outputs a clock signal in the image area of the target and a counter that counts the clock signal output from the logical operation circuit, and the measurement target based on the count value by the counter. An image processing apparatus, characterized in that the length or area of the image is measured. 2. A latch circuit for fetching the count value of the counter every vertical scanning period based on a vertical synchronizing signal included in the reproduction timing signal, and based on the count value fetched by the latch circuit. The image processing apparatus according to claim 1, wherein the area of the image to be measured is measured every one vertical scanning period. 3. The logical operation circuit performs a logical product operation of a clock signal included in the reproduction timing signal, a reproduction enable signal indicating a valid section within a scanning period, and the binary video signal, The image processing apparatus according to claim 1, wherein a clock signal is output in the image area of the measurement target.