JPH06215019A - Arithmetic unit and parallel arithmetic unit system - Google Patents

Abstract

PURPOSE:To avoid the collision of data outputted from respective parts on a data bus or the delay of processing and to accelerate the repeated processing of the arithmetic of the sum of products by improving efficiency for using the respective parts. CONSTITUTION:A latch 12a is arranged before a multiplier 12b. The multiplier 12b supplies the product of an output from the latch 12a and data from an input terminal 13 to a multiplexer 12c. The multiplier 12b supplies the product through the multiplexer 12c and a latch 12d to a serially arranged an arithmetic and logic circuit 12e. The arithmetic and logic circuit 12e calculates the sum of products and outputs the result from an output terminal 14. The latch 12a, multiplexer 12c and arithmetic and logic circuit 12e are respectively controlled by control signals from input terminals 16, 17 and 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit for performing product-sum operation at high speed based on supplied data and a parallel arithmetic system formed by connecting a plurality of arithmetic units in parallel.

[0002]

2. Description of the Related Art Generally, an arithmetic unit for performing a sum-of-products operation is roughly composed of, for example, a memory 60, a multiplier 61 and an arithmetic logic circuit (hereinafter referred to as ALU) 62 shown in FIG.
Each of the above-mentioned units is connected to the data bus DB, and inputs / outputs data via this data bus DB. In particular, the digital signal processor (DSP) circuit having the above-described circuit configuration repeatedly performs the above-described product-sum operation on input data supplied via the data bus DB, and performs, for example, filter processing.

[0003]

By the way, FIG. 4 is actually used.
When calculating the linear function calculation formula y = ax + b for obtaining the output y when the variable x is input using the arithmetic unit shown in FIG. To the data bus DB. After that, the memory 60 uses the variable x as the multiplicand and the multiplier 6
1 through the data bus DB. The memory 60 is
The coefficient b is supplied to the ALU 62 via the data bus DB. The multiplier 61 supplies the product ax, which is the result of multiplication of the coefficient a and the variable x, to the ALU 62 via the data bus DB. The ALU 62 arithmetically adds the supplied product ax and the coefficient b to generate an operation result ax + b, and outputs the data bus D
It is input to the variable y of the memory 60 via B.

However, when the input data is filtered at high speed, the arithmetic unit must perform the repetitive arithmetic operation as described above. When the arithmetic device performs arithmetic processing,
Since data input / output is performed via the data bus DB, data output from each unit collides on the data bus DB, so-called bus lock occurs, or other processing such as data transfer is delayed until the operation ends. May occur.

When such a bus lock or the like occurs, the arithmetic unit cannot efficiently use each unit, and the arithmetic cannot be processed at high speed.

Therefore, the present invention has been made in view of the above situation, and avoids the collision of data output from each unit on the data bus and the delay in processing, thereby improving the use efficiency of each unit. It is an object of the present invention to provide an arithmetic unit and a parallel arithmetic unit capable of speeding up the iterative processing of, for example, product-sum calculation.

[0007]

An arithmetic unit according to the present invention is a arithmetic unit that repeatedly performs sum-of-products calculation based on supplied data, and a data holding unit that temporarily holds data supplied from the outside. The output from the data holding means is used as a multiplication coefficient, and the multiplication means for multiplying this multiplication coefficient and the multiplicand supplied from the outside, and the data supplied from the outside are stored in the register to perform the arithmetic operation and the logical operation. The above problem is solved by having arithmetic logic means and connecting the multiplication means and the arithmetic logic means in series.

Here, the arithmetic unit is provided with a multiplexer for switching the input data supplied to the arithmetic logic means. In this arithmetic unit, the address of the local memory provided outside the arithmetic unit is calculated by the address calculating unit, and the local memory reads out the data according to the address supplied from the address calculating unit and sends it to the inside of the processor. There is.

The coefficient holding means and the arithmetic adder operate according to a control signal supplied from, for example, a microprogram memory.

A parallel computing device system according to the present invention is a parallel computing system in which a plurality of computing devices are connected in parallel, and data holding means for temporarily holding data supplied from the outside to each computing device, and the data holding means. An output from the means is used as a multiplication coefficient, multiplication means for multiplying this multiplication coefficient by a multiplicand supplied from the outside, and arithmetic logic for performing arithmetic operation and logical operation by storing data supplied from the outside in a register The above-mentioned problem is solved by using an arithmetic unit having a means and having a configuration in which the multiplication means and the arithmetic logic means are connected in series.

[0011]

In the arithmetic unit according to the present invention, the coefficient holding means and the arithmetic adder are connected in series, each of which is operated by a control signal according to a program, the data is read and sent to the inside of the processor, and the data is transferred. It becomes possible to avoid collisions in inputting and outputting.

In the parallel arithmetic device system according to the present invention, a plurality of arithmetic devices having the above-mentioned configuration are connected in parallel to avoid a collision in inputting / outputting data.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the arithmetic unit according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a processor that operates according to a microprogram used for efficiently performing code conversion, data input, and the like. The processor includes a program controller (PC) 10, a micro program memory (MPM) 11 and a calculation unit 12.

The program controller 10 generates an address according to the control in the micro program memory 11 and supplies it to the micro program memory 11. The micro program memory 11 stores a micro program. The contents of this microprogram are instructions for controlling the program controller 10 and the arithmetic unit 12, and numerical data NUM given to the arithmetic unit 12. The micro program memory 11 supplies a micro program command for controlling the arithmetic unit 12 and numerical data NUM to the arithmetic unit 12.

The arithmetic unit 12 has an input terminal 13 from the outside.
Data has been entered via. The calculation unit 12 performs, for example, a sum of products calculation on this data and outputs the calculation result from the output terminal 14.

In this processor, the arithmetic unit of the present invention is applied to the arithmetic unit 12. FIG. 2 shows a schematic configuration of the arithmetic unit. Here, common parts are given the same reference numerals. The arithmetic unit is mainly composed of a latch 12a as data holding means, a multiplier 12b as multiplication means, and an arithmetic logic circuit 12c as arithmetic logic means.

The latch 12a is used as a data holding means for temporarily holding numerical data NUM as data supplied from the outside through the input terminal 15.

The multiplier 12b receives the output from the latch 12a as a multiplication coefficient. Further, the multiplier 12b inputs the data supplied from the outside through the input terminal 13 as the multiplicand. The multiplier 12b usually does not have a data holding function. The multiplier 12b inputs two pieces of data of a multiplication coefficient NUM and a multiplicand as multiplication means for multiplication, and outputs one product which is a multiplication result. The multiplier 12b sends the output to the multiplexer 12c.

Numerical data NUM supplied from the input terminal 15 is input to the multiplexer 12c. The multiplexer 12c selects either one of the two inputs according to the control signal and supplies it to the arithmetic logic circuit 12e via the latch 12d. Arithmetic logic circuit 12
The e stores data supplied from the outside in a register to perform arithmetic operation and logical operation. Arithmetic logic circuit 12
The e outputs from the output terminal 14 the result calculated according to the control signal supplied from the input terminal 18.

Next, the operation control of this arithmetic unit will be described with reference to FIG. First, the coefficient b is supplied as numerical data NUM to the latch 12a and the multiplexer 12c via the input terminal 15. The latch 12a is
Since the data holding signal supplied from the input terminal 16 is not in the enabled state, this numerical data NUM is not held. Further, the multiplexer 12c selects the supplied input end on the coefficient b side among the two inputs by the control signal supplied via the input terminal 17.

Next, the numerical data N is input through the input terminal 15.
As UM, coefficient a is latch 12a and multiplexer 12
is supplied to c. The data holding signal is enabled in the latch 12a, and the coefficient a is fetched as data. At this time, the multiplexer 12c supplies the numerical value data NUM = b to the arithmetic logic circuit 12e via the latch 12d. The arithmetic logic circuit 12e has an input terminal 1
Numerical data NU by the control signal supplied via 8
Store M = b in the built-in RAM.

The multiplier 12b takes in the data x1 via the input terminal 13. The multiplier 12b multiplies the coefficient a previously fetched by the data x1 and outputs the result to the multiplexer 12c. The multiplexer 12c selects the multiplier 12b side by the control signal supplied from the input terminal 17 and the arithmetic logic circuit 12e via the latch 12d.
To the product a × x1.

The arithmetic logic circuit 12e takes in the product a × x1 by the control signal supplied through the input terminal 18.
The arithmetic logic circuit 12e performs a product-sum operation by adding the product a × x1 and the coefficient b stored in the RAM. The result of the product-sum operation is output via the output terminal 14. Further, the multiplier 12b takes in the next data x2 into the multiplier 12b via the input terminal 13. The multiplexer 12b selects the multiplication result by the control signal as described above, and latches the signal 12d.
Is supplied to the arithmetic logic circuit 12e via. The arithmetic logic circuit 12e calculates the sum of the product a × x2 and the coefficient b, and outputs the calculation result from the output terminal 14.

As described above, the arithmetic unit avoids data collision by making the circuit configuration and operation for performing the product-sum operation unidirectional so as not to exchange data via the data bus.
In addition, the inputs of the coefficients a and b necessary for the product-sum calculation are also input to the latch 12
By providing a and utilizing the selection of the multiplexer 12c, data collision can be avoided.

In this multiply-accumulate operation, the arithmetic unit fixes the coefficients a and b supplied from the outside without changing during the arithmetic operation, so that the multiplier 12b and the arithmetic logic circuit 12e are supplied with them. It is sufficient to supply the coefficients a and b only once. Therefore, the product-sum calculation once stored in each RAM is carried out every time it is sequentially supplied through the input terminal 13.
The data x is multiplied and summed (a × x + b) by the multiplier 12b and the arithmetic logic circuit 12e, respectively, and output. The arithmetic unit that performs the sum-of-products calculation in this way performs pipeline processing after storing the coefficients a and b.

Further, a more specific preferred embodiment will be described with reference to FIG. FIG. 3 is a calculation processing block diagram for performing image processing by high-speed calculation by applying the calculation device of the present invention. Around the arithmetic processing block 20, a video input bus (VIBus) for flowing one line of video data supplied from a frame memory (not shown), a video output bus (VOBus), and a work memory input bus for writing one-line data to the work memory. (WIBus), 1
A work memory output bus (WOBus) for reading line data to the work memory is provided. The data extracted from these buses is input to and output from the arithmetic processing block 20 via the latches 21 to 24, respectively. Further, a video temporary memory (VTM) 25 and a write temporary memory (WTM) 26 are provided as memories for temporarily storing data. Video temporary memory (VTM) 25 and write temporary memory (WTM) 2
Reference numeral 6 is a local memory provided outside the arithmetic unit.

In the arithmetic processing block 20, for example, one line of image data x passes through the buffer 27 via the input / output interface 26a and then the multiplexers 28, 29, 3 are provided.
0 respectively. The multiplexer 28 selects any one of the numerical data NUM and the image data x and outputs it to the register R1. The register R1 supplies this data to the coefficient arithmetic logic circuit (CALU) 31.

The coefficient arithmetic logic circuit 31 calculates the address of the coefficient memory 34, which is a local memory provided outside the arithmetic unit for storing the multiplication coefficient, for example, as the address calculating means. The coefficient arithmetic logic circuit 31 includes a register R
2, supplied to the coefficient memory 34 via the buffer 32 and the output interface 33. This local memory is a coefficient memory 34. The coefficient memory 34 stores multiplication coefficients, for example, coefficient data (Data) of a data table based on a function such as a sine function. The coefficient memory 34 receives the coefficient data from the multiplexer 2 via the input interface 35 and the buffer 36.
Supply to 9 and 30.

The multiplexers 29 and 30 receive the coefficient address, the numerical value data NUM, the image data x, the coefficient data and the data from each section, and output the data selected according to the program to the latches 37 and 38, respectively. In addition, the multiplexer 30 includes a multiplexer 41
Is supplying the selected data to.

The multiplexer 29 selects, for example, the image data x, and the multiplexer 30 selects the coefficient data (Data) output from the coefficient memory 34 according to the program and outputs it to the latches 37 and 38, respectively. Each of these latches 37 and 38 can handle, for example, 16-bit data. The latches 37 and 38 supply the data selected by the multiplexers 29 and 30 to the multiplier 39.

Here, in the multiplexer 30, the coefficient data of the coefficient b is output from the coefficient memory 34 in accordance with the program, and when the multiplexer 41 switches and selects this data, the arithmetic logic circuit (XALU) is selected via the register R3. ) 43 is supplied with the coefficient b. The arithmetic logic circuit 43 has a built-in register capable of storing data. The arithmetic logic circuit 43 stores the supplied coefficient b in the register.

Next, the multiplexer 30 selects the coefficient a output from the coefficient memory 34 and supplies it to the latch 38. In general, multipliers do not have registers, as mentioned above. The latch continues to hold the supplied coefficient data until the data is changed. The multiplier 39 is
The product of the results of multiplying the coefficient a and the image data x is output. Multiplier 39 has upper 16 bits (MSP) and lower 1
It is configured by being divided into 6 bits (LSP). Multiplier 3
9 is a rounding operation unit (R
ND) 40. The multiplier 39 supplies the lower 16-bit data to the multiplexer 41. The rounding operation unit 40 also supplies the rounding operation result for the upper 16 bits to the multiplexer 41.

The multiplexer 41 selects one of the numerical data NUM, the rounding operation result and the output from the multiplexer 30 according to the program and outputs it to the register R3. The register R3 returns the data to the multiplexers 29 and 30, and outputs the data to the arithmetic logic circuit (XALU) 43. The arithmetic logic circuit 43 incorporates the register as described above, and stores the coefficient b. The arithmetic logic circuit 43 adds the output from the register R3 and the coefficient b and outputs the result to the register R4. When the arithmetic logic circuit 43 performs the product-sum operation, the arithmetic logic circuit 43 calculates the product a × x of the multiplication results.
And the coefficient b are added to obtain the product-sum operation result y.

The register R4 supplies the output data to the multiplexer 47 and also performs clipping (CLIP).
Supply to the section 44. The clipping unit 44, when the supplied data overflows or underflows,
The supplied maximum value or minimum value is replaced with the supplied data and output. The clipping unit 44 supplies the output data to the multiplexer 47, and at the same time, the absolute value calculation unit 4
Supply to 5. The absolute value calculation unit 45 performs absolute value calculation on the supplied data and outputs it to the multiplexer 47.

The multiplexer 47 includes a stack memory (STACK) 46, a register R4, and a clipping unit 4.
4 and one of the output data from the absolute value calculator 45 is selected and supplied to the multiplexers 29, 30 and 48, and also output to the register R5. The register R5 outputs, for example, the product-sum operation result y via the buffer 49 and the input / output interface 26a. Also, register R5
Outputs the result y of the product sum operation via the buffer 50 and the input / output interface 51.

The multiplexer 48 outputs the output data selected via the register R6 to the arithmetic logic circuit (TALU) 5
Supply to 2. The arithmetic logic circuit 52 is used as an address calculating means for calculating an address of a local memory provided outside the arithmetic unit, and performs an arithmetic operation for addressing. The arithmetic logic circuit 52 supplies the output interface 53 and the stack 46 via the register R7. The address data output from the arithmetic logic circuit 52 consists of 17 words. The address data is supplied to the video temporary memory (VTM) 25 and the write temporary memory (WTM) 26 as address data. Once this coefficient is held in the latch and arithmetic logic circuit, it is fixed until the coefficient data is changed.
Can be sequentially supplied to pipeline the product-sum operation.

With this configuration, the multiplier 3
The latches 37 and 38 provided in front of 9 hold the coefficient data, and the product calculated by the multiplier 39 is supplied to the arithmetic logic circuit 43 arranged in series to perform the sum operation, whereby the data flow is in one direction. I have to. Therefore, the arithmetic processing block 20 can speed up repetitive arithmetic operations by preventing data supply, bus lock, and the like, for example, until the arithmetic operations are completed.

Further, by configuring in this way and controlling the operation, it is easy to manage the program.

Further, a parallel computer which is a parallel computing device system is a parallel computing system in which a plurality of computing devices are connected in parallel. The calculation is being performed. By applying this arithmetic unit to a parallel computer in which a plurality of processors are arranged in parallel as described above, it is possible to efficiently and speed up the arithmetic operation.

[0041]

According to the arithmetic unit of the present invention, in an arithmetic unit which repeatedly performs sum-of-products calculation based on supplied data, data holding means for temporarily holding data supplied from the outside, and the data holding unit. An output from the means is used as a multiplication coefficient, multiplication means for multiplying this multiplication coefficient by a multiplicand supplied from the outside, and arithmetic logic for performing arithmetic operation and logical operation by storing data supplied from the outside in a register By connecting the multiplication means and the arithmetic logic means in series, it is possible to prevent a failure such as a bus lock due to a data collision when exchanging data, so that the operation is safe. Can be speeded up.

The arithmetic unit has an address calculating unit for calculating an address of a local memory provided outside the arithmetic unit, and the multiplying unit is based on the data read according to the address from the address calculating unit. By performing the calculation, it is possible to quickly supply the data required for the calculation processing, which can contribute to the speedup.

Further, by using the above-mentioned arithmetic units connected in parallel to a parallel arithmetic system which is formed by connecting a plurality of arithmetic units in parallel, it is possible to avoid a collision in inputting / outputting data and to make high-speed arithmetic more efficient. Well, the calculation can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing a configuration of a processor that operates according to a microprogram used for efficiently performing code conversion, data input, and the like.

FIG. 2 is a schematic block diagram showing this configuration, which is an embodiment when the arithmetic unit according to the present invention is applied to the arithmetic unit of the processor shown in FIG.

FIG. 3 is a calculation processing block diagram for performing image processing by high-speed calculation by applying the calculation device of the present invention as a more specific and more preferable embodiment.

FIG. 4 is a block diagram showing a schematic configuration of a conventional arithmetic device.

[Explanation of symbols]

 10 ... Program controller 11 ... Program memory 12 ... Calculation unit 13, 15-18 ... Input terminal 14 ... Output terminal 12a, 12d ... Latch 12b ... Multiplier 12c ... Multiplexer 12e, 52 ... Arithmetic logic circuit 31 ... Coefficient arithmetic logic circuit

Claims (3)

[Claims] 1. An arithmetic unit for repeatedly performing sum-of-products calculation based on supplied data, wherein data holding means for temporarily holding data supplied from the outside and output from the data holding means are used as multiplication coefficients, And a multiplication means for multiplying the multiplication coefficient by an externally supplied multiplicand, and an arithmetic logic means for storing externally supplied data in a register to perform an arithmetic operation and a logical operation. An arithmetic unit comprising the arithmetic logic means connected in series. 2. The arithmetic unit has an address calculating unit for calculating an address of a local memory provided outside the arithmetic unit, and the multiplying unit reads data according to the address from the address calculating unit. The arithmetic unit according to claim 1, wherein the arithmetic unit is operated based on 3. A parallel arithmetic system comprising a plurality of arithmetic units connected in parallel, wherein the arithmetic unit according to claim 1 is used for each arithmetic unit.