JPH0621472A - Semiconductor memory and fabrication thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory and a method of fabrication thereof wherein a channel length is unchanged, and a cell size is not larger than a stacked gate, and further there is ensured an excess erasing measure with respect to a structure. CONSTITUTION:In a stacked semiconductor memory which is yielded by laminating a floating gate and a control gate putting an insulating layer therebetween, control gates 3 are disposed up and down mediating a connection portion and putting an insulating layer 4 therebetween, and a lower portion of a control gate 5 is disposed adjoining to the floating gate 3 putting a second insulating layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory and its manufacturing method, and more particularly to a floating type MOS as a memory cell.
Flash EEPROM (Electric
ally Erasable Programmable ROM: electrically erasable ROM).

[0002]

2. Description of the Related Art Among MOS ROMs, a floating gate type M is used as a semiconductor memory cell with an EEPROM.
The OS transistor is used. A Flash EEPROM that can electrically erase this EEPROM instantaneously
The problem is that so-called over-erasing, which means erasing more than a predetermined amount of memory inevitably due to its function. This EE
Some countermeasures against over-erasure of PROM have been studied, but a definitive solution has not been issued yet.

As one of the measures against the excessive erasing of the EEPROM, as shown in FIG. 6, a Split Gate type EEPROM is known. EE shown in FIG.
The PROM has a floating gate 3 (width B).
Between the control gate 5 and the select gate (width A), a crack (Split) made of the insulating film 21 is provided to prevent excessive erasing. That is, the depletion is under the floating gate 5.
Since the channel is cut by the control gate 5 even in the state, the structure is such that the leak current does not flow even if it is overerased.

Therefore, the conventional Split Gate shown in FIG.
Type EEPROMs are extremely superior in terms of ease of use because overerasing can be solved with a simple structure.

The conventional Split Gate type EEP shown in FIG.
A method of manufacturing the ROM is shown in FIG.

First, as shown in FIG. 7A, a gate oxide film 2 is formed on a silicon (Si) substrate 1 by thermal oxidation.
Formed to a thickness of 0 nm, and further CVD on the gate oxide film 2.
By the (chemical vapor deposition) method, polysilicon (poly-
By forming a Si) film and patterning it using a photolithography technique, a poly-Si pattern (poly-1) 3a for a floating gate is formed.

Next, as shown in FIG. 7B, thermal oxidation treatment is performed again, and the interlayer insulating film 2 is formed on the Si substrate 1 and on the upper surface and side walls of the poly-Si pattern 3a to a thickness of about 20 nm.
1 is formed. After that, a poly-Si film for control gates (poly) is formed on the interlayer insulating film 21 by a CVD method.
-2) Form 5a.

Next, as shown in FIG. 7C, the poly-2 (5a) is etched on both sides and the poly-1 (3a) is etched on only one side by a photolithography technique. The main part of the obtained memory structure has the same structure as that shown in FIG.

[0009]

The above-mentioned conventional EEPR
In the OM structure, both the floating gate 3 and the control gate 5 are very susceptible to the alignment accuracy of the photolithography technique in their manufacture. That is, in a normal memory cell, the channel length L of a transistor is determined only by its processing accuracy, whereas in a conventional Split Gate type EEPROM with a countermeasure against excessive erasure,
The channel length L of the transistor is, as in the method described above,
Determined by machining accuracy + misalignment. Therefore, the sizes A and B shown in FIG. 6, and hence the channel length L, fluctuate greatly, and the memory characteristics also fluctuate greatly.

Therefore, an object of the present invention is to provide a semiconductor memory in which the channel length is constant, the cell size is not larger than that of the Stack Gate, and structurally measures against excessive erasure are taken, and a manufacturing method thereof. To do.

[0011]

According to the present invention, there is provided a stacked semiconductor memory in which a floating gate and a control gate are laminated with an insulating layer sandwiched therebetween, in which the control gate is connected via a connecting portion. A semiconductor memory cell is disposed above and below the insulating layer, and a lower portion of the control is disposed adjacent to the floating gate via a second insulating layer. .

In the present invention, it is preferable that the upper and lower connecting portions of the control gate are formed by sidewalls.

Further, according to the present invention, the above-mentioned problem is a method of manufacturing a stack type semiconductor memory in which a floating gate and a control gate are laminated with an insulating layer sandwiched therebetween. Floating gate constituent material, first interlayer insulating layer, control gate constituent material and oxidation resistant layer are sequentially deposited and formed, and the oxidation resistant layer and control gate constituent material are patterned to form at least two opposing control gate portions. The step of sequentially removing the first interlayer insulating layer and the floating gate constituent material along the non-opposing outer surfaces of the control gate portion by etching, forming an interlayer insulating layer on the entire surface, and then performing the etching. Insulation sidewall is formed on the side wall of the control unit A part of the floating gate constituent material is removed by isotropic etching using the id wall as a mask to form at least two floating gates; and after the exposed surface of the floating gates is oxidized, the at least two control gates Of the oxidation resistant film on the inner upper surface facing each other, and the second insulating sidewall that reaches the gate insulating film on the outer surface of the control gate portion that is not opposed by etching the interlayer insulating film and the insulating sidewall. A step of forming a control gate constituent second material for forming the control gate portion connecting portion and a lower portion on the entire surface, and a step of forming a control portion connecting portion and a lower portion of the control constituent second material by etching. Characterized by including, It is solved by the method for manufacturing a semiconductor memory.

In the present invention, a resist pattern is formed on at least a part of the second material for constituting the control gate, and the connecting portion and the lower portion of the control gate are formed in a sidewall shape by etching using the resist pattern as a mask. It is preferable.

In the present invention, one end of each of the floating gate and the control gate is formed by self-alignment by anisotropic etching, and the other end of the floating gate is formed by isotropic side etching. Is preferred.

[0016]

According to the present invention, as shown in FIG. 1, the control gate is connected between the floating gate 3 and the lower part of the control gate 5 such that the interlayer insulating layer 10 is self-aligned. It is configured to have a lower portion, and the cell size does not become larger than that of the stack gate type memory.

Further, as shown in FIGS. 2B to 2C, one end of the floating gate 3 is manufactured in self-alignment with one end of the control gate formed thereon, and the other end is formed as shown in FIG. Since the length can be selected by isotropic etching as shown in FIGS. 3 (b) to 3 (c), it can be determined in a self-aligned manner. Further, the length corresponding to the select gate is also determined in a self-aligned manner by the isotropic etching and the etching as shown in FIGS.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the Split Gate type EEP of the present invention.
FIG. 6 is a cross-sectional view for explaining an example of a ROM.

In FIG. 1, the memory cell of this embodiment is shown with two cells 30 and 31 facing each other with the source region 22a interposed therebetween for easy understanding.

The cell 30 on the right side of FIG. 1 will be described to facilitate correspondence with the memory cell structure of FIG. 6 described in the prior art.

In the cell 30 of FIG. 1, even if the floating gate (FG) 3 is over-erased and the channel thereunder is brought into conduction, the control gate (CG) 5 cuts the conduction. No problem work current flows. That is, it is structurally the same as the conventional Split Gate type shown in FIG.

Further, the Split Gate of the present invention shown in FIG. 1 is used.
The memory cell structure of the mold will be described in more detail.

In this structure, a gate oxide film (S) is formed on a silicon substrate 1 having a source region 22a and a drain region 22b.
iO ₂ ) 2 is formed to a thickness of 20 nm, and a floating gate 3 made of poly-Si having a thickness of 100 nm is provided thereon, and the floating gate 3 is provided on and above the floating gate 3 via a connecting portion 12a ′. A control gate 5 is provided on the upper and lower sides with the oxide films 4 and 10 interposed therebetween. Further, the lower portion 12c (selection gate) of the control gate 5 is arranged adjacent to the floating gate 3 via the oxide film 10 in a self-aligned manner. Reference numeral 9 is a nitride film (oxidation resistant film). The control gate 5 has a structure in which an insulating film protruding between the upper and lower layers is formed in the upper and lower layers.

An embodiment of a method of manufacturing the structure shown in FIG. 1 will be described below with reference to process sectional views of FIGS.

In order to manufacture the structure of the present invention, as shown in FIG. 2A, a gate oxide film (SiO ₂ ) 2 is first formed on a silicon (Si) substrate 1 by thermal oxidation by a known technique.
Floating gate (Floating G
ate) polysilicon film (poly-Si) 3a 10
Oxide film 4 with a thickness of 0 nm and on top of it by thermal oxidation
To a thickness of 20 nm, and a poly-Si film 5a for control gate (Control Gate) 150a thereon.
After the nitride film 9 is deposited to a thickness of m and the nitride film 9 is deposited to a thickness of 50 nm, a photoresist is applied on the entire surface and patterned to form two resist patterns 6.

Next, as shown in FIG. 2B, using the resist pattern 6 as a mask, the nitride film 9 and the poly-Si are formed.
The film 5a is sequentially removed by RIE (reactive ion etching), and a photoresist is applied to the entire surface of the resist pattern 6 and so as to fill the space between the control gate poly-Si film 5a, and then patterned to form a resist pattern 7. To form.

Resist pattern 6, and therefore poly-S
Using the i film 5a and the resist pattern 7 as a mask, the oxide film 4 and the floating gate poly-Si film 3a are removed by self-alignment etching, and then the resist patterns 6 and 7 are removed (FIG. 2C).

Next, as shown in FIG. 3A, CVD
CV to a thickness of 200 nm by (Chemical Vapor Deposition) method
A D oxide film (SiO ₂ ) 8 is formed.

Thereafter, a photoresist is applied and patterned to form a resist pattern 10, and the oxide film 8 is anisotropically etched using the resist pattern 10 as a mask to form sidewalls 8a (FIG. 3B).

In this state, the floating gate pol
The y-Si film 3a is isotropically etched (wet etching). At this time, po for the control gate (CG)
Since the upper surface of the ly-Si film 5a is covered with the nitride film 9 and the side surface thereof is covered with the oxide film 8a, the ly-Si film 5a is not etched.
Floating gate (FG) poly-Si film 3a
Only the exposed part is gradually etched.

In this isotropic etching (side etching), as shown in FIG. 3C, FG3 is used for CG po.
The process is performed until the side surface of the ly-Si film 5a is fully etched by a predetermined length.

After that, as shown in FIG. 4A, only the exposed side surface of the isotropically etched FG 3 is oxidized by a predetermined amount to form an oxide film 14. Then, the nitride film 9 is selectively etched to expose the CG poly-Si film 5a.

Next, as shown in FIG. 4 (b), after removing the resist pattern 10, the exposed oxide film is etched by anisotropic etching to remove the sidewalls 8a and the CG poly-. A new sidewall 8b is formed on the side opposite to the sidewall 8a with respect to the Si film 5a.

Next, as shown in FIG. 4 (c), p is formed on the entire surface.
Poly-Si is deposited to a thickness of 200 nm by the CVD method to form the poly-Si film 12a for the control connection portion. In this step, the poly-Si film 12a is made of F
G3 enters the etched recess (bottom) and is sufficiently buried so as to contact the oxide film 14. In addition, this poly-Si film 12 a is adjacent to the floating gate 3 via the oxide film 14 at the embedded portion, that is, a part of the so-called lower portion of the control gate. poly-S
The i film 5a is sufficiently ohmic-contacted at its exposed portion.

Next, as shown in FIG. 5, a resist pattern 13 is formed on the resist pattern 13 by a photolithography technique.
It is formed above the ohmic contact portion of the y-Si film 5a. In the resist pattern 13, if the misalignment is 0.15 μm, the width 17 of the sidewall 12b of the poly-Si film 12a is set to 0.15 μm. At this time, from the resist pattern 13 to the CG pol
The horizontal distance 16 to the left end of the y-Si film 5a is 0.2 μm.
Met. In this way, after forming the resist pattern 13, the poly-S is used with this resist pattern as a mask.
The i film 12a is etched to obtain the EEPROM shown in FIG.
Get the structure. In this etching, the poly-Si film 1
Whether 2a is left in a sidewall shape or completely removed is not determined at this stage depending on the characteristics of the memory at that time and the like. If you want to leave a poly-Si side wall, p
It is also possible to sufficiently perform isotropic etching after covering the sidewalls of the oli-Si film with a resist pattern.

[0037]

As described above, according to the present invention,
The width of the poly-Si film for the floating gate (FG) is determined in a self-aligned manner simply by poly-Si etching processing without matching the resist pattern by photolithography technology, and the contact gate also corresponds to the floating gate. In this way, the structure is a countermeasure against excessive erasure that is manufactured in a self-aligned and compact manner.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a Split Gate type memory cell structure of the present invention.

FIG. 2 is a process sectional view (I) of one embodiment of the present invention.

FIG. 3 is a process sectional view (II) of one embodiment of the present invention.

FIG. 4 is a process sectional view (III) of the embodiment of the present invention.

FIG. 5 is a process sectional view (IV) of one embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view showing a conventional Split Gate type memory cell structure.

FIG. 7 is a schematic cross-sectional view showing a conventional Split Gate type memory cell structure.

[Explanation of symbols]

 1 Silicon (Si) Substrate 2 Gate Oxide Film 3 Floating Gate (FG) 3a Poly-Si Film for Floating Gate 4,14 Oxide Film 5 Control Gate (CG) 5a Poly-Si Film for Control Gate 6, 7, 10, 13 Resist pattern 9 Nitride film 12a Poly-Si film for control gate connection part 12a 'Control gate connection part 12b Side wall 12c Control lower part 21 Interlayer insulating film 22a Source region 22b Drain region 30,31 Cell

Claims (5)

[Claims] 1. A stack type semiconductor memory in which a floating gate and a control gate are laminated with an insulating layer sandwiched therebetween, wherein the control gate is vertically arranged with the insulating layer sandwiched through a connecting portion, and A semiconductor memory cell, wherein a lower part of the control is arranged adjacent to the floating gate via a second insulating layer. 2. The semiconductor memory according to claim 1, wherein the upper and lower connecting portions of the control gate are formed by sidewalls. 3. A method of manufacturing a stack type semiconductor memory comprising a floating gate and a control gate laminated with an insulating layer sandwiched therebetween, comprising: a gate insulating film, a floating gate constituent material, and a first interlayer insulating film on a silicon substrate. A step of sequentially depositing and forming a layer, a control gate constituent material and an oxidation resistant layer, patterning the oxidation resistant layer and the control gate constituent material to form at least two opposing control gate portions, facing the control gate portion The step of sequentially removing the first interlayer insulating layer and the floating gate constituent material along the outer side surface by etching, after forming the interlayer insulating layer on the entire surface, etching is performed to form an insulating sidewall on the side wall of the opposing control section. Formed, using the insulating sidewall as a mask A step of removing at least two floating gate constituent materials by isotropic etching to form at least two floating gates; oxidizing exposed surfaces of the floating gates, and then facing opposite insides of the at least two control gate portions; Removing the oxidation resistant film on the upper surface, etching the interlayer insulating film and the insulating sidewall to form a second insulating sidewall reaching the gate insulating film on the non-opposing outer surface of the control gate portion, Forming a control gate constituent second material for forming the control gate portion connecting portion and a lower portion on the entire surface; and forming a control portion connecting portion and a lower portion of the control constituent second material by etching. Characteristic semiconductor memory manufacturing method . 4. A resist pattern is formed on at least a part of the control gate forming second material, and the control gate connecting portion and the lower portion are formed in a sidewall shape by etching using the resist pattern as a mask. The method of claim 2 characterized. 5. One end of each of the floating gate and the control gate is formed by self-alignment by anisotropic etching, and the other end of the floating gate is formed by isotropic side etching. The method of claim 2.