JPH0621272A - Semiconductor - Google Patents
SemiconductorInfo
- Publication number
- JPH0621272A JPH0621272A JP17242392A JP17242392A JPH0621272A JP H0621272 A JPH0621272 A JP H0621272A JP 17242392 A JP17242392 A JP 17242392A JP 17242392 A JP17242392 A JP 17242392A JP H0621272 A JPH0621272 A JP H0621272A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- sealing resin
- semiconductor
- resin
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Physical Vapour Deposition (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体素子を有し、そ
の囲りを樹脂封止している半導体装置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which has a semiconductor element and whose surrounding is sealed with a resin.
【0002】[0002]
【従来の技術】近年、半導体装置の多機能化、縮小化に
ともない、半導体素子の表面実装化が進んでいる。2. Description of the Related Art In recent years, as semiconductor devices have become more multifunctional and smaller, the surface mounting of semiconductor elements has been progressing.
【0003】従来の技術について、図面を参照しながら
説明する。図4は、バンプを介しリードフレームと接合
している従来の半導体装置の断面図である。1は半導体
素子、2はリードフレーム、3は前記半導体素子と前記
リードフレームを電気的に接合するためのバンプ、4は
これらを覆う封止樹脂である。A conventional technique will be described with reference to the drawings. FIG. 4 is a cross-sectional view of a conventional semiconductor device bonded to a lead frame via bumps. Reference numeral 1 is a semiconductor element, 2 is a lead frame, 3 is a bump for electrically connecting the semiconductor element and the lead frame, and 4 is a sealing resin that covers them.
【0004】従来は、半導体素子1の裏面はなにも処理
することなく樹脂封止していた。Conventionally, the back surface of the semiconductor element 1 was resin-sealed without any treatment.
【0005】[0005]
【発明が解決しようとする課題】しかしながら上記従来
の半導体装置では、プリント基板に実装する際、封止樹
脂4に吸湿した水分により、封止樹脂4と半導体素子1
の裏面の間で水蒸気圧が発生し、その圧力で封止樹脂4
と半導体素子1の裏面の間がはく離したり、又は封止樹
脂4が割れる現象が発生していた。封止樹脂4と半導体
素子1の裏面の間がはく離したり、又は封止樹脂4が割
れるため、水分が半導体装置内部に浸入するリードパス
が短くなり、その後の耐湿信頼性が悪くなってしまう。However, in the above-mentioned conventional semiconductor device, when the semiconductor device is mounted on a printed circuit board, the sealing resin 4 and the semiconductor element 1 are caused by moisture absorbed by the sealing resin 4.
Water vapor pressure is generated between the back surfaces of the sealing resin 4 and the pressure.
There is a phenomenon in which the back surface of the semiconductor element 1 is peeled off or the sealing resin 4 is cracked. Peeling between the sealing resin 4 and the back surface of the semiconductor element 1 or cracking of the sealing resin 4 shortens the lead path through which moisture penetrates into the semiconductor device, resulting in poor moisture resistance reliability.
【0006】本発明は上記課題を解決するもので、封止
樹脂4と半導体素子1の裏面の間のはく離、又は封止樹
脂4の割れを防止した半導体装置を提供することを目的
としている。The present invention is intended to solve the above problems, and an object thereof is to provide a semiconductor device in which peeling between the sealing resin 4 and the back surface of the semiconductor element 1 or cracking of the sealing resin 4 is prevented.
【0007】[0007]
【課題を解決するための手段】本発明は上記課題を解決
するために、半導体素子の裏面に酸化珪素膜又は窒化珪
素膜に代表される珪素化合物膜を形成することを特徴と
する。In order to solve the above problems, the present invention is characterized in that a silicon compound film typified by a silicon oxide film or a silicon nitride film is formed on the back surface of a semiconductor element.
【0008】[0008]
【作用】本発明は上記構成により、半導体素子と封止樹
脂のすき間をなくし、珪素化合物膜により密着性を向上
させることにより、半導体素子裏面と封止樹脂の間のは
く離、又はプラスチック封止樹脂の割れを防ぐことがで
きる。According to the present invention having the above structure, the gap between the semiconductor element and the sealing resin is eliminated, and the adhesion is improved by the silicon compound film. Can be prevented from cracking.
【0009】[0009]
【実施例】以下、本発明の実施例について図1および図
2を参照しながら説明する。図1は、バンプを介し半導
体素子とリードフレームを電気的に接合し、その囲りを
封止樹脂で覆ったものであり、5は半導体素子、6はリ
ードフレーム、7はバンプ、8は封止樹脂、9は酸化珪
素膜である。図2は、バンプを介し半導体素子とリード
フレームを電気的に接合し、その囲りを封止樹脂で覆っ
たものであり、10は半導体素子、11はリードフレー
ム、12はバンプ、13は封止樹脂、14は窒化珪素膜
である。Embodiments of the present invention will be described below with reference to FIGS. 1 and 2. 1A and 1B show a semiconductor element and a lead frame electrically joined via a bump, and the surrounding thereof is covered with a sealing resin. 5 is a semiconductor element, 6 is a lead frame, 7 is a bump, and 8 is a seal. Stop resin, 9 is a silicon oxide film. FIG. 2 is a diagram in which a semiconductor element and a lead frame are electrically joined via bumps and the surroundings are covered with a sealing resin. 10 is a semiconductor element, 11 is a lead frame, 12 is a bump, and 13 is a seal. Resin 14 is a silicon nitride film.
【0010】次に図1および図2に示す本発明の実施例
に係る半導体装置の動作例として、図3を参照して信頼
性試験結果を示す。Next, as an operation example of the semiconductor device according to the embodiment of the present invention shown in FIGS. 1 and 2, a reliability test result will be shown with reference to FIG.
【0011】図3に示すように厳しい条件で信頼性試験
として封止樹脂に強制加湿試験を行った後、高温のはん
だに浸漬しても、半導体素子5,10の裏面と封止樹脂
8,13の間のはく離、及び樹脂8,13の割れが発生
することがない。As shown in FIG. 3, after conducting a forced humidification test on the encapsulating resin as a reliability test under severe conditions, even if the encapsulating resin is immersed in high temperature solder, the back surfaces of the semiconductor elements 5, 10 and the encapsulating resin 8, There is no peeling between 13 and cracking of the resins 8 and 13.
【0012】なお、酸化珪素膜9、窒化珪素膜14を形
成するには、蒸着により可能である。The silicon oxide film 9 and the silicon nitride film 14 can be formed by vapor deposition.
【0013】[0013]
【発明の効果】以上の実施例から明らかなように、本発
明によれば、プリント基板に半導体素子を実装した際、
半導体素子の裏面と封止樹脂の間のはく離、又は封止樹
脂の割れることがない半導体装置を実現できるものであ
る。As is apparent from the above embodiments, according to the present invention, when a semiconductor element is mounted on a printed circuit board,
It is possible to realize a semiconductor device without peeling between the back surface of the semiconductor element and the sealing resin or cracking of the sealing resin.
【図1】本発明の実施例のシリコン基板の裏面に酸化珪
素膜を蒸着した半導体装置の断面図FIG. 1 is a cross-sectional view of a semiconductor device having a silicon oxide film deposited on the back surface of a silicon substrate according to an embodiment of the present invention.
【図2】本発明の実施例のシリコン基板の裏面に窒化珪
素膜を蒸着した半導体装置の断面図FIG. 2 is a cross-sectional view of a semiconductor device having a silicon nitride film deposited on the back surface of a silicon substrate according to an embodiment of the present invention.
【図3】本発明の実施例に係る半導体装置に対して、信
頼性試験を実施した際の結果を示す図FIG. 3 is a diagram showing a result when a reliability test is performed on a semiconductor device according to an example of the present invention.
【図4】従来の半導体装置の断面図FIG. 4 is a sectional view of a conventional semiconductor device.
1,5,10 半導体素子 2,6,11 リードフレーム 3,7,12 バンプ 4,8,13 封止樹脂 9 酸化珪素膜 14 窒化珪素膜 1, 5, 10 Semiconductor element 2, 6, 11 Lead frame 3, 7, 12 Bump 4, 8, 13 Sealing resin 9 Silicon oxide film 14 Silicon nitride film
Claims (3)
態で樹脂封止されていることを特徴とする半導体装置。1. A semiconductor device characterized by being resin-sealed with a silicon compound film on the back surface of a semiconductor element.
徴とする請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the silicon compound film is a silicon oxide film.
徴とする請求項1記載の半導体装置。3. The semiconductor device according to claim 1, wherein the silicon compound film is a silicon nitride film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17242392A JPH0621272A (en) | 1992-06-30 | 1992-06-30 | Semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17242392A JPH0621272A (en) | 1992-06-30 | 1992-06-30 | Semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0621272A true JPH0621272A (en) | 1994-01-28 |
Family
ID=15941698
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17242392A Pending JPH0621272A (en) | 1992-06-30 | 1992-06-30 | Semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0621272A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116053239A (en) * | 2023-04-03 | 2023-05-02 | 中科华艺(天津)科技有限公司 | Packaging structure of multi-chip assembly |
-
1992
- 1992-06-30 JP JP17242392A patent/JPH0621272A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116053239A (en) * | 2023-04-03 | 2023-05-02 | 中科华艺(天津)科技有限公司 | Packaging structure of multi-chip assembly |
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