JPH0621228Y2 - Chip type composite capacitor - Google Patents
Chip type composite capacitorInfo
- Publication number
- JPH0621228Y2 JPH0621228Y2 JP14406388U JP14406388U JPH0621228Y2 JP H0621228 Y2 JPH0621228 Y2 JP H0621228Y2 JP 14406388 U JP14406388 U JP 14406388U JP 14406388 U JP14406388 U JP 14406388U JP H0621228 Y2 JPH0621228 Y2 JP H0621228Y2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- capacitor element
- chip
- type composite
- electrolytic capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 本考案はチップ型複合コンデンサに関し、特に電解コン
デンサ素子とセラミックコンデンサ素子とを重ね合わせ
てなるチップ型の複合コンデンサに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a chip-type composite capacitor, and more particularly to a chip-type composite capacitor in which an electrolytic capacitor element and a ceramic capacitor element are stacked.
一般的に電解コンデンサはセラミックコンデンサに比べ
コンデンサの容量が大きいので低周波領域におけるイン
ピーダンス特性は良いが、等価直列抵抗が大きいため、
高周波領域でのインピーダンスが大きいという欠点があ
る。このため、低周波領域から高周波領域までの広い範
囲で良好なインピーダンス特性を得るために、2つのコ
ンデンサを電気的に並列になるように回路基板上に配置
していた。2つのコンデンサを別々に配置したのでは、
実装コストが2倍になるだけではなく実装密度も下がっ
てしまうという問題がある。Generally, an electrolytic capacitor has a larger capacitance than a ceramic capacitor, so the impedance characteristics in the low frequency region are good, but since the equivalent series resistance is large,
It has the drawback of high impedance in the high frequency range. Therefore, in order to obtain good impedance characteristics in a wide range from the low frequency region to the high frequency region, the two capacitors are arranged on the circuit board so as to be electrically parallel to each other. If you place the two capacitors separately,
There is a problem that not only the mounting cost is doubled but also the mounting density is lowered.
この問題を解決する手段として、電解コンデンサとイン
ピーダンス特性の良いコンデンサを並列に接続した複合
コンデンサが考えられる。As a means for solving this problem, a composite capacitor in which an electrolytic capacitor and a capacitor having good impedance characteristics are connected in parallel can be considered.
従来の技術としては、例えば第5図に示した特公昭55
−47718公報のように電解コンデンサ3aのリード
9a,9bとインピーダンス特性改善コンデンサ8のリ
ード8a,8bを2つのコンデンサが並列になるよう
に、端子11a,11bに接続した後、容器12に収納
し、しかる後、封止部材10で端子11a,11bの一
部を外部へ露出させるようにして封口した複合コンデン
サがある。As a conventional technique, for example, Japanese Patent Publication Sho 55 shown in FIG.
-Leads 9a and 9b of the electrolytic capacitor 3a and leads 8a and 8b of the impedance characteristic improving capacitor 8 are connected to the terminals 11a and 11b so that the two capacitors are parallel to each other, and then housed in the container 12 as in Japanese Patent Publication No. 47718. After that, there is a composite capacitor in which the sealing member 10 seals a part of the terminals 11a and 11b so as to be exposed to the outside.
しかしながら、この複合コンデンサはリード線を有する
2つのコンデンサの各々のリード線部を並列に接続した
後、同一容器内に封入した構造となっているので外形寸
法が大きくなってしまうという欠点だけでなく、チップ
型とすることができないので高密度実装ができないとい
う欠点がある。However, this composite capacitor has a structure in which the lead wires of two capacitors each having a lead wire are connected in parallel and then sealed in the same container, so not only is the external dimension increased, However, since it cannot be made into a chip type, it has a drawback that high-density mounting cannot be performed.
そこで、第6図の如く、電解コンデンサ素子3より導出
された陽極引き出しリード線4と陽極端子の平面部1c
を有する陽極素子3に電気溶接により電気的に接続す
る。しかる後、セラミックコンデンサ素子5の電極部6
に前記陽極端子の平面部1cと電解コンデンサ素子を重
ね合わせるようにして導電性接着剤7で接続したチップ
型複合コンデンサがある。Therefore, as shown in FIG. 6, the anode lead wire 4 led out from the electrolytic capacitor element 3 and the flat portion 1c of the anode terminal.
Is electrically connected to the anode element 3 having a. After that, the electrode portion 6 of the ceramic capacitor element 5
There is a chip-type composite capacitor in which the flat portion 1c of the anode terminal and the electrolytic capacitor element are superposed and connected by a conductive adhesive 7.
上述した従来チップ型複合コンデンサは、第6図の如く
電解コンデンサの陽極端子が、セラミックコンデンサ素
子の電極部と重ね合わせて接続されているので、このチ
ップ型複合コンデンサはセラミックコンデンサ素子側を
実装面としなければならない。このため、このチップ型
複合コンデンサを自動実装しようとした場合には電解コ
ンデンサ素子面を吸着して実装しなければならない。し
かしながら、電解コンデンサ素子は、セラミックコンデ
ンサ素子と比べ平らな部分が少ないので、吸着ノヅルで
吸着できないという問題がある。同様の理由で、第5図
の如くチップ型複合コンデンサはチップ型でありなが
ら、自動実装をおこなうことが非常に難しいという欠点
がある。In the conventional chip type composite capacitor described above, the anode terminal of the electrolytic capacitor is overlapped and connected with the electrode portion of the ceramic capacitor element as shown in FIG. 6, so that this chip type composite capacitor is mounted on the ceramic capacitor element side. And have to. Therefore, when attempting to automatically mount this chip-type composite capacitor, the electrolytic capacitor element surface must be attached by suction. However, since the electrolytic capacitor element has a smaller number of flat portions than the ceramic capacitor element, there is a problem that the electrolytic capacitor element cannot be adsorbed by the adsorption nozzle. For the same reason, the chip-type composite capacitor as shown in FIG. 5 is chip-type, but has a drawback that it is very difficult to perform automatic mounting.
本考案の目的は、広範囲で良好なインピーダンス特性を
持ち、小型化され、かつ表面実装が可能で、しかも低価
格化ができ、さらに自動実装が可能なチップ型複合コン
デンサを提供することにある。An object of the present invention is to provide a chip-type composite capacitor which has good impedance characteristics in a wide range, can be miniaturized, can be surface-mounted, can be reduced in cost, and can be automatically mounted.
本考案のチップ型複合コンデンサは、中央突出部と上部
平面部及び下部平面部を有する陽極端子の中央突出部に
電解コンデンサ素子より引き出された陽極引き出しリー
ド線が電気的に接続され、電極形成の完了したチップ型
のセラミックコンデンサ素子の電極部が前記陽極端子の
上面、および電解コンデンサ素子の上面に重ね合わせて
電気的に並列に接続されたことを特徴として構成され
る。In the chip-type composite capacitor of the present invention, the anode lead wire drawn from the electrolytic capacitor element is electrically connected to the central protruding portion of the anode terminal having the central protruding portion, the upper flat portion and the lower flat portion to form an electrode. The electrode part of the completed chip type ceramic capacitor element is superposed on the upper surface of the anode terminal and the upper surface of the electrolytic capacitor element and electrically connected in parallel.
次に、本考案について図面を参照して説明する。第2図
は、本考案のチップ型複合コンデンサの陽極端子の斜視
図である。下部平面部1bを有する陽極端子1の上部を
折り曲げて上面部1aを形成し、その上面部1aの一部
に切り込みを入れて折り曲げて中央突出部2aを形成す
る。Next, the present invention will be described with reference to the drawings. FIG. 2 is a perspective view of an anode terminal of the chip type composite capacitor of the present invention. The upper portion of the anode terminal 1 having the lower plane portion 1b is bent to form the upper surface portion 1a, and a notch is made in a part of the upper surface portion 1a and then bent to form the central protruding portion 2a.
第1図は本考案の第1の実施例のチップ型複合コンデン
サの断面図である。陽極端子1の中央突出部2に電解コ
ンデンサ素子3より引き出された陽極引き出しリード線
4を電気溶接で接続する。しかる後、電極形成が完了し
たチップ型のセラミックコンデンサ素子5の電極部6を
それぞれ電解コンデンサ素子の上面部3aと陽極端子1
の上面1aに導電性接着剤7で接続する。FIG. 1 is a sectional view of a chip type composite capacitor according to a first embodiment of the present invention. An anode lead wire 4 drawn from the electrolytic capacitor element 3 is connected to the central protruding portion 2 of the anode terminal 1 by electric welding. Then, the electrode portion 6 of the chip-type ceramic capacitor element 5 on which the electrode formation is completed is connected to the upper surface portion 3a of the electrolytic capacitor element and the anode terminal 1, respectively.
It is connected to the upper surface 1a of the above with a conductive adhesive 7.
第3図は本考案の第2の実施例の断面図である。陽極端
子1の上部を折り曲げて形成した上面部1aと逆方向に
折り曲げて中央突出部2を形成する。しかる後、第1の
実施例と同様に電解コンデンサ素子3とチップ型のセラ
ミックコンデンサ素子5を重ね合わせて接続する。この
実施例では第1の実施例に比べ外形寸法が大きくなる
が、中央突出部2の上部に陽極端子1の上部面1aがな
いので、中央突出部2に電解コンデンサ素子3より引き
出された陽極引き出しリード線4を電気溶接で接続する
作業が容易であるという組み立て作業上の利点がある。FIG. 3 is a sectional view of the second embodiment of the present invention. The central projection 2 is formed by bending the anode terminal 1 in the direction opposite to the upper surface 1a formed by bending the upper portion. Then, similarly to the first embodiment, the electrolytic capacitor element 3 and the chip-type ceramic capacitor element 5 are superposed and connected. In this embodiment, the outer dimensions are larger than those in the first embodiment, but since the upper surface 1a of the anode terminal 1 is not provided on the upper portion of the central protruding portion 2, the anode protruding from the electrolytic capacitor element 3 is attached to the central protruding portion 2. There is an advantage in assembling work that the work of connecting the lead wire 4 by electric welding is easy.
第4図はインピーダンスの周波数特性を示している。第
4図中のグラフ1はタンタルコンデンサンサ(容量:
6.8μF)単体のインピーダンスの周波数特性、グラ
フ2はセラミックコンデンサ(容量:0.1μF)単体
でのインピーダンスの周波数特性、グラフ3はタンタル
コンデンサ素子(容量:6.8μF)とセラミックコン
デンサ素子(容量:0.1μF)により製造した本考案
のチップ型複合コンデンサのインピーダンスの周波数特
性を示している。FIG. 4 shows impedance frequency characteristics. Graph 1 in Fig. 4 shows the tantalum condenser (capacity:
6.8 μF) impedance frequency characteristics of a single unit, graph 2 shows impedance frequency characteristics of a ceramic capacitor (capacity: 0.1 μF) single unit, graph 3 shows tantalum capacitor element (capacity: 6.8 μF) and ceramic capacitor element (capacitance: : 0.1 μF), the frequency characteristics of impedance of the chip type composite capacitor of the present invention are shown.
以上説明したように本考案は、中央突出部と上部平面部
及び下部平面部を有する陽極端子の中央突出部に電解コ
ンデンサの陽極引き出しリードを接続し、しかる後電解
コンデンサ素子の上面部と陽極端子の上面部にチップ型
のセラミックコンデンサ素子の電極部を重ね合わせて導
電性接着剤で接着することにより、第4図に示した如
く、低周波領域では容量の大きな電解コンデンサの特徴
をもち、高周波領域では、E.S.R(等価直列抵抗)
の小さなセラミックコンデンサの特徴を有するコンデン
サ、つまり広範囲で良好なインピーダンス特性を有する
複合コンデンサが得られるだけではなくチップ型の複合
コンデンサとすることができるので、従来の複合コンデ
ンサと比べ小型化されていると同時に表面実装が可能と
なり複合コンデンサを使用した装置の小型化低価格化で
きるという効果がある。As described above, according to the present invention, the anode lead of the electrolytic capacitor is connected to the central protruding portion of the anode terminal having the central protruding portion, the upper flat portion and the lower flat portion, and then the upper surface portion of the electrolytic capacitor element and the anode terminal are connected. As shown in FIG. 4, the electrode part of the chip-type ceramic capacitor element is superposed on the upper surface of and is adhered with a conductive adhesive, so that it has the characteristics of an electrolytic capacitor with a large capacitance in the low frequency region, In the region, E. S. R (equivalent series resistance)
Is smaller than the conventional composite capacitor because not only a capacitor having the characteristics of a small ceramic capacitor, that is, a composite capacitor having good impedance characteristics in a wide range can be obtained, but also a chip type composite capacitor can be obtained. At the same time, there is an effect that surface mounting becomes possible and the size and cost of the device using the composite capacitor can be reduced.
さらに、本考案のコンデンサは、実装面を電解コンデン
サ側自動実装する際の吸着面を素子本体に平面部を有す
るチップ型のセラミックコンデンサ素子側とすることが
できるので自動実装が容易になるという利点がある。Further, in the capacitor of the present invention, the mounting surface can be automatically mounted on the electrolytic capacitor side because the adsorption surface can be the chip type ceramic capacitor element side having the flat portion on the element body, which facilitates automatic mounting. There is.
第1図は本考案の第1の実施例のチップ型複合コンデン
サの断面図、第2図は本考案の第1の実施例のチップ型
複合コンデンサの陽極端子の斜視図、第3図は本考案の
第2の実施例のチップ型複合コンデンサの断面図、第4
図は電解コンデンサ、セラミックコンデンサそれぞれの
単体の場合と本考案のチップ型複合コンデンサのインピ
ーダンスの周波数特性を示したグラフ、第5図は従来技
術の複合コンデンサの断面図、第6図は電解コンデンサ
素子とセラミックコンデンサ素子を組み合わせてなる従
来技術のチップ型の複合コンデンサの断面図である。 1……陽極端子、1a……上面部、1b……下部平面
部、1c……陽極端子の平面部、2……中央突出部、3
……電解コンデンサ素子、3a……電解コンデンサ、4
……陽極引き出しリード線、5……チップ型のセラミッ
クコンデンサ素子、6……電極部、7……導電性接着
剤、8……特性改善コンデンサ、8a,8b……特性改
善コンデンサのリード、9a,9b……リード、10…
…封止部材、11a,11b……端子、12……容器。FIG. 1 is a sectional view of a chip type composite capacitor of the first embodiment of the present invention, FIG. 2 is a perspective view of an anode terminal of the chip type composite capacitor of the first embodiment of the present invention, and FIG. Sectional view of a chip type composite capacitor of a second embodiment of the invention,
Figure is a graph showing the frequency characteristics of impedance of the electrolytic capacitor and ceramic capacitor respectively and the chip type composite capacitor of the present invention. Fig. 5 is a sectional view of the prior art composite capacitor. Fig. 6 is an electrolytic capacitor element. FIG. 3 is a cross-sectional view of a conventional chip-type composite capacitor in which a ceramic capacitor element and a ceramic capacitor element are combined. DESCRIPTION OF SYMBOLS 1 ... Anode terminal, 1a ... Top surface, 1b ... Lower plane part, 1c ... Anode terminal plane part, 2 ... Center protrusion part, 3
...... Electrolytic capacitor element, 3a ...... Electrolytic capacitor, 4
...... Anode lead wire, 5 ... Chip type ceramic capacitor element, 6 ... Electrode part, 7 ... Conductive adhesive, 8 ... Characteristic improving capacitor, 8a, 8b ... Characteristic improving capacitor lead, 9a , 9b ... lead, 10 ...
... sealing member, 11a, 11b ... terminal, 12 ... container.
Claims (1)
有する陽極端子の中央突出部に電解コンデンサ素子より
引き出された陽極引き出しリード線が電気的に接続さ
れ、電極形成の完了したチップ型のセラミックコンデン
サ素子の電極部が前記陽極端子の上面、および電解コン
デンサ素子の上面に重ね合わせて電気的に並列に接続さ
れたことを特徴とするチップ型複合コンデンサ。1. A chip type in which an electrode lead-out wire drawn out from an electrolytic capacitor element is electrically connected to a central protruding portion of an anode terminal having a central protruding portion, an upper flat surface portion and a lower flat surface portion, and electrode formation is completed. 2. The chip-type composite capacitor, wherein the electrode portion of the ceramic capacitor element is superposed on the upper surface of the anode terminal and the upper surface of the electrolytic capacitor element and electrically connected in parallel.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14406388U JPH0621228Y2 (en) | 1988-11-02 | 1988-11-02 | Chip type composite capacitor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14406388U JPH0621228Y2 (en) | 1988-11-02 | 1988-11-02 | Chip type composite capacitor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0265325U JPH0265325U (en) | 1990-05-16 |
JPH0621228Y2 true JPH0621228Y2 (en) | 1994-06-01 |
Family
ID=31411441
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14406388U Expired - Lifetime JPH0621228Y2 (en) | 1988-11-02 | 1988-11-02 | Chip type composite capacitor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0621228Y2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10008340B2 (en) * | 2014-07-17 | 2018-06-26 | Samsung Electro-Mechanics Co., Ltd. | Composite electronic component, board having the same, and power smoother including the same |
-
1988
- 1988-11-02 JP JP14406388U patent/JPH0621228Y2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0265325U (en) | 1990-05-16 |
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