JPH0621024A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make disappear charge stored in an interface between an insulating material and a semiconductor substrate or an insulating material of different dielectric constant and in a film by casting short wavelength light of a specific wavelength after processing by using plasma or ionic species or after a film formation process by plasma CVD method. CONSTITUTION:In this manufacturing method of a semiconductor device having a processing by using plasma or ionic species or a film formation process by plasma CVD method, a process for casting short wavelength light whose wavelength is shorter that of ultraviolet ray is provided after a processing using plasma or ionic species or after a film formation process by plasma CVD method. For example, when an SRAM of a high resistance load type constituting a high resistance load by a three-layer structure of a high resistance polysilicon layer 8, a buffer silicon oxide film 9 and a nitride film 10 is manufactured, short wavelength light is casted without a resist film after a dry etching process or after a film formation process by plasma CVD method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a processing step using plasma or ion species or a film forming step by a plasma CVD method.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device including an integrated circuit using a planar technology has a double structure including an insulating film and a semiconductor substrate, or an insulating film and an insulating film having a dielectric constant different from that of the insulating film. is doing. That is, between the insulator for separating the elements on the semiconductor substrate and the semiconductor substrate, the MIS
Between the gate insulating film and the semiconductor substrate of the field effect transistor, between the gate insulating film and the gate polycide, and the SRA
There are various interfaces in the semiconductor device such as between the polycrystalline silicon and the silicon oxide film of the M high resistance portion, or between the silicon oxide film and the nitride film. When forming a wiring layer or the like of a semiconductor device, a conventional process of etching by using ion species or plasma species such as RIE is used. Further, as a method of forming an oxide film or a nitride film, a method of forming the oxide film or the nitride film by a plasma CVD method utilizing a plasma reaction has been conventionally used.

[0003]

In the conventional method of manufacturing a semiconductor device, as described above, a film-forming process is carried out by dry etching using an ion species such as RIE or a plasma species or a plasma CVD method utilizing a plasma reaction. The process was used. Then, various interfaces such as an interface between the silicon oxide film and the nitride film exist in the semiconductor device.

Here, if the above-mentioned dry etching process or film formation by plasma CVD is performed at the time of forming a semiconductor device, there is a problem that charges are accumulated in the interface and in the film. When electric charges are accumulated on the interface and in the film in this manner, for example, the electrical characteristics of a high-resistance load of SRAM fluctuate, and the leakage current between elements exceeding the element isolation insulating film on the semiconductor substrate increases. Is caused.

That is, conventionally, during dry etching using an ion species or plasma species or film formation by a plasma CVD method, charges are accumulated at the interface between an insulator and a semiconductor substrate or an insulator having a different dielectric constant. There was an inconvenience that it would end up. As a result, it has been difficult to obtain stable and uniform electric characteristics of the semiconductor device.

The present invention has been made in order to solve the above-mentioned problems, and an insulator and a semiconductor substrate are formed by a processing step by dry etching using an ion species or a plasma species or a film forming step by a plasma CVD method. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of eliminating charges accumulated in an interface with an insulator having a different dielectric constant and in a film.

[0007]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a processing step utilizing plasma or ion species, or a film forming step by a plasma CVD method. After processing using ion species or plasma CVD
After the film forming step by the method, there is provided a step of irradiating short-wavelength light having a wavelength shorter than that of ultraviolet rays.

[0008]

In the method of manufacturing a semiconductor device according to the present invention, short-wavelength light having a wavelength shorter than that of ultraviolet rays is irradiated after the processing step using plasma or ion species or the film-forming step by the plasma CVD method. The irradiation of the short-wavelength light effectively eliminates the electric charges accumulated (charged) in the interface between the insulator and the semiconductor substrate or the insulator having a different dielectric constant and in the film.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional structural view for explaining a first embodiment of a method for manufacturing a semiconductor device of the present invention. This first
In the embodiment, the manufacturing method of the present invention is applied to a high resistance load type SRAM having a 3 polysilicon 1 aluminum wiring structure. First, the sectional structure of the SRAM will be described with reference to FIG. In this SRAM, the semiconductor substrate 21
An element isolation film 4 made of a silicon oxide film for element isolation is formed in a predetermined region on the upper main surface. N ⁺ source / drain regions 2 are formed on the main surface of semiconductor substrate 21 at predetermined intervals, and N ⁻ source / drain regions 1 are formed so as to overlap with N ⁺ source / drain 2. . In addition, N ⁻ source / drain regions 1 and N
⁺ N ⁻ contact region 3 is formed so as to overlap with source / drain region 2. A gate electrode having a polycide structure composed of a doped polysilicon film 5 and a tungsten silicide film 6 is formed on a semiconductor substrate 21 between a pair of N ⁻ source / drain regions 1. The gate electrode, N ⁻ source / drain region 1 and N ⁺ source / drain region 2 form an N channel MOS transistor 22.
Is configured. In addition, N ⁻ source / drain regions 1 and N
⁺ N-channel MOS with source / drain region 2
The LDD structure of the transistor is constructed.

An interlayer film 7a made of a silicon oxide film is formed so as to cover the gate electrode made of doped polysilicon film 5 and tungsten silicide film 6. A high resistance polysilicon layer 8 which becomes a high resistance load is electrically connected to the tungsten silicide film 6 through a contact hole of the interlayer film 7a. A buffer silicon oxide film 9 serving as a stress relaxation buffer layer is formed on the high resistance polysilicon layer 8, and the nitride film 1 is formed on the buffer silicon oxide film 9.
0 is formed. An interlayer film 7b made of a silicon oxide film is formed so as to cover the nitride film 10, and a BPSG film 11 is formed on the interlayer film 7b. BPSG film 11
An interlayer film 7c made of a silicon oxide film is formed on the top. Underlay doped polysilicon film 12 is formed so as to be electrically connected to high-resistance polysilicon layer 8 through contact holes formed in interlayer film 7b, BPSG film 11 and interlayer film 7c. An aluminum film 13 is formed on the underlying doped polysilicon film 12. The PSG film 14 is formed so as to cover the entire surface, and the plasma nitride film 15 is formed so as to cover the PSG film.

Here, in the nitride film 10, the resistance value of the high resistance polysilicon layer 8 changes due to the diffusion of phosphorus or boron from the BPSG film 11 and the hydrogen diffusion from the plasma nitride film (P-SIN film) 15. It is provided as a protective film for preventing this. The underlay doped polysilicon film 12 serves as an underlay wiring of the aluminum wiring 13, and plays an effective role in reducing step disconnection and migration failure of aluminum and increasing the surface concentration of the N ⁻ contact region 3.

FIG. 2 is a wiring diagram of a memory cell with a high resistance load formed of the N channel MOS transistor 22 of the SRAM structure and the high resistance polysilicon layer 8 shown in FIG. Referring to FIG. 2, in order to increase the capacity of SRAM, it is necessary to reduce the quiescent current of each memory cell. At present, a high resistance load is required to have a resistance value of 1 GΩ or more. Along with this, in order to prevent the write data from being lost due to the cutoff current of the transistor and the leak current between the elements, the PA value lower than the current value flowing through the high resistance by about two orders of magnitude.
Cut-off current values and leak current values on the order of (pico amps) are required. Here, in the structure shown in FIG. 1, a stable and high resistance value of 1 GΩ or higher is obtained by the high resistance polysilicon layer 8, the buffer silicon oxide film 9 and the nitride film 10.
This is achieved by the three-layer structure of

FIG. 3 is an energy band diagram when a high resistance load is formed by the three-layer structure including the high resistance polysilicon layer 8, the buffer silicon oxide film 9 and the nitride film 10 shown in FIG. Referring to FIG. 3, nitride film 10 sandwiched between buffer silicon oxide film 9 and silicon oxide film 7 serves as a well. For this reason, the nitride film 10 is easily charged with electric charges during dry etching using plasma species or ion species or during film formation by the plasma CVD method. When the nitride film 10 is charged with electric charges, the surface layer of the high resistance polysilicon layer 8 is inverted or the electric charges are accumulated, so that the resistance value is lowered.

Therefore, in the present invention, short wavelength light having a wavelength equal to or shorter than the wavelength of ultraviolet rays is irradiated without a resist film after the dry etching step or the film forming step by the plasma CVD method. As a result, it is possible to eliminate the electric charge charged in the nitride film 10. As a result, a stable and high resistance value can be obtained.

The following method is adopted in order to increase the efficiency of charge loss during irradiation of short wavelength light according to the present invention.
That is, the back surface of the semiconductor substrate 22 is etched before the short-wavelength light is irradiated, and then the short-wavelength light is irradiated in the state where the charges are applied to the semiconductor substrate 22. In addition, the semiconductor substrate 2
Irradiation with short-wavelength light may be performed in a state where 2 is heated.
Further, short-wavelength light may be radiated in the form of applying voltage to the substrate and heating the substrate in combination. By irradiating the short wavelength light in this manner, rearrangement of charges occurs. As a result, the excess charge region is eliminated, and the charge at the interface between the semiconductor substrate 21 and the silicon oxide film (inter-element isolation film) 4 is also stabilized, and the inter-element leakage current can be effectively reduced.

FIG. 4 is a sectional structural view for explaining a second embodiment of the semiconductor device manufacturing method of the present invention. The second embodiment is an example in which the manufacturing method of the present invention is applied to BICMOS. Referring to FIG. 4, first in this BICMOS, an N-type semiconductor layer 48 is formed on a P-type substrate 46 by epitaxial growth. N-type semiconductor layer 48
A P well 47 is formed in a predetermined area of. In the P well 47, N ⁻ source / drain regions 31 are formed at a predetermined interval, and the N ⁺ source / drain regions 32 are overlapped with the N ⁻ source / drain regions 31.
Are formed. A pair of N ^- source / drain regions 3
The doped polysilicon film 35 is formed on the P well 47 between the two.
Further, a gate electrode having a polycide structure made of the tungsten silicide film 36 is formed. The gate electrode, N ⁻ source / drain region 31 and N ⁺ source / drain region 32 form an N channel MOS transistor. An element isolation film 34 is formed so as to surround the N channel MOS transistor.

A collector 49 is formed at the boundary between the N type semiconductor layer 48 and the P type substrate 46. An external base 50 and an intrinsic base 5 are formed on the main surface of the N-type semiconductor layer 48.
2 and the emitter 51 are formed. The collector 49, the external base 50, the intrinsic base 52 and the emitter 51 form an NPN bipolar transistor. N ⁻ source / drain region 31, external base 5
An aluminum film 43 is connected to each of 0 and the collector 49. An aluminum film 43 is electrically connected to the emitter 51 via a polysilicon layer 53. An interlayer film 37 made of a silicon oxide film which covers the entire surface and has contact holes at predetermined positions is formed. A polysilicon layer 54 forming a resistance region is formed on the interlayer film 37 located above the boundary region between the N-type semiconductor layer 48 and the P well 47. Polysilicon layers 53 and 54
A buffer silicon oxide film 55 is formed so as to cover the. A nitride film 40 is formed on the interlayer film 37 including the buffer silicon oxide film 55 and the silicon oxide film. The nitride film 40 has a low impurity concentration (the intrinsic base region 5).
2. It functions as a protective film for preventing diffusion of phosphorus and boron into the polysilicon layer 54) in the resistance region. Therefore, in the region of the polysilicon layer 54 in the resistance region and the polysilicon layer 53 on the intrinsic base region 52, the three-layer structure shown in FIG. 3 is formed. Therefore, the nitride film 40 in this region is likely to be electrically charged during dry etching using plasma species or ionic species or during formation of a plasma CVD film. When the nitride film 40 in this region is electrically charged, the surface layers of the polysilicon layers 53 and 54 are inverted or the charges are accumulated, so that the characteristics change.

Therefore, also in the manufacturing method of the second embodiment, short-wavelength light having a wavelength equal to or shorter than the wavelength of ultraviolet rays is used after the dry etching step or the film forming step by the plasma CVD method as in the first embodiment. Irradiate without. As a result, it is possible to eliminate the electric charges charged in the nitride film 40, and as a result, it is possible to prevent variations in the characteristics of the element and easily manufacture a semiconductor device having stable and uniform electrical characteristics.

[0020]

As described above, according to the present invention, short-wavelength light having a wavelength shorter than that of ultraviolet rays is irradiated after the processing step using plasma or ion species or the film-forming step by the plasma CVD method. As a result, the electric charge accumulated by the processing process using plasma or ion species or the film formation process by the plasma CVD method is lost, so that the characteristic value variation of each element is effectively prevented and, as a result, stable and uniform characteristics are obtained. A semiconductor device having the semiconductor device can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a sectional view of an SRAM structure for explaining a first embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a wiring diagram of a memory cell of an SRAM including an N-channel MOS transistor and a high resistance load shown in FIG.

FIG. 3 is an energy band diagram when a high resistance load is created by a three-layer structure including a high resistance polysilicon layer, a buffer silicon oxide film and a nitride film.

FIG. 4 is a sectional view of a BICMOS structure for explaining a second embodiment of the method for manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

1: N ⁻ source / drain region 2: N ⁺ source / drain region 3: N ⁻ contact region 4: silicon oxide film (element isolation film) 5: doped polysilicon film 6: tungsten silicide film 7: silicon oxide film (Interlayer film) 8: High resistance polysilicon layer 9: Buffer silicon oxide film 10: Nitride film 11: BPSG film 12: Underlay doped polysilicon film 13: Aluminum film 14: PSG film 15: Plasma nitride film 46: P type Substrate 47: P-well 48: N-type silicon layer 49: Collector 50: External base region 51: Emitter region 52: Intrinsic base region

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device comprising a processing step using plasma or ion species, or a film forming step by plasma CVD method, which is performed after the processing step using plasma or ion species or by plasma CVD method. A method of manufacturing a semiconductor device, comprising a step of irradiating short wavelength light having a wavelength shorter than that of ultraviolet rays after the film forming step.