JPH0620995A - Semiconductor device and production thereof - Google Patents

Abstract

PURPOSE:To improve the performance of a semiconductor device by preventing the deterioration of yield and reliability due to wiring disconnection by the step on the side surface of a contact hole and increasing the contact area of the contact hole. CONSTITUTION:A contact hole 6 for electrically connecting a diffused layer 2A formed on a silicon substrate 1 with a wiring layer is formed on a second BPSG film 3B, a CVD oxide film 5 and a first BPSG film 3A and a polycrystal silicon film side wall 7 is formed on the side surface of the contact hole 6. Then, a Ti-TiN film 8 and an Al film 9 are formed as the top layer wiring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a connection hole for connecting a diffusion layer and a wiring.

[0002]

2. Description of the Related Art In semiconductor devices, the miniaturization of elements, wirings, etc. is rapidly advancing along with the recent high integration.
With the progress of miniaturization of elements and wirings, the area of the connection hole for connecting the diffusion layer of the semiconductor substrate and the wiring is rapidly decreasing in proportion to the square of the reduction rate.

FIG. 2 shows a connection hole which is commonly used at present.
The cross-sectional structure is as shown in. First, the N-type diffusion layer 2 is formed on the P-type silicon substrate 1 by using the photolithography technique and the ion implantation technique. After that, a first BPSG film 3A to be an interlayer insulating film is formed by a CVD method, and a lower layer wiring 4 made of a polycrystalline silicon film or a refractory metal silicide film is formed thereon by a CVD technique or a sputtering technique,
It is formed by using photolithography technology and etching technology. After that, an oxide film (CV) is formed by the CVD method for preventing outward diffusion of phosphorus and boron from the second BPSG film 3B.
After the D oxide film) 5 is deposited, the second BPSG film 3B is deposited thereon by the CVD method.

After that, a connection hole 6A is formed by wet etching and anisotropic dry etching for connecting the upper wiring and the N-type diffusion layer 2. Next, impurities are ion-implanted into the inside of the contact hole in order to lower the connection resistance and prevent leakage current. At this time, in order to prevent damage to the substrate surface inside the contact hole, the activity of the injected ions is also reduced. A thin oxide film (not shown) is formed by the CVD technique to prevent outward diffusion of phosphorus and boron from the first and second BPSG films 3A and 3B during the heat treatment for conversion. Then, according to the above purpose, ion implantation and heat treatment are performed.

Next, in order to remove the thin oxide film, wet etching is performed with a fluorine-based etching solution. After that, a Ti—TiN film 8 and an Al film 9 containing Si and Cu are formed as an upper metal wiring film by a sputtering technique, a photolithography technique, and an etching technique.

[0006]

In this conventional method for manufacturing a contact hole, the sidewall of the contact hole is simultaneously removed when the thin oxide film deposited before the ion implantation into the inside of the contact hole is removed by wet etching. It will be etched. At this time, the sidewall of the contact hole is covered with the first BPSG film 3 as an interlayer insulating film.
A, the CVD oxide film 5 and the second BPSG film 3B are formed, but since the etching rate of each film with the wet etching solution is different, a step is formed on the sidewall of the connection hole at the end of the wet etching. Therefore, there is a problem that the metal material for the upper layer wiring, that is, the Ti—TiN film 8 and the Al film 9 is cut inside the connection hole, and the yield of the semiconductor device is reduced or the reliability is deteriorated. Further, due to the decrease in the area of the connection hole, the voltage drop due to the increase in the resistance of the conductor in the connection hole causes a problem that the power supply voltage margin is deteriorated and the speed characteristic is deteriorated.

[0007]

A semiconductor device according to a first aspect of the present invention comprises a diffusion layer formed on the surface of a semiconductor substrate, a plurality of interlayer insulating films formed on the diffusion layer and having different etching rates, and the interlayer insulating film. The insulating film and the diffusion layer include a connection hole formed by digging a part of the diffusion layer, and a sidewall made of a polycrystalline silicon film formed on a side surface of the connection hole.

A method of manufacturing a semiconductor device according to a second aspect of the present invention includes a step of forming a diffusion layer on the surface of a semiconductor substrate, and a step of forming a plurality of interlayer insulating films having different etching rates on the entire surface including the diffusion layer, The step of etching the surface of the interlayer insulating film and the diffusion layer to form a contact hole, and the step of forming a polycrystalline silicon film on the entire surface and then etching to form a sidewall made of a polycrystalline silicon film on the side surface of the contact hole. And a process.

[0009]

The present invention will be described below with reference to the drawings. 1A to 1C are sectional views of a semiconductor chip for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, a first N-type diffusion layer 2A is formed on a P-type silicon substrate 1 by a photolithography technique and an ion implantation technique. After that, a first BPSG film is formed as an interlayer insulating film with a thickness of 400 n using the CVD method.
After being formed to a thickness of m, a lower layer wiring 4 made of a polycrystalline silicon film, a refractory metal silicide film or the like is formed thereon. After that, a CVD oxide film 5 is deposited to 100 nm to prevent outward diffusion of phosphorus and boron from the second BPSG film, and then a second BPSG film 3B is formed by the CVD method.

After this, the connection hole 6 is formed by the photolithography technique. In this case, first, wet etching is performed to 200 nm with a hydrofluoric acid-based etching solution, and then the oxide film is etched to the semiconductor substrate by anisotropic etching with a CF ₄ -based etching gas. Then, anisotropic dry etching is performed with an SF ₆ / Cl ₂ -based etching gas to dig down the silicon substrate to a depth of 200 n.
The groove 10 of m is formed.

Next, as shown in FIG. 1 (b), P is ion-implanted to reduce the resistance of the connection resistance and the leakage current, so that 60 kev is obtained at the self-alignment and the dose amount is 5 ×.
The second N-type diffusion layer 3B is formed by injecting so as to inject into the sidewall of the connection hole of the silicon substrate at an inclination of 10 ¹⁵ / m ² and 7 °. After that, polycrystalline silicon is formed to a thickness of 200 nm by the CVD method, and then HBr / Cl _{2 is} added.
Anisotropic dry etch back processing is performed using a system etching gas to form the sidewalls 7 of the polycrystalline silicon film on the side surfaces of the connection holes 6. Thereafter, in order to improve the shape of the connection hole, heat treatment is performed at 900 ° C. for 15 minutes in a nitrogen atmosphere. At this time, since a small amount of oxide film grows, wet etching is performed for 15 seconds with a hydrofluoric acid-based etching solution.

Next, as shown in FIG. 1 (c), a Ti-TiN film 8 (Ti film 60 nm, TiN film 100 nm) to be an upper wiring is deposited by a sputtering method, and a high speed heat treatment is performed to form a Ti film. Silicide. Next, after depositing an Al film 9 containing Si and Cu to a thickness of 600 nm, patterning is performed using the photolithography technique.

As described above, according to this embodiment, since the sidewall is formed on the side surface of the contact hole and then the heat treatment is performed, the formed oxide film is removed by the wet etching method.
No step is formed on the side surface of the connection hole. Therefore, the upper layer wiring is not cut.

In the above embodiment, the side wall 7 made of a polycrystalline silicon film was formed after P was ion-implanted. However, the side wall 7 may be formed and then ion-implanted. In this case, since the sidewall 7 is made more conductive by the ion implantation, the connection resistance can be further reduced.

[0016]

As described above, according to the present invention, since the sidewall of the polycrystalline silicon film is formed on the side surface of the contact hole, the heat treatment for improving the shape of the contact hole is performed. At times, no step is formed on the side walls of the connection holes formed in the plurality of interlayer insulating films having different etching rates. In addition, even in the step portion of the side wall of the connection hole caused by other cleaning, the side wall is formed to prevent the wiring in the upper layer from being cut off inside the connection hole. It also has the effect of improving reliability.

Further, since the connection hole is formed by digging down to the surface of the semiconductor substrate, the contact area of the connection portion becomes large, and the connection resistance can be made smaller than that of the connection hole of the same size, improving the power supply voltage margin, It also has the effect of improving speed derivation.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2A, 2B N-type diffusion layer 3A, 3B BPSG film 4 Lower layer wiring 5 CVD oxide film 6, 6A Connection hole 7 Sidewall 8 Ti-TiN film 9 Al film 10 Groove

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 21/306 S 9278-4M 21/3205 21/90 C 7514-4M

Claims (2)

[Claims] 1. A diffusion layer formed on the surface of a semiconductor substrate,
A plurality of interlayer insulating films formed on the diffusion layer and having different etching rates, a connection hole formed by digging a part of the interlayer insulating film and the diffusion layer, and a multi-hole formed on the side surface of the connection hole. A semiconductor device comprising a sidewall made of a crystalline silicon film. 2. A step of forming a diffusion layer on a surface of a semiconductor substrate, a step of forming a plurality of interlayer insulating films having different etching rates on the entire surface including the diffusion layer, and a surface of the interlayer insulating film and the diffusion layer. And forming a contact hole, and forming a polycrystalline silicon film on the entire surface and then etching to form a side wall made of a polycrystalline silicon film on the side surface of the contact hole. Device manufacturing method.