JPH06208939A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device in which a large scale integrated circuit can be realized by enlarging the chip using current process at low cost while avoiding difficult technology and abrupt increase of investment. CONSTITUTION:In the structure of a semiconductor device for increasing the memory capacity, an amorphous silicon layer 2 for relaxing mechanical stress is formed partially on a substrate 1 for constituting a chip, a single crystal silicon layer 3 is formed thereon, and a desired element is formed on the single crystal silicon layer 3. Consequently, a device structure similar to that of previous generation can be employed without decreasing the design rule abruptly and the mechanical stress of enlarged chip is suppressed by the amorphous silicon layer 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a large chip for realizing a large scale integrated circuit.

[0002]

^2. Description of the Related Art DRAM, E ² In a semiconductor memory device represented by a PROM or the like, an increase in storage capacity due to miniaturization and high integration of elements is the most important issue. Is facing a critical situation due to its rapid growth.

Regarding the difficulty of the technology, for example, while the processing technology such as lithography and etching has entered the area of the design rule of 0.25 μm, its precision and controllability have many technical problems. . In the future, further reduction of design rules will bring enormous technical problems and the feasibility is being reduced. Further, due to the complicated device structure, introduction of increasingly expensive new process technology is required, and the difficulty of controllability of the process technology is increasing.

On the other hand, the rapid increase in investment includes, for example, a significant increase in the number of processes, an increase in new expensive processes and machines, and an increase in development investment.

[0005]

As described above, the conventional semiconductor memory device faces a critical situation due to the rapid difficulty of technology for increasing the storage capacity and the rapid increase of investment. Further, the above problem can be similarly applied to a semiconductor device in which a large scale integrated circuit is formed on one chip.

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to realize a large-scale integrated circuit by increasing the size of a chip by using the current process, which is a rapid technical change. An object of the present invention is to provide a semiconductor device which can be manufactured at low cost while avoiding difficulty and a rapid increase in investment.

[0007]

The gist of the present invention does not sharply reduce the design rules, but uses the same device structure as in the previous generation and instead suppresses the mechanical stress of the increased chip. In order to do so, the stress relieving member is used.

That is, according to the present invention, in a semiconductor device for realizing a large-scale integrated circuit, a stress relief member for relieving mechanical stress is provided on a part of a chip on which a desired element is formed. . Here, preferable embodiments of the present invention include the following (1) to (9). (1) The stress relieving member is formed by being embedded in the substrate forming the chip.

(2) A plurality of stress relaxation members are formed in parallel with the substrate forming the chip. Further, the chip is bent at the portion where the stress relaxation member is formed. (3) The stress relieving member is formed in a grid pattern on the substrate forming the chip. (4) The substrate material itself constituting the chip is formed of a stress relieving member. (5) Stacking a plurality of chips on which a stress relaxation member is formed. (6) The stress relieving member is composed of amorphous silicon. (7) The stress relaxation member is composed of an organic semiconductor. (8) Part of the wiring layer (especially wiring that crosses the stress relief member)
Is made of a material that is soft and resistant to stress (eg, aluminum). (9) Loosen the design rules and have a device structure before the previous generation.

[0010]

As described above, the increase in storage capacity of semiconductor memory devices and the like currently depends on the reduction of design rules. The present invention has an opposite idea, and intends to increase the memory capacity and the like by increasing the chip area without changing the design rule. Here, simply increasing the size of the chip may increase the influence of mechanical stress, and some elements may not function or the chip may be damaged, resulting in a defective product. Therefore, in the present invention, a stress relieving member such as amorphous silicon is provided on a part of the chip to absorb and relieve the mechanical stress.

Therefore, according to the present invention, since the design rule is not reduced and the device structure similar to that of the previous generation is used with a large chip, a cheap and simple process and a cheap machine can be used. It is possible to effectively suppress the difficulty of the investment and the increase of the investment. Further, since the stress relieving member is provided in a part thereof, it is possible to relieve the mechanical stress of the enlarged chip and prevent the chip from becoming a defective product.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. <Embodiment 1> FIG. 1 is a sectional view of a cell array portion of an embodiment when the present invention is applied to a DRAM, and FIG. 2 is a sectional conceptual view of the entire chip.

As shown in FIG. 1, a metal substrate such as stainless steel, ceramics, a glass substrate, or a laminated body of these is used as the substrate 1, and an amorphous silicon layer 2 is formed thereon as a stress relaxation member. A part of the amorphous silicon layer 2 is single-crystallized as required to form a single-crystal silicon layer 3. Then, on the single crystal silicon layer 3, the field shield electrode 4, the diffusion layer 5, the capacitor insulating film 6, the plate electrode 7,
A desired element is formed by forming the gate insulating film 8, the gate electrode 9, the diffusion layer 10, the bit line 11 and the like.

Further, as shown in FIG. 2, the single crystal silicon layer 3 is partially formed, and in the boundary region between the cell array and the periphery or the core circuit, only the amorphous silicon layer 2 constitutes a stress relaxation portion. ing. In this boundary region, the wiring layer is not formed of the hard wiring 12, but is formed of the wiring 13 made of a material that is soft and resistant to mechanical stress (for example, aluminum).

With this structure, the mechanical stress applied to the chip is absorbed or alleviated by the amorphous silicon layer 2 embedded in the chip.
The mechanical stress applied to each cell formed in the single crystal silicon layer 3 separated by the amorphous silicon layer 2 is extremely small. Further, since the wiring layer straddling the exposed amorphous silicon layer 3, that is, the wiring layer to which a large mechanical stress is applied is formed by the wiring 13 such as aluminum which is strong against the mechanical stress, there is a problem such as disconnection of the wiring layer. It can be prevented. Therefore, even if the size of the chip is increased, it is possible to prevent the occurrence of defects due to mechanical stress in each cell.

As shown in FIG. 1, the cell structure of this embodiment is a structure before the previous generation, specifically, a planar capacitor type one transistor / transistor similar to a 1M bit DRAM.
It is a one-capacitor structure. This simple structure allows the use of cheap and simple processes and machines, and reduces technological difficulties and increased investment. In other words, avoiding the difficulty of technology and the increase of investment, low cost and large capacity DR
AM can be realized. <Example 2>

FIG. 3 shows a NAND type E ^{2 according} to the present invention. PROM
3 is a cross-sectional view of a cell array portion of the example applied to FIG. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The structure of the chip is similar to that of the first embodiment, and the amorphous silicon layer 2 is formed on the substrate 1,
The single crystal silicon layer 3 is formed in a part thereof. A memory cell array is formed on the single crystal silicon layer 3. In the figure, 14 is a floating gate electrode, 15 is a selection gate electrode, 16 is a control gate electrode, and 17 is an element isolation insulating film. Although not shown in the sectional view of FIG. 3, the single crystal silicon layer 3 is separated by the amorphous silicon layer 2 as in the example of FIG.

Even with such a structure, the mechanical stress can be absorbed or relieved by the amorphous silicon layer 2 as in the first embodiment, and the occurrence of cell defects due to the mechanical stress is caused. Instead, it can be made into a large chip. Therefore, avoiding the difficulty of technology and the increase of investment, E ² of large capacity at low cost can be obtained. A PROM can be realized. <Example 3>

FIG. 4 shows an example of a multi-chip layout. The memory chips formed in the first and second embodiments can be made thin like paper and have a large area. Furthermore, the chip itself is resistant to mechanical stress. Therefore, as shown in FIG. 4, by stacking a plurality of sheets on top of each other, the degree of integration can be further increased. At this time, the pins are collectively arranged on the side surface, and signals can be input and output from there. <Example 4>

FIG. 5 shows a modified chip-shaped embodiment. When a metal or a divided ceramic or a laminated structure of glass and metal is used for the substrate, the chip can be largely deformed by inserting the stress relaxation portion.

Specifically, as shown in FIG. 5 (b), a plurality of stress relaxation members 1 are arranged in parallel with the chip itself at regular intervals.
By forming 9, the chip can be folded back and forth as shown in FIG. As a result, it is possible to greatly improve the mounting density when viewed in plan. <Example 5>

FIG. 6 shows another embodiment of the modified tip shape. When a metal or a divided ceramic or a laminated structure of glass and metal is used for the substrate, the chip can be largely deformed by inserting the stress relaxation portion.

Specifically, as shown in FIG. 6B, a plurality of stress relieving members 19 are formed in parallel with the chip itself so that the chip is spirally folded as shown in FIG. 6A. be able to.

The stress relieving member 19 arranged to relieve the mechanical stress may be arranged in any other manner. For example, as shown in FIG. 7, they may be arranged in a grid pattern (lattice pattern). In this case, the bending direction of the chip is not limited to one, and the chip can be bent in either the short side direction or the long side direction as necessary. <Embodiment 6> FIGS. 8 to 12 are process sectional views of the embodiment of FIG.

First, a metal as shown in FIG.
A substrate 1 made of ceramics, glass, or a laminated body of these is prepared, a single crystal silicon layer 18 is attached thereon, and patterned by RIE or the like. A direct wafer bonding technique may be used to attach the single crystal silicon layer 18.

Next, as shown in FIG. 8B, the substrate 1
Further, the amorphous silicon layer 2 is deposited on the entire surface of the single crystal silicon layer 18 by the plasma CVD method or the photo CVD method and is planarized by polishing or the like. At this time, the upper end of the single crystal silicon layer 18 is exposed, or the recrystallized layer is formed in the subsequent recrystallization process of amorphous silicon.
The amorphous silicon layer 2 is polished to such a degree that it comes into contact with the upper end of the.

Next, as shown in FIG. 8C, a part of the amorphous silicon layer 2 is recrystallized by irradiation with a laser beam, an electron beam or the like to form a single crystal silicon layer 3. . At this time, a good quality single crystal can be obtained by using the single crystal silicon layer 18 as a seed for recrystallization.

Then, as shown in FIG. 9A, a field shield electrode 4 is formed on the entire surface of the substrate with an oxide film interposed therebetween to form an element isolation region. Subsequently, the diffusion layer region 5, the capacitor insulating film 6 and the plate electrode 7 are formed to realize a memory cell capacitor.

Next, as shown in FIG. 9B, the word line 9 and the element region diffusion layer 10 are formed, and the bit line 11 is further processed through the contact to form the DRA.
M cells are realized. And if necessary, word 9
A wire shunt is performed with two layers of Al or the like.

As described above, in the case of the present embodiment, the cell structure has a planar type and a simple structure, can be formed by an extremely simple and inexpensive process and manufacturing apparatus, and the manufacturing cost can be greatly reduced.

Further, even if the quality of the amorphous silicon or crystallized silicon layer 3 is somewhat poor, it does not affect the operation because a large storage capacity can be obtained. Further, since a large chip area can be taken, redundant circuits can be applied to the cell portion, core portion, peripheral circuit portion, etc., an ECC circuit can be attached, and a refresh operation can be performed before the accumulated charge leaks. When metal is used even for a part of the substrate, the heat dissipation during operation is increased, which is effective. Also, the metal of this substrate can be used as a power line or wiring.

FIG. 10 shows the present invention in which an A4 size chip size DRAM and E ^{2 are used.} It shows the number of memory bits when applied to a PROM, the horizontal axis is the design rule, and the vertical axis is the number of memory bits. From this figure, it is possible to realize a 1.2 Gbit DRAM by using a flat cell with the design rule of IMDRAM of 1.2 μm. This is the capacity to store a moving image for 8 minutes.

Further, the NAND type E ^{2 is used} under the same design rule. If you make a PROM, you can store 13 minutes of moving images on a 2 Gbit scale. Further, assuming a rule of 0.25 μm, one A4 size NAND type E ² In case of PROM,
You can memorize as many as 12 hours of moving images. <Example 7>

Although amorphous silicon is used as the stress relieving member in the above-mentioned embodiments, an organic semiconductor, which has recently been receiving attention, may be used. In the case of this embodiment, as shown in FIG. 11, it is applied to a DRAM, but polythienylenevinylene (PTV) or the like is used as the organic semiconductor in the uppermost layer.

Specifically, the bit line is formed on the substrate 1, the SiOx film 21, the plate electrode 7, and the gate electrode 9 are formed thereon, and the SiOx film 21 is flattened. Then, the tungsten film 22 is buried in the contact hole formed in the SiOx film 21, and a PTV film as the organic semiconductor film 23 is formed on the SiOx film 21 and the tungsten film 22.

With such a structure, the organic semiconductor film 2
3 functions as a stress relieving member, and as in the first embodiment, the occurrence of defects due to mechanical stress can be suppressed in advance. Here, in the configuration of FIG. 11, the same effect can be obtained even if an amorphous silicon film is used instead of the organic semiconductor film 23.

The present invention is not limited to the above embodiments. In the embodiment, DRAM and NAND type E ² Although an example of application to a PROM is shown, it can be applied to all other LSIs or ICs, and can also be applied to an SRAM or the like using amorphous silicon.
Furthermore, these embedded memories can be made. Further, mixed mounting with a logic such as a microprocessor and gate array, mixed mounting with an image pickup device such as CCD, further mixed mounting with a liquid crystal display device, and mixed mounting with a solar cell are possible. In addition, various modifications can be made without departing from the scope of the present invention.

[0039]

As described above, according to the present invention, the stress relief member for relieving the mechanical stress is provided in a part of the chip. Therefore, the design rule is not sharply reduced and the stress is less than that of the previous generation. A similar device structure can be used instead to suppress the mechanical stress on the enlarged chip. Therefore, it is possible to realize a large-scale integrated circuit by increasing the size of a chip by using the current process, and to realize a semiconductor device that can be manufactured at low cost while avoiding the rapid difficulty of technology and the rapid increase of investment. Is possible.

[Brief description of drawings]

FIG. 1 is a sectional view showing the configuration of a cell array section of a first embodiment in which the present invention is applied to a DRAM.

FIG. 2 is a sectional view showing the overall structure of the chip of the first embodiment.

FIG. 3 illustrates the present invention in NANDE ² Second applied to PROM
3 is a cross-sectional view showing the configuration of the cell array section of the embodiment of FIG.

FIG. 4 is a diagram showing an example of a multilayer chip layout according to the third embodiment of the present invention.

FIG. 5 is a diagram showing an example of a modified tip shape according to the fourth embodiment of the present invention.

FIG. 6 is a view showing another example of the modified tip shape according to the fifth embodiment of the present invention.

FIG. 7 is a view showing another arrangement example of the stress relieving material.

8 is a view showing the first half of the manufacturing process of the embodiment in FIG.

9 is a diagram showing the latter half of the manufacturing process of the embodiment in FIG.

FIG. 10 is a diagram showing a relationship between the number of bits and the number of bytes and a design rule.

FIG. 11 is a diagram showing another example in which the present invention is applied to a DRAM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate (metal, ceramic, glass, or laminated body thereof) 2 ... Amorphous silicon layer 3 ... Single crystal Si or amorphous silicon layer 4 ... Field shield electrode 5 ... Diffusion layer 6 ... Capacitor insulating film 7 ... Plate electrode 8 ... Gate insulating film 9 ... Gate electrode 10 ... Diffusion layer 11 ... Bit line 12 ... Hard wiring (wiring vulnerable to stress) 13 ... Soft wiring (material resistant to stress) 14 ... Floating gate electrode 15 ... Select gate electrode 16 ... Control gate Electrode 17 ... Element isolation 18 ... Silicon layer 19 ... Stress relaxation member 20 ... Pin 21 ... SiOx film 22 ... Tungsten film 23 ... Amorphous silicon or organic semiconductor film

Claims (1)

[Claims] 1. A semiconductor device, wherein a part of a chip on which a desired element is formed is formed of a stress relieving member for relieving mechanical stress.