JPH06208506A - Extended storage controller - Google Patents

Abstract

PURPOSE:To increase the throughputs of individual data processing parts and to improve the performance of the whole system by the controller which control data transfer between a main storage device and an extended storage device by plural data processing parts. CONSTITUTION:The data processing parts 1a-1c are provided with start factor display means 3a-3c which displays whether or not there is start indication information in start queues 2a-2c and also provided with a start acceptability display part 6 which determines which data processing part is permitted to control data transfer. This start acceptability display part 6 is provided with order display circuits 61-63 which display permission order corresponding to the respective data processing parts and also provided with a selecting circuit 64 which selects the data processing part having the top priority; and the data processing part selected by the selecting circuit 64 is allowed to perform data transfer control once current data transfer ends.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an extended storage control device for controlling data transfer between a main storage device and an extended storage device, and more particularly to control of data transfer activation according to activation instruction information generated by a data processing section. The present invention relates to an extended storage control device for performing.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional extended storage control device of this type, in which 1a and 1b are data processing units and 2a and 2 are shown.
Reference numeral b is a boot wait queue, 4a and 4b are boot instruction information reading units, 5 is a data transfer circuit, 7 is a main storage device, 8 is an extended storage device, 10a and 10b are inquiry units, and 11 is a transfer status display unit.

The activation waiting queues 2a and 2b store activation instruction information for activating data transfer between the main storage device 7 and the extended storage device 8, and the activation instruction information reading units 4a and 4b. , Start waiting queue 2a,
The activation instruction information read from 2b is guided to the data transfer circuit 5.

The data transfer circuit 5 transfers data between the main storage device 7 and the extended storage device 8 in accordance with the start instruction information received from the start instruction information reading units 4a and 4b, and displays the transfer status after the transfer is completed. The transfer status display unit 11 is a circuit that sends a transfer end signal to the unit 11. The transfer status display unit 11 displays the operation status of the data transfer circuit 5, that is, “transfer is possible” or “transfer is in progress”.
Is displayed. In addition, the inquiry unit 10a,
10b inquires the transfer status display unit 11 about the data transfer status, and when "transfer is possible", the startup instruction information reading unit 4a,
4b is permitted.

Now, when the activation instruction information is stored in the activation waiting queues 2a and 2b, the inquiry units 10a and 10b first inquire of the transfer status display unit 11 about the data transfer status. As a result, when "transfer is possible", the transfer status display unit 11 notifies the inquiring units 10a and 10a.
Report to b. Inquiry section 10a receiving this report,
10b instructs the activation instruction information reading units 4a and 4b to guide the activation instruction information extracted from the activation waiting queues 2a and 2b to the data transfer circuit 5. At this time, the display of the transfer status display unit 11 is changed from "transferable" to "transferring".

On the other hand, when the inquiry units 10a and 10b inquire about the transfer status and the result is "transferring", the transfer status display unit 11 reports the fact to the inquiry units 10a and 10b. As a result, the inquiry units 10a, 10
After that, b continues to make an inquiry to the transfer status display unit 11 until the transfer status is displayed as "transfer enabled", and when the transfer status is displayed, the above operation is performed.

The data transfer circuit 5, which has received the start instruction information from the start instruction information reading units 4a and 4b, transfers data between the main storage device 7 and the extended storage device 8 in accordance with the start instruction information. Then, when the data transfer is completed, a transfer end signal is sent to the transfer status display unit 11. Upon receiving the transfer end signal, the transfer status display unit 11 changes the display of the data transfer status from "transferring" to "transferable".

Incidentally, FIG. 3 shows two data processing units 1a and 1a.
Although the example of b has been described, the same operation is performed in the case of three or more data processing units.

[0009]

In the conventional extended storage control device having the above-mentioned configuration, when the display of the transfer status display section 11 is "transferring", the data processing sections 1a and 1b instruct the data transfer circuit 5 to start up. I cannot give you information. Therefore, if a conflict with another data processing unit occurs, the data processing unit must inquire many times and monitor the current data transfer state until the display of the transfer status display unit 11 becomes “transferable”. In addition, there is a problem that the processing efficiency of the entire data transfer system decreases.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an extended storage control device which improves the processing efficiency of a data transfer system.

[0011]

An extended storage control device of the present invention that achieves the above object generates and outputs data transfer control between a main storage device and an extended storage device from any one of a plurality of data processing units. A data transfer circuit that executes the data transfer control upon receipt of the start instruction information and outputs a transfer end signal at each transfer end, and the data of the start instruction information. Each data processing unit has a reception control unit that controls reception to the transfer circuit, each data processing unit generates a start instruction information generating unit, a start waiting queue that stores the start instruction information, and this start A start factor display section that displays a start factor when the start instruction information is stored in the waiting queue, and a self-starting unit according to a reception instruction sent from the reception control means while the start factor is being displayed. And a start instruction information reading section for reading the start instruction information stored in the start waiting queue of the data transfer circuit and guiding the start instruction information to the data transfer circuit. The selection circuit is provided corresponding to the processing unit, and includes a selection circuit that selects the display order of each of the order display circuits at the earliest, and is selected by the selection circuit when the transfer end signal is received from the data transfer circuit. The reception instruction is output to the data processing unit corresponding to the counting means.

The selection circuit causes the rank display circuit corresponding to the data transfer processing unit that controls the data transfer to display the last rank in sequence when the data transfer currently being executed is completed.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an extended storage control device according to an embodiment of the present invention. Since this embodiment is an improvement of the conventional device, parts having the same functions as those of the conventional device are designated by the same reference numerals, the description thereof will be omitted, and different parts will be mainly described.

Referring to FIG. 1, three data processing units 1a-1c are connected to the data transfer circuit 5. Each of the data processing units 1a to 1c has a conventional inquiry unit 10a, 1c.
Instead of 0b, it has the activation factor display sections 3a to 3c for displaying the presence or absence of the activation instruction information in its own activation waiting queue, that is, the presence or absence of the activation factor, and when the activation instruction information exists, the activation is performed. The factor “present” is displayed, and the fact is reported to the activation acceptance possible display unit (acceptance control means) 6 described later.

The start acceptability display section 6 includes a data transfer circuit 5
In each data processing unit 1a to
1c, and when the plurality of data processing units 1a to 1c have activation instruction information, which data processing unit 1a to 1c is to be activated is determined. .

The start acceptability display unit 6 is, specifically,
The data processing units 1a to 1c are provided with order display circuits 61, 62 and 63 respectively provided correspondingly, and one selection circuit 64.

Each of the order display circuits 61 to 63 displays the order in which the activation can be accepted. In the initial state,
Arbitrary numerical values different from each other are displayed.

The selection circuit 64 lowers the rank of the data processing unit controlling the data transfer to the last (lowest) when the data transfer currently being executed is completed, and the display of the activation factor display units 3a to 3c is displayed. Data processing unit 1 that is "Yes"
This is a circuit that selects the highest rank from the rank display circuits 61 to 63 of a to 1c.

Next, the operation of this extended storage control device will be described.

In each of the data processing units 1a to 1c, when data is transferred from the main storage device 7 to the extension storage device 8 or vice versa,
Information necessary for data transfer, for example, start instruction information including an address and a count is generated. It is usually generated by software.

The activation instruction information is not directly sent to the data transfer circuit 5 for data transfer processing, but is temporarily stored in the activation waiting queues 2a to 2c in each of the data processing units 1a to 1c. . The activation waiting queues 2a to 2c are queued in the order in which the activation instruction information is generated. Then, the fact that the activation instruction information exists in the activation waiting queues 2a to 2c is displayed by the activation factor display units 3a to 3c, and at the same time, is reported to the activation acceptance possible display unit 6.

The activation factor display sections 3a to 3c continue to display and report until there is no activation instruction information from the activation waiting queues 2a to 2c.

When the transfer end signal is sent from the data transfer circuit 5, the start acceptance possible display section 6 reads the start instruction information reading section (4a) of the data processing section (1a-1c) displaying the start factor "present". ~ 4c) displays that the start acceptance is possible.
At this time, when the activation factor “present” is displayed in the plurality of data processing units (1a to 1c), it is determined which activation instruction information reading unit (4a to 4n) should display the activation acceptance. To do.

The procedure of this determination will be described with reference to the timing chart of FIG. For convenience of explanation, a
The activation instruction information shown in FIG. 1 to c are the data processing units 1a to 1c.
For each one.

In the initial state, each activation factor display section 3a ...
3c respectively display "none", and the rank display circuits 61 to 63
Indicates the order of "3", "1", and "1", respectively.
The larger the value, the higher the priority.

First, when the first activation instruction information a is executed by the software and an activation interrupt is applied to the first data processing unit 1a, the data processing unit 1a waits for its activation instruction information a. Once stored in queue 2a,
The display of the activation factor display portion 3a is set to "present" and the next interrupt is waited for. Since the activation factor display portion 3a has become "present", the selection circuit 64 selects the one 61 whose activation factor display is "present" from the order display circuits 61 to 63. At this time, the activation acceptance display unit 6 displays activation acceptance on the first data processing unit 1a.

In the first data processing unit 1a, when the start acceptance is displayed, an interrupt occurs, and the data transfer start request is sent to the data transfer circuit 5 by the start instruction information a. Then, the display of the activation factor display portion 3a is changed to "none", and the next interrupt is waited for. Further, the data transfer circuit 5 starts data transfer according to the data transfer activation request.

The data transfer time of the start instruction information a normally takes 10 [ns]. Therefore, transfer start 2 [n
s], the next transfer instruction information b is executed during the transfer.
This transfer instruction information b is executed, and the second data processing unit 1
When the activation interrupt is applied to b, the second data processing unit 1
In step b, the start instruction information b is temporarily stored in its own start-up waiting queue 2b, the start-up factor display section 3b displays "Yes", and waits for the next interrupt. Even if the activation factor display unit 3b becomes “present”, the data transfer circuit 5 is transferring the previous activation instruction information a, so the activation acceptance possible display unit 6 waits for the end of the transfer. At this time, the second data transfer processing unit 1b can execute other processing until the start acceptance is displayed.

After 2 [ns], the next activation instruction information c is executed. When the activation interrupt is applied to the third data processing unit 1c by the execution of the activation instruction information c, the third data processing unit 1c temporarily stores the activation instruction information c in its own activation waiting queue 2c. , Activation factor display section 3c
Wait for the next interrupt with the display of "Yes". Even if the activation factor display unit 3c becomes “present”, the data transfer circuit 5 is transferring the first activation instruction information a, so the activation acceptance possible display unit 6 waits for the end of the transfer. At this time, the third data processing unit 1c can execute other processing until the start acceptance of its own is displayed.

After 6 [ns], when the data transfer of the start instruction information a is completed, the data transfer circuit 5 sends a transfer end signal to the start acceptability display section 6. Then, the selection circuit 64
Is the first data processing unit 1a that has finished the data transfer control.
The rank display circuit 61 corresponding to is lowered to the lowest display "1", and the display of the rank display circuit 62 which has been "2" until then is changed to "3" and the display of the rank display circuit 63 which is "1".
2 "respectively. Then, the activation factor display section 6 selects the circuit 63 having the highest order among the order determination circuits 62, 63 corresponding to the second and third data processing sections 1b, 1c of" present ". .

At this time, the activation acceptance display unit 6 displays activation acceptance permission on the third data processing unit 1c. This start acceptance enable display interrupts the third data processing unit 1c, and the third data processing unit 1c causes the data transfer circuit 5 to operate.
A data activation request based on the activation instruction information c is sent to, and the display of the activation factor display unit 3c is changed to "none", and the next interrupt is waited for. In response to this data transfer activation request, the data transfer circuit 5
Starts data transfer according to the start instruction information c.

Start data transfer of start instruction information c 10 [n
[s] and then the data transfer is completed, the data transfer circuit 5
Sends a transfer end signal to the start acceptability display unit 6. Then, the selection circuit 64 selects the order determination circuit 62 whose start factor display is “present”. At this time, the activation acceptance display unit 6 displays activation acceptance enabled on the second data processing unit 1b. When the activation acceptance is displayed, the second data processing unit 1b is interrupted, and the second data processing unit 1b sends a data activation request by the activation instruction information b to the data transfer circuit 5, and the activation factor display unit 3b. Change the display of to "No" and wait for the next interrupt. In response to this data transfer start request, the data transfer circuit 5 starts data transfer according to the start instruction information b.

[0034]

As described above in detail, the extended storage control device of the present invention is provided with an activation factor display section for each of the plurality of data processing sections, and at the end of the data transfer currently being executed. Since the reception control means is provided for notifying the data processing unit of the highest priority that the activation instruction information can be received, it is not necessary for each data processing unit to continuously inquire whether data transfer is possible, unlike the conventional case. This has the effect of reducing the time for waiting for data transfer.

Further, each data processing unit can execute other processing until the reception instruction is given to itself, as long as the activation factor display is “present”, so that the processing efficiency of each data processing unit is improved. Has the effect of

Further, when the currently executed data transfer is completed, the last display order is sequentially displayed on the order display circuit corresponding to the data transfer processing unit that controls the data transfer, so that a plurality of data processings are performed. Even when the parts are used, smooth and efficient data transfer can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram of an extended storage control device according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of the present embodiment.

FIG. 3 is a block diagram of a conventional extended storage control device.

[Explanation of symbols]

1a, 1b, 1c ... Data processing unit 2a, 2b, 2c ... Activation waiting queue 3a, 3b, 3c ... Activation factor display unit 4a, 4b, 4c ... Activation instruction information reading unit 5 ... Data transfer circuit 6 ... Activation acceptance possible display Part (acceptance control means) 61 to 63 ... Order display circuit 64 ... Selection circuit 7 ... Main storage device 8 ... Extended storage device 10a, 10b ... Inquiry unit 11 ... Transfer status display unit

Claims (2)

[Claims] 1. A device for performing data transfer control between a main storage device and an extended storage device according to activation instruction information generated and output from any of a plurality of data processing units, the acceptance of the activation instruction information. And a reception control unit that controls reception of the start instruction information to the data transfer circuit, the data transfer circuit executing the data transfer control and outputting a transfer end signal at each transfer end. The processing unit includes a boot instruction information generating unit that generates the boot instruction information,
A start waiting queue for storing the start instruction information,
When the activation instruction information is stored in the activation waiting queue, the activation factor display section for displaying the activation factor and the reception instruction sent from the acceptance control means while the activation factor is displayed are stored in the own activation waiting queue. And a start instruction information reading unit for reading the start instruction information and guiding it to the data transfer circuit, wherein the reception control means includes a rank display circuit for displaying the transmission order of the reception instruction in association with each data processing unit. A data processing unit corresponding to the counting means selected by the selection circuit when the transfer end signal is received from the data transfer circuit An extended storage control device, which outputs the acceptance instruction to 2. The selection circuit causes the rank display circuit corresponding to the data transfer processing unit that controls the data transfer to display the last rank in sequence when the data transfer currently being executed is completed. The extended storage device according to claim 1.