JPH06207968A - High speed digital signal processing circuit - Google Patents

Abstract

PURPOSE:To allow high speed operation test using a low speed tester. CONSTITUTION:The high speed digital signal processing circuit comprises a clock buffer 20 for shaping an external clock signal Ck inputted to a clock signal input terminal 12 and internally outputting a positive phase clock signal Ck and a negative phase clock signal CkR, a delay regulation circuit 22 for regulating the positive phase clock signal Ck depending on a pass delay time (d) of a selector 21 to output a delayed clock signal Ckd, and the selector 21 for receiving the negative phase clock signal CkRd and a test clock signal TCK having phase lead of beta ahead of the external clock signal CK received at a test clock terminal 13 and feeding any one of two clock signals CkR, TCK to the clock signal input terminal of a master side data latch 5M0 depending on a test control signal TCS. The delayed clock signal Ckd is fed to the clock signal terminal of a slave side data latch 5S0.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed digital signal processing circuit, and more particularly to a high speed operation test thereof.

[0002]

2. Description of the Related Art In recent years, the speed of LSI has been remarkably increased. For example, in the field of image processing, 14.3 MHz or 28.6 MHz for digital television, JPEG, M
High-speed signal processing of about 30 MHz is required for LSI for PEG, and 48.6 MHz for LSI for MUSE system, which is one of the high-definition televisions.

In the field of CPU, there are even those capable of 100 MHz operation. One of the current problems in high-speed digital signal processing LSIs such as LS
I have a problem with the operation test.

FIG. 4 is a block diagram of an example of a conventional high-speed digital signal processing circuit, and a time chart of each clock signal is shown in part of FIG. 2 to explain the operation of the block.

The data signal Si input from the input terminal 10 of FIG. 4 is input to a data flip-flop (hereinafter abbreviated as DFF) 30. The external clock signal CK input to the clock signal terminal 12 is an internal clock signal Ck whose waveform is shaped by the clock buffer 20A and which is slightly delayed by the phase α from the rising times t1 and t2.

The data signal Si input to the DFF 30 is output as an output signal S30 in synchronization with the rising time (t1 + α) of the clock signal Ck, and the signal processing circuit 40
The signal processing is performed by and is input to the DFF 31.

The clock signal Ck is again input to the DFF 31.
The data signal synchronized with the rising edge of
The signal processing is performed again by 1 and is input to the DFF 32.

Thereafter, similar processing is performed, and finally DFF3
The data signal synchronized with the rising edge of the clock signal Ck at (n-1) is subjected to signal processing by the signal processing circuit 4 (n-1) and input to the DFF 3n at the final stage.

The data signal synchronized with the rising edge of the clock signal Ck in the DFF 3n is output from the output terminal 11 as the processed output signal So. Digital signal processing is performed as described above.

When performing an operation test of such a high-speed digital signal processing circuit, the cycle T of the external clock signal CK
Naturally, 1 must be higher than the operating frequency of this signal processing circuit.

In the LSI tester currently used for the operation test of the LSI, the operation speed of the tester which is generally used is about 20 to 30 MHz, and the LSI tester which operates at a high speed of 50 MHz or more is very expensive. And the number is small.

[0012]

As described above, the conventional high-speed digital signal processing circuit requires a high-speed LSI tester capable of operating at an operation speed equal to or higher than the operation speed of the LSI in its operation test. There was a problem that the operation test could not be processed.

It is an object of the present invention to provide a high speed digital signal processing circuit which enables a high speed operation test even with a low speed LSI tester.

A high-speed digital signal processing circuit according to the present invention is a master-slave type data circuit in which two stages of data latches on a master side and a slave side are cascaded for a data signal input to an input terminal. While synchronizing n flip-flops with the internal clock signal (n-
1) Clock signal input in a high-speed digital signal processing circuit capable of performing a signal processing of the stage, outputting a processed output signal from an output terminal, confirming the processed output signal that is normal with respect to the data signal, and testing a normal operation A clock buffer that performs waveform shaping on an external clock signal input from a terminal and internally outputs a positive-phase clock signal and a negative-phase clock signal, and a delay adjustment circuit that performs delay adjustment on the positive-phase clock signal and outputs a delayed clock signal And the opposite phase clock signal is input to one side and the test clock signal of a predetermined lead phase to the external clock signal is input to the other side, and one of the two clock signals is input to the master according to a test control signal. The delayed clock signal, comprising a selection circuit input to the clock signal input terminal of the (slave) side data latch. The slave input to the clock signal terminal of the data latch (master) side, and is configured by adjusting said predetermined phase lead.

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention.
FIG. 2 is a time chart of each signal shown for explaining the operation of the block of FIG.

The high-speed digital signal processing circuit of the present embodiment has a master side data latch (abbreviated as DL in the drawing) 5M0 for the data signal Si input to the input terminal 10.
And a master-slave type data flip-flop 3A0 in which two stages of a slave side data latch 5S0 are connected in cascade.
.About.3An are synchronized with the internal clock signal and processed by the (n-1) stage signal processing circuits 40 to 4n.
The processing output signal So is output from the output terminal 11.

This high-speed digital signal processing circuit applies a waveform shaping to the external clock signal CK input from the clock signal input terminal 12 and internally outputs a positive-phase clock signal Ck and a negative-phase clock signal CkR 20.
A delay adjustment circuit 22 for adjusting the positive phase clock signal Ck according to the passage delay time d of the selector 21 and outputting the delayed clock signal Ckd; and the negative phase clock signal CkRd.
Is input to one side and the test clock signal TCK whose phase is advanced by β from the external clock signal CK is input to the other side from the test clock terminal 13, and one of the two clock signals CkR and TCK is input by the test control signal TCS. The master-side data latch 5M0 is provided with a selector 21 which is input to a clock signal input terminal. The delayed clock signal Ckd is input to the clock signal end of the slave side data latch 5S0.

Next, the operation of the block of FIG. 1 will be described with reference to the time chart of FIG. Similar to the conventional high-speed digital signal processing circuit shown in FIG. 3, the data signal Si input to the input terminal 10 is a data flip-flop (DF
F) Input to 3A0.

The external clock signal CK input to the clock signal terminal 12 is the internal positive / negative phase clock signal C whose waveform is shaped by the clock buffer 20 and whose phase is delayed by α.
After becoming k and CkR, the normal phase clock signal Ck is delayed by the delay adjusting circuit 22 by the delay time d due to passage through the selector 21.
The delay is adjusted by the same amount as the above to become the delayed clock signal Ckd.

The negative phase clock signal CkR is input to one input of the selector 21 and becomes the signal CkRd output from the selector 21 in the normal operation mode. On the other hand, the external test clock signal TCK whose phase is advanced by β from the external clock signal CK is connected to the other input of the selector 21, but is not selected in the normal operation mode.

Data signal Si input to DFF3A0
Is output as the signal S3A0 in synchronization with the rising time td of the clock signal Ckd, and the first signal processing circuit 40
Signal processing is performed by and is input to the DFF 3A1.

The clock signal C is again input to the DFF 3A1.
Data signal S3 synchronized with the rising time point td of kd
A1 is subjected to signal processing again by the signal processing circuit 41 and is input to the DFF 3A2.

Thereafter, similar processing is performed, and finally DFF is performed.
3A (n-1), the data signal S3A (n- synchronized with the rising time point td of the delayed clock signal Ckd
1) is subjected to signal processing by the signal processing circuit 4 (n-1) and input to the final flip-flop DFF3An.

In the DFF 3An, the data signal synchronized with the rising time point td of the delayed clock signal Ckd is output from the output terminal 11 as the processing output signal So.

In the present embodiment, the positive phase clock signal Ckd is always input to the clock signal input terminals of the slave side data latches 5S0 to 5Sn, but the selector is connected to the clock signal input terminals of the master side data latches DM5A0 to 5Mn. The output signal of 21 is input.

The test control signal TCS selects the negative-phase clock signal CkRd in the normal operation mode and the test clock signal TCK in the test mode,
The test clock signal TCkd is delayed by the delay time d due to the passage of the selector 21, respectively.

Therefore, the signal processing circuits 40 to 4 (n-1)
Is the delayed clock signal C shown in FIG. 2 in the normal operation mode.
The processing may be completed at the rising time td of kd to the falling time (t2 + td) of the clock signal CkRd, that is, the cycle T1.

However, in the test mode, from the rising time td of the delayed clock signal Ckd to the falling time tc of the test clock signal TCkd, that is, the period from the next rising time t2 to the time of the advance time β (T2 = t.
In c-td), high speed signal processing must be completed.

Therefore, when the operation test is good in this period T2, the same effect as the external clock cycle period T1 being shortened to T2 and being made faster can be obtained as a result.

For example, when T2 is 1/2 of T1, 2
50MHz with 5MHz external clock signal CK tester
This is equivalent to the confirmation of the high-speed operation of the circuit. Also,
At this time, the same effect can be obtained even if the selector 21 and the delay adjusting circuit 22 are exchanged.

Next, when such a circuit configuration is adopted, the hold time and the propagation delay time increase, which is very problematic in a high-speed digital signal processing LSI. A circuit for solving this problem is a second embodiment. 3 is shown as a block diagram of FIG.

The data signal Si is input to the DFF 3B,
The delayed clock signal Ckd is output to the DFF 3A0 via the delay adjustment circuit 22 for preventing the latch miss, in synchronization with the internal clock signal Ck whose waveform has been shaped by the clock buffer 20 and whose delay adjustment has not been performed.

The processing output signal So output from the DFF 5Bn is output by the DFF 3C in synchronization with the internal clock signal Ck.

As described above, by directly synchronizing with the internal clock signal Ck whose waveform is shaped by the clock buffer 20 on the input terminal 10 side and the output terminal 11 side of the LSI, the increase of the hold time and the propagation delay time is suppressed. You can For other circuit operations, refer to the above-mentioned first
The description is omitted because it is similar to the embodiment.

Further, two internal clock signals Ckd, T input to the clock terminals of the data latch of the first embodiment.
The same effect can be obtained by replacing ckd with the case of FIG. 1 on the master side and the slave side.

[0034]

As described above, according to the present invention, (n-1) stage signal processing is performed while the input data signal is synchronized with the clock signal by the n data flip-flops, and output to the output terminal. The data flip-flop is intended for a master-slave high-speed digital signal processing circuit in which two data latches are connected in cascade.

In the test mode, the clock signal input of the master side data latch of the data flip-flop is switched to the test clock signal of the leading phase input from the outside to accelerate the operation speed of the signal processing circuit and use a normal LSI tester. As a result, there is an effect that a higher speed digital signal processing test can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

2 is a time chart of a clock signal shown to explain the operation of the blocks of FIGS. 1 and 4. FIG.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of an example of a conventional high speed digital signal processing circuit.

[Explanation of symbols]

10 Input Terminal 11 Output Terminal 12 Clock Signal Terminal 13 Test Clock Signal Terminal 14 Test Control Terminal 20, 20A Clock Buffer 21 Selector 22, 22A Delay Adjustment Circuit 3A0-3An, 3B, 3C Data Flip-Flop 40-4 (n-1) Signal processing circuit 5M0 to 5Mn Master side data latch 5S0 to 5Sn Slave side data latch CK External clock signal Ck Internal clock signal Ckd Delayed clock signal CkR Reverse phase internal clock signal CkRd Reverse phase selection clock signal Si data signal So process output signal TCK test Clock signal TCkd Delay test clock signal TCS test control signal T1, T2 cycle t1, t2 time point d delay time α delay phase β advance phase

Claims (1)

[Claims] 1. A master-slave type data flip-flop having n master-slave two-stage data latches connected in cascade to a data signal input to an input terminal is synchronized with an internal clock signal. (N-
1) Clock signal input in a high-speed digital signal processing circuit capable of performing stage signal processing, outputting a processed output signal from an output terminal, confirming the normal processed output signal against the data signal, and testing a normal operation A clock buffer that performs waveform shaping on an external clock signal input from a terminal and internally outputs a positive-phase clock signal and a negative-phase clock signal, and a delay adjustment circuit that performs delay adjustment on the positive-phase clock signal and outputs a delayed clock signal And the opposite phase clock signal is input to one side and the test clock signal of a predetermined lead phase to the external clock signal is input to the other side, and one of the two clock signals is input to the master according to a test control signal. The delayed clock signal, comprising a selection circuit input to the clock signal input terminal of the (slave) side data latch. The slave (master) is input to the clock signal terminal side of the data latch, high-speed digital signal processing circuit, characterized by adjusting said predetermined phase lead.