JPH06204794A - Criterion feedback type equalizer - Google Patents

Abstract

PURPOSE:To attain the equalization processing of a reception signal at a high speed. CONSTITUTION:A forward equalization filter 61 is provided with a weighting circuit for a reception signal, an adder sequentially adding outputs of each tap, and a register arranging the timing of an output signal of each adder. A backward equalization filter 10 is provided with a weighting circuit for the output signal of a discrimination unit 69, an adder outputting directly a 1st tap output as a 1st output A and sequentially adding the outputs of 2nd and succeeding taps, and a register arranging the timing of an output signal of each adder as a 2nd output B. Them the equalizer is provided with a 1st adder 11 adding the output of the forward equalization filter and the 2nd output of the backward equalization filter and a 2nd adder 12 adding the output of the 1st adder and the 1st output of the backward equalization filter, outputting the sum via a register and giving it to the direcrimination unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decision feedback equalizer using a transversal filter having excellent equalization characteristics under frequency selective fading. The present invention is also applicable to a cross polarization interference compensator using a transversal filter.

[0002]

2. Description of the Related Art In a wireless communication transmission line, a received signal is a combination of a direct wave and a plurality of reflected waves which are interference waves of the received wave and are therefore used to compensate for waveform distortion. A transversal filter is used for the conversion processing.

FIG. 4 is a block diagram showing a configuration example of a transversal filter. In the figure, the received signal is
A plurality of delay elements 4 connected in cascade from the input terminal 41
2 ₁ and 42 ₂ are input to each delay element of the data signal 1
By giving a delay corresponding to a time slot, a signal advanced from the main signal and a signal delayed from the main signal (a signal with a plurality of taps) are extracted. The signals of the multiple taps are weighted by the weighting circuit 43 ₁ corresponding to each tap.
In ~ 43 _3, each predetermined weighting coefficients C _-1, C _0,
Multiply by C ₁ and combine them in adder 44. The control circuit 45 generates weighting coefficients to be given to the weighting circuits 43 ₁ to 43 ₃ so that intersymbol interference (waveform distortion) generated before and after the main signal in the combining process in the adder 44 is canceled. With such a configuration, it is possible to equalize the waveform distortion of the received signal due to the plurality of reflected waves.

FIG. 5 is a block diagram showing a configuration example of a decision feedback equalizer for equalizing a quadrature amplitude modulation signal. In addition,
The decision feedback equalizer is an application of the transversal filter shown in FIG. 4, which separates the tap input before and after the center point of the equalization output, and uses the received signal in the forward equalization (FF) filter. The rear equalization (FB) filter is configured to use the determination result of the output signal of the front equalization filter.

In the figure, a quadrature amplitude modulation signal received by a receiver 50 is input to a quadrature detector 52 via a distributor 51, detected using local oscillation signals whose phases are different by 90 degrees, and quadrature with each other. Are output as the I channel signal and the Q channel signal. The quadrature detector 52
Is composed of a local oscillator 53, a 90-degree phase shifter 54, and two mixers 55 ₁ and 55 ₂ . The I-channel signal and the Q-channel signal are converted into digital signals by analog-to-digital converters (AD) 56 ₁ and 56 ₂ and input to the decision feedback equalizer 60.

A forward equalization (FF) filter 61 and a backward equalization (FB) filter 62 which constitute the decision feedback equalizer 60.
Are realized by four series of transversal filters for removing in-phase distortion and quadrature distortion of the I channel and the Q channel, respectively.

The I-channel signal input to the decision feedback equalizer 60 is a common-mode filter (II-) for equalizing common-mode distortion.
FF) 63 ₁ and a quadrature filter (QI-FF) 64 that removes quadrature distortion from the I channel signal to the Q channel signal.
Entered in ₁ . The Q-channel signal is input to an in-phase filter (QQ-FF) 63 ₂ that equalizes in-phase distortion and a quadrature filter (IQ-FF) 64 ₂ that removes quadrature distortion from the Q-channel signal to the I-channel signal.

II-FF63 ₁ and IQ-FF64 ₂
The respective outputs of ₁ are combined by the adder 65 ₁ , and intersymbol interference from the signal received later than the main signal of the I channel signal is removed. The outputs of QQ-FF63 ₂ and QI-FF64 ₁ are combined by adder 65 ₂ to eliminate intersymbol interference from the signal received later than the main signal of the Q channel signal.

The output of the adder 65 _{1 and} the outputs of the in-phase filter (II-FB) 66 ₁ and the quadrature filter (IQ-FB) 67 ₂ of the backward equalization filter 62 are combined by the adder 68 ₁ to obtain the I channel signal. The intersymbol interference from the signal received earlier than the main signal of is removed. The output of the adder 65 _2, the in-phase filter backward equalization filter 62 (QQ-F
B) The outputs of 66 ₂ and the quadrature filter (QI-FB) 67 ₁ are combined by the adder 68 ₂ to remove intersymbol interference from the signal received earlier than the main signal of the Q channel signal. The outputs of the adders 68 ₁ and 68 ₂ are taken out as I channel signals and Q channel signals equalized by the decision feedback equalizer 60.

Also, the equalized I-channel signal and Q
The channel signal is input to the rear equalization filter 62 via the discriminators 69 ₁ and 69 ₂ . The signal information (hard decision bit) of the I channel signal output from the discriminator 69 ₁ includes II-FB66 ₁ that equalizes in-phase distortion and QI-FB67 that removes quadrature distortion from the I channel signal to the Q channel signal. Entered in ₁ . The signal information (hard decision bit) of the Q channel signal output from the discriminator 69 ₂ is
And QQ-FB66 ₂ to equalize the in-phase distortion, IQ-F for removing quadrature distortion to I-channel signal from the Q-channel signal
Input to B67 ₂ .

In the structure of the decision feedback equalizer 60, the adder 65 for processing the output of the forward equalization filter 61 is used.
_1, 65 to the _second output, the signal intersymbol interference removed from the signal received with a delay from the main signal (the signal passing through the negative tap path) can be obtained, correspondingly backward equalization filter 62 The signals input to the plus-side taps of the in-phase filter 66 and the quadrature filter 67 inside are cleared, and the equalization capability can be improved.

[0012]

By the way, in the decision feedback equalizer 60, it is necessary to make the tap interval between the front equalization filter 61 and the rear equalization filter 62 continuous. However, for high-speed received signals, the adder 6 between both filters
In order to suppress the total operation delay of 5, 68 and discriminator 69 within the one time slot, it is necessary to operate each element with a high-speed clock higher than the transmission speed, and it is easy to secure the continuity of taps. Was not.

The present invention provides a decision feedback equalizer capable of equalizing a received signal at high speed and further reducing the circuit scale by configuring all circuits by digital circuits. To aim.

[0014]

SUMMARY OF THE INVENTION The present invention is a decision feedback equalizer having a front equalization filter, a discriminator, and a rear equalization filter, wherein the front equalization filter divides a received signal into a plurality of received signals. It is provided with a weighting circuit that distributes to taps and performs predetermined weighting for each tap, an adder that sequentially adds the output of each tap, and a register that outputs the output signals of each adder at the same timing. The filter is
The output signal of the discriminator is distributed to a plurality of taps, and a weighting circuit that performs a predetermined weighting for each tap and a first tap output is directly output as a first output,
An adder that sequentially adds tap outputs after the second tap,
A first adder for synthesizing an output of the front equalization filter and a second output of the rear equalization filter, the register including a register for outputting the second output by adjusting the timings of the output signals of the respective adders; A second adder for synthesizing the output of the adder and the first output of the backward equalization filter, outputting the result through a register and giving the same to the discriminator.

[0015]

In the present invention, the tap output of the signal (first tap path) received one time slot ahead of the main signal is directly output from the weighting circuit as the first output of the backward equalization filter. Also, as the second output of the backward equalization filter, the tap output of the signal (after the second tap path) received earlier than the main signal by two time slots or more is output.

Here, the output of the front equalization filter and the second output of the rear equalization filter are added in the first adder, and the output of the first adder is added in the second adder. , The first output directly obtained from the backward equalization filter is added, and the result is taken out as the output of the decision feedback equalizer via the register to obtain the final tap of the forward equalization filter and the first tap of the backward equalization filter. The tap interval of can be continuous.

[0017]

1 is a block diagram showing the construction of an embodiment of a decision feedback equalizer of the present invention. The present embodiment shows a configuration example of a decision feedback equalizer that equalizes a quadrature amplitude modulation signal.

The forward equalization (FF) filter 61 is the same as the conventional one shown in FIG. 5, and FIG. 2 shows an example of the configuration of a transversal filter (in-phase filter, quadrature filter) of the four series.

In FIG. 2, a received signal (I channel signal or Q channel signal) is distributed to a plurality of taps C _{0 to} C _-3 , and weighting circuits 21 _{1 to} 21 ₄ for performing a predetermined weighting on each tap. Are entered at the same time. The adder 22 ₁ synthesizes the signal (main signal) of the tap path of the center tap C ₀ output from the weighting circuit 22 ₁ and "0", and sends it to the register 23 ₁ . Register 23 ₁
Sends the output of the adder 22 ₁ (tap output of C ₀ ) to the next adder 22 ₂ at the timing synchronized with the clock. The adder 22 ₂ sends a signal tap path C _0, and a signal tap path C _-1 outputted from the weighting circuit 22 ₂ synthesis to the register 23 _2. And so on
The adder 22 ₃ sends the C ₀ and C and combined output signals of each tap path of _-1, the weighting circuit 22 ₃ and a signal tap path C _-2 outputted synthesized to the register 23 ₃ ,
The adder 22 ₄ outputs the combined output of the signals of the tap paths of C ₀ , C _-1 , and C _-2 and the C output from the weighting circuit 22 _4.
-3 and the signal of the tap path are combined and sent to the register 23 ₄ .

[0020] Here, the adder 22 _4, 1T by signal passes through the register 23 ₃ taps path C _-2 when viewed on a time axis is input (T is the baud rate intervals) later, C _- The signal of the tap path of ₁ is the register 23 ₂ , 23
₃ is 2T delayed input by passing through, is input with a delay 3T by the signal tap path C ₀ is passed through the registers 23 ₁ to 23 _3.

With such a configuration, the received signal controls the weighting coefficient (tap coefficient C _{0 to} C _-3 ) for each tap, so that intersymbol interference from three signals received later than the main signal is received. Can be removed, register 2
Can be taken as the output of the forward equalizer filter 61 at the timing synchronized _3-4 clock.

In FIG. 1, the I-channel signal input to the decision feedback equalizer is an in-phase filter (II-FF) 63 ₁ for equalizing in-phase distortion and a quadrature distortion from the I-channel signal to the Q-channel signal. Quadrature filter (QI-
FF) 64 ₁ . Q channel signal, a phase filter (QQ-FF) 63 ₂ for equalizing the phase distortion, Q
It is input to an orthogonal filter (IQ-FF) 64 ₂ that removes orthogonal distortion from the channel signal to the I-channel signal.

Adder 65₁Is the common mode distortion of the I channel signal
Delayed from main signal
Register to remove intersymbol interference from received signals
11 ₁Send to. Adder 65₂Is the Q-channel signal
A signal that equalizes in-phase distortion and quadrature distortion is combined and
Inter-symbol interference from signals received later in
Dista 11₂Send to. Register 11₁, 11₂Is
Timed synchronization of each equalized channel signal to the clock
With the output of the backward equalization (FB) filter 10
First adder 12 of the two-stage configuration for performing₁, 1
Two₂Send to.

On the other hand, the equalized I channel signal and Q
The channel signal is input to the backward equalization filter 10 via the discriminators 69 ₁ and 69 ₂ . The determination signal of the I channel signal output from the discriminator 69 ₁ includes an in-phase filter (II-FB) 14 ₁ that equalizes in-phase distortion and a quadrature filter (II-FB) that removes quadrature distortion from the I-channel signal to the Q-channel signal. QI-FB) 15 ₁ . Determination signal Q channel signal output from the discriminator 69 ₂ in-phase filter to equalize the phase distortion (QQ-FB) 14
₂ and a quadrature filter (IQ-FB) 15 ₂ that removes the quadrature distortion from the Q channel signal to the I channel signal.

The backward equalization filter 10 is different from the conventional one shown in FIG. 5, and FIG. 3 shows an example of the configuration of the four-series transversal filter (in-phase filter, quadrature filter).

In FIG. 3, the determination signal is distributed to a plurality of taps C _{1 to} C ₃ and is simultaneously input to weighting circuits 31 _{1 to} 31 ₃ which perform a predetermined weighting for each tap.

First tap C₁The signal on the tap path of
Signals other than the path of are not added in this filter,
Weighting circuit 31₃Of the backward equalization filter 10 directly from
Taken as output A. Adder 32₁Is weighted
Circuit 31₃Output from C ₃With the tap path signal of
Register 33 by combining with "0"₁Send to. Regis
33₁Is the adder 3 at the timing synchronized with the clock
Two₁Output (C₃Tap output) to the next adder 32₂To
Send out. Adder 32₂Is C₃Signal on tap path
And the weighting circuit 31₂Output from C₂Tap of
Register 33 by synthesizing with the signal of the road₂Send to.

[0028] Here, the register 33 to the _second output signal of the C ₂ taps path when viewed on the time axis register 33 ₂
Retrieved late 1T by passing through, the signal tap path C ₃ is taken out delayed 2T by passage through the registers 33 _1, 33 ₂ are sent as output B from the backward equalization filter 10. The output A is C
The signal of the tap path of ₁ is output with a delay of 0T.

In FIG. 1, in the first adder 12 ₁ ,
An I channel signal equalized by the front equalization filter 61,
II-FB 14 ₁ and IQ- of the rear equalization filter 10
Each C _{2 of the} FB 15 ₂ and the combined output (output B) of the signal that has passed through the tap path of C ₃ are combined. Second adder 1
In 3 _1, and the output of the first adder 12 _1, II-FB14 ₁ and IQ-FB15 ₂ signals of each C ₁ tap path (output A) of the backward equalization filter 10 and combined to the register 16 Send to ₁ .

Similarly, in the first adder 12 ₂ , the Q channel signal equalized by the front equalization filter 61 and the QQ-FB 14 ₂ and QI-FB 1 of the rear equalization filter 10 are used.
The combined output (output B) of the signals passing through the tap paths of C ₂ and C ₃ of 5 ₁ is combined. The second adder 13 ₂ outputs the output of the first adder 12 ₂ and the backward equalization filter 1
0 QQ-FB14 ₂ and QI-FB15 ₁ each C ₁
Register 1 by synthesizing with the signal (output A) of the tap path of
Send to 6 ₂ .

The outputs of the respective second adders 13 ₁ and 13 ₂ are
Registers 16 ₁ , 16 at the timing synchronized with the clock
₂ are extracted as I channel signals and Q channel signals equalized by the decision feedback equalizer, and the discriminator 6
It is fed back to the backward equalization filter 10 via 9 ₁ and 69 ₂ .

Here, the continuity of each tap will be described by taking an I channel signal as an example. By I-channel signal inputted to the decision feedback equalizer is input to the first adder 12 _1, the tap path C _0, the register 23 _1,
It takes 5T since it passes through 23 ₂ , 23 ₃ , 23 ₄ , and 11 ₁ . In the tap path of C _-1 , register 2
It takes 4T since it passes through 3 ₂ , 23 ₃ , 23 ₄ , and 11 ₁ . In the tap path of C _-2 , the registers 23 ₃ ,
It takes 3T since it passes through 23 ₄ and 11 ₁ . C
_In the tap path of _-3 , it takes 2T since it passes through the registers 23 ₄ and 11 ₁ .

On the other hand, C₁The signal on the tap path of₀of
At the time of 5T required for the tap path signal (main signal),
Dista 16₁The second adder with a delay of 6T
Thirteen ₁Entered in. Also, C₂Signal on tap path
At the time of 5T required by the main signal, register 16₁, 3
Three₂7T delay due to the addition of₃Tap of
The signal of the road is registered in the register 1 at the time of 5T required by the main signal.
6₁, 33₁, 33₂8T delay due to the delay
Second adder 13₁Entered in.

With such a configuration, the signal of the tap path of C ₀ and the signal of the tap path of C ₁ can be made 1T difference, and the front equalization filter 61 and the rear equalization filter 1 can be made.
The tap interval of 0 can be continuous.

The front equalizing filter 61 and the rear equalizing filter 10 are composed of four series of transversal filters, and the adders 12 and 13 having three inputs are used, so that the I channel signal and the Q channel are all digital circuits. In-phase distortion and quadrature distortion of the channel signal can be removed at the same time.

[0036]

As described above, in the decision feedback equalizer of the present invention, the adder in the feedback loop of the first tap path of the backward equalization filter is used as the second adder of the first adder. By arranging the output in the subsequent stage, taking out the output through the register, and feeding it back to the backward equalization filter, the continuity of the tap interval between the forward equalization filter and the backward equalization filter can be maintained.

That is, it is not necessary to use a high-speed clock having a transmission speed higher than that of a high-speed received signal, and a decision feedback equalizer capable of easily equalizing a high-speed signal can be realized.

Further, since the decision feedback equalizer of the present invention can be constructed by all digital circuits, the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a decision feedback equalizer of the present invention.

FIG. 2 is a block diagram showing a configuration example of a four-series transversal filter (II, IQ, QI, QQ-FF) of the front equalization filter 61.

FIG. 3 is a block diagram showing one configuration example of a four-series transversal filter (II, IQ, QI, QQ-FB) of the backward equalization filter 10.

FIG. 4 is a block diagram showing a configuration example of a transversal filter.

FIG. 5 is a block diagram showing a configuration example of a decision feedback equalizer that equalizes a quadrature amplitude modulation signal.

[Explanation of symbols]

 10 Backward equalization (FB) filter 11 Register 12 First adder 13 Second adder 14 In-phase filter (II-FB, QQ-FB) 15 Quadrature filter (QI-FB, IQ-FB) 16 Register 21 Weighting Circuit 22 Adder 23 Register 31 Weighting circuit 32 Adder 33 Register 41 Input terminal 42 Delay element (T) 43 Weighting circuit 44 Adder 45 Control circuit 50 Receiver 51 Distributor 52 Quadrature detector 53 Local oscillator 54 90 degree phase shift Unit 55 Mixer 56 Analog-to-Digital Converter (AD) 60 Decision Feedback Equalizer 61 Forward Equalization (FF) Filter 62 Backward Equalization (FB) Filter 63,66 In-phase Filter 64,67 Quadrature Filter 65,68 Adder 69 discriminator

Claims (1)

[Claims] 1. A forward equalization filter that receives a received signal and removes intersymbol interference from a signal received later than a main signal, and a discriminator that outputs a discrimination result of an output signal of the forward equalization filter. And input the identification result of the output signal of the forward equalization filter,
In a decision feedback equalizer with a backward equalization filter for removing intersymbol interference from a signal received earlier than the main signal, the forward equalization filter distributes the received signal to a plurality of taps, A weighting circuit that performs predetermined weighting for each tap, an adder that sequentially adds the output of each tap,
And a register for outputting the output signals of the respective adders at the same timing, wherein the rear equalization filter distributes the output signal of the discriminator to a plurality of taps, and performs weighting for predetermined weighting for each tap. A circuit, an adder for directly outputting the first tap output as the first output, a register for sequentially adding the tap outputs of the second and subsequent taps, and a register for aligning the timing of the output signals of the respective adders and outputting as the second output A first adder for synthesizing an output of the front equalization filter and a second output of the rear equalization filter; an output of the first adder; and a second output of the rear equalization filter. A decision feedback equalizer, characterized in that it comprises a second adder which combines the one output and outputs it through a register and gives it to the discriminator.