JPH06204632A - Copper-clad laminated board for surface mounting printed wiring board - Google Patents

Copper-clad laminated board for surface mounting printed wiring board

Info

Publication number
JPH06204632A
JPH06204632A JP14910591A JP14910591A JPH06204632A JP H06204632 A JPH06204632 A JP H06204632A JP 14910591 A JP14910591 A JP 14910591A JP 14910591 A JP14910591 A JP 14910591A JP H06204632 A JPH06204632 A JP H06204632A
Authority
JP
Japan
Prior art keywords
copper
surface mounting
butyral
printed wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14910591A
Other languages
Japanese (ja)
Inventor
Hirobumi Tsuji
博文 辻
Kazunori Mitsuhashi
一紀 光橋
Shigeru Ito
繁 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Shin Kobe Electric Machinery Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Kobe Electric Machinery Co Ltd filed Critical Shin Kobe Electric Machinery Co Ltd
Priority to JP14910591A priority Critical patent/JPH06204632A/en
Publication of JPH06204632A publication Critical patent/JPH06204632A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the generation of cracks caused by thermal shock at the solder connecting part of a surface mounting part with a copper-clad laminated board for a surface mounting printed wiring board. CONSTITUTION:In an epoxy resin laminated board of glass woven fiber base material, a layer of butyral denaturation phenol resin is formed in the inside of a copper foil as a unitary body at the surface in contact with the copper foil. The layer becomes a rubber state at a high temperature. Stress based on the difference in thermal expansions of the surface mounting part and a substrate is absorbed, and the generation of cracks caused by the above described stress at a solder connecting part is prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、表面実装部品(Sur
face Mount Device:SMD)搭載のた
めのプリント配線板用銅張り積層板に関する。
BACKGROUND OF THE INVENTION The present invention relates to surface mount components (Sur
The present invention relates to a copper-clad laminate for a printed wiring board for mounting a face mount device (SMD).

【0002】[0002]

【従来の技術】セラミックチップ等のSMDを搭載する
プリント配線板は、SMDの熱膨張係数が6.5×10~
6/℃と小さいために、配線板の基板にも平面方向の熱
膨張係数が小さいものが要求される。従来用いられてい
るのは、ガラス織布基材エポキシ樹脂積層板(FR−
4)を基板としたものであり、その平面方向の熱膨張係
数は、(10〜15)×10~6/℃である。SMDの搭
載には、クリーム半田を使用するリフロー半田付け法が
主として採用されている。
2. Description of the Related Art A printed wiring board on which an SMD such as a ceramic chip is mounted has a coefficient of thermal expansion of 6.5 × 10 to SMD.
Since it is as small as 6 / ° C, a substrate for a wiring board is also required to have a small coefficient of thermal expansion in the plane direction. Conventionally used is a glass woven fabric-based epoxy resin laminate (FR-
4) the is obtained by a substrate, the thermal expansion coefficient of the plane direction is (10~15) × 10 ~ 6 / ℃. A reflow soldering method using cream solder is mainly used for mounting the SMD.

【0003】[0003]

【発明が解決しようとする課題】上記の技術では、SM
Dと基板の熱膨張係数の差が比較的小さいので、両者の
熱による膨張収縮の差もそれほど大きいものではなく、
現時点では対応している。しかし、熱衝撃が大きくなる
と、前記膨張収縮の差も大きくなり、半田接続部に大き
な応力が作用して、半田接続部にクラックが生じやすく
なる。本発明が解決しようとする課題は、SMDを搭載
したプリント配線板の半田接続部の熱衝撃に対する接続
信頼性を高めることであり、そのための銅張り積層板を
提供する。
In the above technique, the SM is used.
Since the difference in the coefficient of thermal expansion between D and the substrate is relatively small, the difference in the expansion and contraction due to the heat of the two is not so large.
Currently supported. However, when the thermal shock increases, the difference between the expansion and contraction also increases, and a large stress acts on the solder connection portion, so that cracks are likely to occur in the solder connection portion. The problem to be solved by the present invention is to improve the connection reliability against the thermal shock of the solder connection part of the printed wiring board on which the SMD is mounted, and to provide a copper clad laminate for that purpose.

【0004】[0004]

【課題を解決するための手段】上記課題を解決する本発
明に係る表面実装プリント配線板用銅張り積層板は、エ
ポキシ樹脂含浸ガラス織布基材層を基板としその表面に
銅箔を一体に設けたものにおいて、銅箔の内側に、これ
と接してブチラール変性フェノール樹脂の層を形成した
ことを特徴とする。
A copper-clad laminate for a surface-mounting printed wiring board according to the present invention which solves the above-mentioned problems has an epoxy resin-impregnated glass woven base material layer as a substrate and a copper foil integrally formed on the surface thereof. The provided one is characterized in that a layer of butyral-modified phenolic resin was formed inside the copper foil in contact with it.

【0005】[0005]

【作用】上記ブチラール変性フェノール樹脂の層は、1
00℃における弾性率が40Kgf/cm2であり、殆どゴム
状態にあると考えられる。従って、使用環境が高温にな
って基板と搭載しているSMDとの間の熱膨張の差が大
きくなっても、ゴム状態になっているブチラール変性フ
ェノール樹脂の層が変形することにより、前記熱膨張差
に基づく応力を吸収し、半田接続部に応力がかかるのを
回避することができる。
The above-mentioned butyral-modified phenol resin layer has 1 layer.
The elastic modulus at 00 ° C. is 40 Kgf / cm 2 , which is considered to be almost rubbery. Therefore, even if the use environment becomes high and the difference in thermal expansion between the substrate and the mounted SMD becomes large, the layer of butyral-modified phenolic resin in the rubber state is deformed, and the heat It is possible to absorb the stress due to the difference in expansion and avoid applying stress to the solder connection portion.

【0006】[0006]

【実施例】実施例1 0.2mm厚さのガラス織布に臭素化ビスフェノールA型
エポキシ樹脂を含浸乾燥して得たプリプレグを8枚重
ね、その両側に25μ厚さのブチラール変性フェノール
樹脂シートを配し、最外層には18μmの銅箔を配し
て、温度165℃、圧力30Kgf/cm2で50分間加熱加
圧成形して1.6mm厚さの銅張り積層板とした。この積
層板に、以下の工程にて配線板加工を行った。所定位置
にスルホール加工をした後、エッチングにより回路形成
をし、最終仕上げとして半田レベラー処理を行った。部
品の実装および半田付け工程は、リフロー面およびフロ
ー面にセラミックチップ抵抗(4532タイプ)を搭載
し、遠赤外リフロー半田付け(クリーム半田)し、その
後フロー半田付け(溶融半田)をした。半田接続部の初
期の表面状態を観察した後、−30℃/30分と80℃
/30分の気層冷熱サイクル試験を行い、半田接続部の
クラック発生状況を観察した。その結果を他の特性と共
に表2に示すが、表1には基板とブチラール変性フェノ
ール樹脂層の弾性率を参考までに示した。ブチラール変
性フェノール樹脂層は、30℃においても基板の約1/
5の弾性率である。
Example 1 Eight prepregs obtained by impregnating a 0.2 mm-thick glass woven cloth with a brominated bisphenol A type epoxy resin and drying the prepregs were laminated with a 25 μ-thick butyral-modified phenolic resin sheet on both sides. Then, a copper foil of 18 μm was placed on the outermost layer, and heat and pressure molding was performed at a temperature of 165 ° C. and a pressure of 30 Kgf / cm 2 for 50 minutes to obtain a 1.6 mm thick copper clad laminate. Wiring board processing was performed on this laminated board in the following steps. After the through hole processing at a predetermined position, a circuit was formed by etching, and a solder leveler process was performed as a final finish. In the component mounting and soldering process, a ceramic chip resistor (4532 type) was mounted on the reflow surface and the flow surface, far infrared reflow soldering (cream solder) was performed, and then flow soldering (molten solder) was performed. After observing the initial surface condition of the solder joint, -30 ℃ / 30 minutes and 80 ℃
A vapor phase cooling / heating cycle test was performed for / 30 minutes, and the occurrence of cracks at the solder joints was observed. The results are shown in Table 2 together with other properties. In Table 1, the elastic moduli of the substrate and the butyral-modified phenolic resin layer are shown for reference. The butyral modified phenolic resin layer is about 1 / th of the substrate even at 30 ° C.
The elastic modulus is 5.

【0007】尚、ブチラール変性フェノール樹脂層は、
そのシートを使用する代わりに銅箔の接着面や表面のプ
リプレグにブチラール変性フェノール樹脂を塗布してお
いて形成してもよい。
The butyral modified phenolic resin layer is
Instead of using the sheet, a butyral-modified phenolic resin may be applied to the adhesive surface of the copper foil or the prepreg on the surface.

【0008】[0008]

【表1】 [Table 1]

【0009】従来例1 実施例1において、ブチラール変性フェノール樹脂シー
トを使用せず、他は実施例1と同様の工程を経て配線板
とした。その特性を表2に示す。
Conventional Example 1 In Example 1, a butyral-modified phenolic resin sheet was not used, and the other steps were the same as in Example 1 to obtain a wiring board. The characteristics are shown in Table 2.

【0010】[0010]

【表2】 [Table 2]

【0011】表2において、スルホール信頼性は、20
℃シリコンオイルと260℃シリコンオイルへの繰返し
浸漬を行ない、導通抵抗の増加が起こるまでのサイクル
を調べた。半田耐熱性は、260℃半田浴に浸漬して実
施した。絶縁抵抗は、櫛型パターン(ピッチ0.5mm,
ライン幅0.5mm)を使用して、C−1000/80/
95処理後に100Vを1分間印加後に測定した。
In Table 2, the through hole reliability is 20
By repeating the dipping in the silicone oil of ° C and the silicone oil of 260 ° C, the cycle until the increase of the conduction resistance occurred was examined. The solder heat resistance was measured by immersing in a solder bath at 260 ° C. Insulation resistance is a comb pattern (pitch 0.5 mm,
Line width 0.5mm), C-1000 / 80 /
After 95 treatment, 100 V was applied for 1 minute and then measured.

【0012】[0012]

【発明の効果】表1から明らかなように、基板と表面実
装部品の熱膨張の差に基づく応力をブチラール変性フェ
ノール樹脂の層が吸収して、半田接続部に前記応力に起
因するクラックが発生するのを防止することができる。
そして、他の特性は、従来のガラス織布基材エポキシ樹
脂積層板と同等である。
As is apparent from Table 1, the butyral-modified phenolic resin layer absorbs the stress caused by the difference in thermal expansion between the substrate and the surface-mounted component, and cracks due to the stress are generated in the solder joint. Can be prevented.
And other characteristics are the same as the conventional glass woven fabric-based epoxy resin laminate.

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成3年6月24日[Submission date] June 24, 1991

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0006[Correction target item name] 0006

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【実施例】実施例1 0.2mm厚さのガラス織布に臭素化ビスフェノールA型
エポキシ樹脂を含浸乾燥して得たプリプレグを8枚重
ね、その両側に25μ厚さのブチラール変性フェノール
樹脂シートを配し、最外層には18μmの銅箔を配し
て、温度165℃、圧力30Kgf/cm2で50分間加熱加
圧成形して1.6mm厚さの銅張り積層板とした。この積
層板に、以下の工程にて配線板加工を行った。所定位置
にスルホール加工をした後、エッチングにより回路形成
をし、最終仕上げとして半田レベラー処理を行った。部
品の実装および半田付け工程は、リフロー面およびフロ
ー面にセラミックチップ抵抗(4532タイプ)を搭載
し、遠赤外リフロー半田付け(クリーム半田)し、その
後フロー半田付け(溶融半田)をした。半田接続部の初
期の表面状態を観察した後、−30℃/30分と80℃
/30分の気層冷熱サイクル試験を行い、半田接続部の
クラック発生状況を観察した。その結果を他の特性と共
に表2に示すが、表1には基板とブチラール変性フェノ
ール樹脂層の弾性率を参考までに示した。ブチラール変
性フェノール樹脂層は、30℃においても基板の約1/
00の弾性率である。
Example 1 Eight prepregs obtained by impregnating a 0.2 mm-thick glass woven cloth with a brominated bisphenol A type epoxy resin and drying the prepregs were laminated with a 25 μ-thick butyral-modified phenolic resin sheet on both sides. Then, a copper foil of 18 μm was placed on the outermost layer, and heat and pressure molding was performed at a temperature of 165 ° C. and a pressure of 30 Kgf / cm 2 for 50 minutes to obtain a 1.6 mm thick copper clad laminate. Wiring board processing was performed on this laminated board in the following steps. After the through hole processing at a predetermined position, a circuit was formed by etching, and a solder leveler process was performed as a final finish. In the component mounting and soldering process, a ceramic chip resistor (4532 type) was mounted on the reflow surface and the flow surface, far infrared reflow soldering (cream solder) was performed, and then flow soldering (molten solder) was performed. After observing the initial surface condition of the solder joint, -30 ℃ / 30 minutes and 80 ℃
A vapor phase cooling / heating cycle test was performed for / 30 minutes, and the occurrence of cracks at the solder joints was observed. The results are shown in Table 2 together with other properties. In Table 1, the elastic moduli of the substrate and the butyral-modified phenolic resin layer are shown for reference. The butyral modified phenolic resin layer is about 1 / th of the substrate even at 30 ° C.
5, which is a 00 modulus of elasticity.

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0008[Correction target item name] 0008

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【表1】 [Table 1]

【手続補正3】[Procedure 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0012[Correction target item name] 0012

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【発明の効果】表から明らかなように、基板と表面実
装部品の熱膨張の差に基づく応力をブチラール変性フェ
ノール樹脂の層が吸収して、半田接続部に前記応力に起
因するクラックが発生するのを防止することができる。
そして、他の特性は、従来のガラス織布基材エポキシ樹
脂積層板と同等である。
As is clear from Table 2 , the butyral-modified phenolic resin layer absorbs the stress caused by the difference in thermal expansion between the substrate and the surface-mounted component, and the solder joint is cracked due to the stress. Can be prevented.
And other characteristics are the same as the conventional glass woven fabric-based epoxy resin laminate.

【手続補正書】[Procedure amendment]

【提出日】平成6年3月1日[Submission date] March 1, 1994

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0006[Correction target item name] 0006

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0006】[0006]

【実施例】実施例1 0.2mm厚さのガラス織布に臭素化ビスフェノールA型
エポキシ樹脂を含浸乾燥して得たプリプレグを8枚重
ね、その両側に25μ厚さのブチラール変性フェノール
樹脂シートを配し、最外層には18μmの銅箔を配し
て、温度165℃、圧力30Kgf/cm2で50分間加熱加
圧成形して1.6mm厚さの銅張り積層板とした。この積
層板に、以下の工程にて配線板加工を行った。所定位置
にスルホール加工をした後、エッチングにより回路形成
をし、最終仕上げとして半田レベラー処理を行った。部
品の実装および半田付け工程は、リフロー面およびフロ
ー面にセラミックチップ抵抗(4532タイプ)を搭載
し、遠赤外リフロー半田付け(クリーム半田)し、その
後フロー半田付け(溶融半田)をした。半田接続部の初
期の表面状態を観察した後、−30℃/30分と80℃
/30分の気層冷熱サイクル試験を行い、半田接続部の
クラック発生状況を観察した。その結果を他の特性と共
に表2に示すが、表1には基板とブチラール変性フェノ
ール樹脂層の弾性率を参考までに示した。ブチラール変
性フェノール樹脂層は、30℃においても基板の約1/
00の弾性率である。
Example 1 Eight prepregs obtained by impregnating a 0.2 mm-thick glass woven cloth with a brominated bisphenol A type epoxy resin and drying the prepregs were laminated with a 25 μ-thick butyral-modified phenolic resin sheet on both sides. Then, a copper foil of 18 μm was placed on the outermost layer, and heat and pressure molding was performed at a temperature of 165 ° C. and a pressure of 30 Kgf / cm 2 for 50 minutes to obtain a 1.6 mm thick copper clad laminate. Wiring board processing was performed on this laminated board in the following steps. After the through hole processing at a predetermined position, a circuit was formed by etching, and a solder leveler process was performed as a final finish. In the component mounting and soldering steps, a ceramic chip resistor (4532 type) was mounted on the reflow surface and the flow surface, far infrared reflow soldering (cream solder) was performed, and then flow soldering (molten solder) was performed. After observing the initial surface condition of the solder joint, -30 ℃ / 30 minutes and 80 ℃
A vapor phase cooling / heating cycle test was performed for / 30 minutes, and the occurrence of cracks at the solder joints was observed. The results are shown in Table 2 together with other properties. In Table 1, the elastic moduli of the substrate and the butyral-modified phenolic resin layer are shown for reference. The butyral modified phenolic resin layer is about 1 / th of the substrate even at 30 ° C.
5, which is a 00 modulus of elasticity.

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0008[Correction target item name] 0008

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0008】[0008]

【表1】 [Table 1]

【手続補正3】[Procedure 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0012[Correction target item name] 0012

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0012】[0012]

【発明の効果】表から明らかなように、基板と表面実
装部品の熱膨張の差に基づく応力をブチラール変性フェ
ノール樹脂の層が吸収して、半田接続部に前記応力に起
因するクラックが発生するのを防止することができる。
そして、他の特性は、従来のガラス織布基材エポキシ樹
脂積層板と同等である。
As is clear from Table 2 , the butyral-modified phenolic resin layer absorbs the stress caused by the difference in thermal expansion between the substrate and the surface-mounted component, and the solder joint is cracked due to the stress. Can be prevented.
And other characteristics are the same as the conventional glass woven fabric-based epoxy resin laminate.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】エポキシ樹脂含浸ガラス織布基材層を基板
としその表面に銅箔を一体に設けた銅張り積層板におい
て、銅箔の内側に、これと接してブチラール変性フェノ
ール樹脂の層を形成した表面実装プリント配線板用銅張
り積層板。
1. A copper-clad laminate having an epoxy resin-impregnated glass woven base material layer as a substrate, and a copper foil integrally provided on the surface thereof, wherein a butyral-modified phenolic resin layer is provided inside the copper foil and in contact therewith. The formed copper-clad laminate for surface-mounted printed wiring boards.
JP14910591A 1991-06-21 1991-06-21 Copper-clad laminated board for surface mounting printed wiring board Pending JPH06204632A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14910591A JPH06204632A (en) 1991-06-21 1991-06-21 Copper-clad laminated board for surface mounting printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14910591A JPH06204632A (en) 1991-06-21 1991-06-21 Copper-clad laminated board for surface mounting printed wiring board

Publications (1)

Publication Number Publication Date
JPH06204632A true JPH06204632A (en) 1994-07-22

Family

ID=15467810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14910591A Pending JPH06204632A (en) 1991-06-21 1991-06-21 Copper-clad laminated board for surface mounting printed wiring board

Country Status (1)

Country Link
JP (1) JPH06204632A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6504240B2 (en) 1999-12-20 2003-01-07 Nec Corporation Semiconductor device having reliable coupling between wiring substrate and semiconductor pellet

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS529865A (en) * 1975-07-14 1977-01-25 Matsushita Electric Works Ltd Method of manufacturing substrate for coating surface
JPS5828848A (en) * 1981-05-06 1983-02-19 アイ・テイ・テイ・インダストリ−ズ・インコ−ポレ−テツド Integrated circuit, semiconductor device and method of mounting component
JPS63264342A (en) * 1987-04-22 1988-11-01 Shin Kobe Electric Mach Co Ltd Copper plated laminate and its manufacture
JPH02217240A (en) * 1989-02-20 1990-08-30 Matsushita Electric Works Ltd Surface mounting laminated sheet

Patent Citations (4)

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JPS63264342A (en) * 1987-04-22 1988-11-01 Shin Kobe Electric Mach Co Ltd Copper plated laminate and its manufacture
JPH02217240A (en) * 1989-02-20 1990-08-30 Matsushita Electric Works Ltd Surface mounting laminated sheet

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6504240B2 (en) 1999-12-20 2003-01-07 Nec Corporation Semiconductor device having reliable coupling between wiring substrate and semiconductor pellet

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