JPH06204548A - Light-sensing semiconductor device, manufacture thereof and photocoupler using same - Google Patents

Light-sensing semiconductor device, manufacture thereof and photocoupler using same

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Publication number
JPH06204548A
JPH06204548A JP35068292A JP35068292A JPH06204548A JP H06204548 A JPH06204548 A JP H06204548A JP 35068292 A JP35068292 A JP 35068292A JP 35068292 A JP35068292 A JP 35068292A JP H06204548 A JPH06204548 A JP H06204548A
Authority
JP
Japan
Prior art keywords
light
light receiving
semiconductor substrate
receiving elements
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP35068292A
Other languages
Japanese (ja)
Other versions
JP2687831B2 (en
Inventor
Toshio Araki
俊雄 荒木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP35068292A priority Critical patent/JP2687831B2/en
Publication of JPH06204548A publication Critical patent/JPH06204548A/en
Application granted granted Critical
Publication of JP2687831B2 publication Critical patent/JP2687831B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Light Receiving Elements (AREA)
  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)

Abstract

PURPOSE:To make it possible to change a current transfer rate by changing a wiring and to construct two light-sensing circuits in the case when a light- sensing semiconductor device is applied to a photocoupler. CONSTITUTION:Array-shaped photodiodes 1 and two transistors 2 are provided in a chip, while bonding pads (3 to 6) are disposed at four corners of the chip, and they are connected by Al wirings 7. By changing the number of the photodiodes connected in parallel, the sensitivity of a light-sensing semiconductor device (the current transfer rate of a photo-coupler, accordingly, when the device is applied thereto) can be changed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、マトリックス状に配置
された複数のフォトダイオードを有する受光半導体装
置、その製造方法およびそれを用いた光結合装置(フォ
トカプラ、フォトインタラプタ等)に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light receiving semiconductor device having a plurality of photodiodes arranged in a matrix, a method for manufacturing the same and an optical coupling device (photo coupler, photo interrupter, etc.) using the same.

【0002】[0002]

【従来の技術】図7の(a)は、光結合装置に用いられ
ている従来の受光半導体装置の平面図であり、図7の
(b)はその等価回路図である。従来の受光半導体装置
では、同図に示されるように、フォトダイオード1aと
トランジスタ2aとが1個ずつ設けられ、またチップの
四隅には出力端子3、電源端子4、予備端子5、GND
端子6となるボンディングパッドがそれぞれ配置され、
これら各素子間と各端子とがAl配線7により接続され
ていた。
2. Description of the Related Art FIG. 7A is a plan view of a conventional light receiving semiconductor device used in an optical coupling device, and FIG. 7B is an equivalent circuit diagram thereof. In the conventional light receiving semiconductor device, as shown in the figure, one photodiode 1a and one transistor 2a are provided, and an output terminal 3, a power supply terminal 4, a spare terminal 5, and a GND are provided at four corners of the chip.
Bonding pads to be terminals 6 are arranged respectively,
These elements were connected to each terminal by an Al wiring 7.

【0003】従来の受光用半導体装置は、サブストレー
ト上にエピタキシャル層を形成した後に、図3の(b)
で示す複数フォトリピータ(フォトリソグラフィ工程、
エッチング工程、拡散工程等を含む一組みの工程、以
下、PRと記す)工程を経て形成されてきた。即ち、必
要に応じてn+ 埋め込み層の形成されたp型サブストレ
ート上にn型エピタキシャル層を形成した後、素子分離
領域となるp+ 型拡散層を形成する素子分離PR、コレ
クタ取り出し領域およびフォトダイオードのカソード取
り出し領域を形成するコレクタ・リン拡散PR、ベース
領域およびフォトダイオードのアノード領域を形成する
ボロン拡散PR、エミッタ領域を形成するエミッタ・リ
ン拡散PR、コンタクト孔PR、Al配線PR、ボンデ
ィングパッドPRの諸工程を実行する。
In the conventional light-receiving semiconductor device, an epitaxial layer is formed on a substrate, and then the light-receiving semiconductor device shown in FIG.
Multiple photo repeaters (photolithography process,
It has been formed through a set of processes including an etching process, a diffusion process, and the like (hereinafter referred to as PR) process. That is, after forming an n-type epitaxial layer on a p-type substrate on which an n + buried layer is formed, if necessary, an element isolation PR for forming a p + type diffusion layer serving as an element isolation region, a collector extraction region, and Collector / phosphorus diffusion PR forming the cathode extraction region of the photodiode, boron diffusion PR forming the base region and anode region of the photodiode, emitter / phosphorus diffusion PR forming the emitter region, contact hole PR, Al wiring PR, bonding The steps of pad PR are executed.

【0004】而して、光結合装置では、機種に応じて要
求される電流伝達率(Current Transfer Ratio:以下、
CTRと記す)が異なるため、従来の受光半導体装置で
はこれに応えるためにエミッタ領域の拡散深さに変更を
加えてきた。図8は、エミッタ・リン拡散PRにおける
拡散時間とCTRとの関係を示すグラフである。エミッ
タ拡散時間に応じてベース幅が、従ってトランジスタの
FEが変化するため、CTRは拡散時間に従ってほぼ直
線的に変化する。
In the optical coupling device, the current transfer ratio (Current Transfer Ratio:
In the conventional light receiving semiconductor device, the diffusion depth of the emitter region has been changed in order to respond to this. FIG. 8 is a graph showing the relationship between the diffusion time and the CTR in the emitter / phosphorus diffusion PR. The CTR varies almost linearly with diffusion time because the base width, and thus the transistor h FE , varies with emitter diffusion time.

【0005】従来の製法では、ボロン拡散PR(ベース
拡散工程)が終了した状態のウェハを中間在庫品として
保有しておき、製造すべき光結合装置のCTRが決定さ
れるとそれに応じてエミッタ拡散時間を決定し、エミッ
タ・リンPR以降の4つのPR工程を実行することによ
り所望の特性の受光半導体装置を得てきた。
In the conventional manufacturing method, a wafer in which boron diffusion PR (base diffusion process) has been completed is held as an intermediate stock product, and when the CTR of the optical coupling device to be manufactured is determined, the emitter diffusion is performed accordingly. The light receiving semiconductor device having desired characteristics has been obtained by determining the time and performing the four PR steps after the emitter phosphorus PR.

【0006】[0006]

【発明が解決しようとする課題】上述した従来の受光半
導体装置では、フォトカプラのCTRが決定されてから
受光半導体装置の製造が完了する迄に少なくとも4つの
PR工程が必要となるため、製品を得る迄の時間が長く
かかるという問題点があった。また、従来の受光半導体
装置は、フォトダイオードとトランジスタとを各1個ず
つしか内蔵していなかったため、受光回路は図7の
(b)に示されるように、1回路しか構成できず、一つ
の製品で多用な用途に応じることは不可能なことであっ
た。
In the above-described conventional light receiving semiconductor device, at least four PR steps are required from the determination of the CTR of the photocoupler to the completion of the manufacture of the light receiving semiconductor device. There was a problem that it took a long time to get it. Further, since the conventional light receiving semiconductor device has only one photodiode and one transistor built therein, the light receiving circuit can be configured with only one circuit as shown in FIG. 7B. It was impossible for the product to meet a variety of uses.

【0007】[0007]

【課題を解決するための手段】本発明の受光半導体装置
は、半導体基板の表面領域内に複数の受光素子が規則的
に配置され、その中の選択された受光素子が金属配線を
介してトランジスタに接続されてたものである。
In a light receiving semiconductor device of the present invention, a plurality of light receiving elements are regularly arranged in a surface region of a semiconductor substrate, and a selected light receiving element among them is a transistor via a metal wiring. It was connected to.

【0008】そして、この受光半導体装置は、各チップ
内にトランジスタと規則的配列状態にある複数のフォト
ダイオードとを形成し、基板表面を絶縁膜で被覆し、コ
ンタクト孔開設のためのフォトリソグラフィ工程を施し
た後、上記各工程の施されたウェハを中間在庫品として
保管しておく第1の段階と、求められる製品の特性に応
じて前記複数のフォトダイオードの中から配線を施すべ
きフォトダイオードを決定し、その決定に基づいてAl
配線を形成する第2の段階と、を経て製造されるもので
ある。
In this light receiving semiconductor device, a transistor and a plurality of photodiodes in a regular array are formed in each chip, the surface of the substrate is covered with an insulating film, and a photolithography process for opening a contact hole is performed. After performing the above steps, a first step of storing the wafers subjected to the above-mentioned steps as an intermediate inventory product, and a photodiode to which wiring is to be provided from among the plurality of photodiodes according to the required characteristics of the product Al based on that decision
It is manufactured through the second step of forming wiring.

【0009】[0009]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。図1は、本発明の一実施例の受光半導体装
置の平面図である(但し、Al配線の図示は省略されて
いる)。同図に示されるように、チップ中央部には、ほ
ぼ正方形の複数のフォトダイオード1が規則的配列状態
で形成され、またチップ下部には2個のトランジスタ2
が形成されている。チップの四隅には、出力端子3、電
源端子4、予備端子5およびGND端子6となるボンデ
ィングパッドが配置されている。
Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a plan view of a light receiving semiconductor device according to an embodiment of the present invention (however, Al wiring is not shown). As shown in the figure, a plurality of substantially square photodiodes 1 are formed in a regular array in the central part of the chip, and two transistors 2 are formed in the lower part of the chip.
Are formed. Bonding pads serving as an output terminal 3, a power supply terminal 4, a spare terminal 5 and a GND terminal 6 are arranged at the four corners of the chip.

【0010】図2の(a)は、図1のフォトダイオード
部分の拡大図である。フォトダイオード1は素子分離領
域10により分離・区画されて形成されている。素子分
離領域10上にはアノードAl配線7aと電源Al配線
7bとが敷設されており、これら各Al配線は各フォト
ダイオードのアノード領域とカソード領域とに接続され
ている。
FIG. 2A is an enlarged view of the photodiode portion of FIG. The photodiode 1 is formed by being separated and divided by the element separation region 10. An anode Al wiring 7a and a power Al wiring 7b are laid on the element isolation region 10, and these Al wirings are connected to the anode region and the cathode region of each photodiode.

【0011】図2の(b)は、図2の(a)のX−Y線
断面図である。図2の(b)に示されるように、p型サ
ブストレート8上にはn型エピタキシャル層9が形成さ
れており、各フォトダイオード1はn型エピタキシャル
層を貫通する素子分離領域(p+ 型拡散層)10に囲繞
されて形成されている。フォトダイオードのカソード取
り出し領域であるn+ 型拡散層11は電源Al配線7b
に接続され、フォトダイオードのアノード領域であるp
型拡散層12はアノードAl配線7aに接続されてい
る。
FIG. 2B is a sectional view taken along line XY of FIG. As shown in FIG. 2B, an n-type epitaxial layer 9 is formed on the p-type substrate 8, and each photodiode 1 has an element isolation region (p + -type) penetrating the n-type epitaxial layer. It is formed so as to be surrounded by a diffusion layer 10. The n + type diffusion layer 11 which is the cathode extraction region of the photodiode is the power source Al wiring 7b.
Connected to p, which is the anode region of the photodiode
The type diffusion layer 12 is connected to the anode Al wiring 7a.

【0012】次に、図3の(a)の流れ図に従って、図
2に示す本実施例の受光半導体装置の製造方法について
説明する。p型サブストレート8上に必要に応じて選択
的にn+ 型埋め込み層(図示なし)を形成した後、n型
エピタキシャル層9を成長させる。次に、素子分離PR
において、ボロンを高濃度にイオン注入して素子分離領
域10を形成し、コレクタ・リン拡散PRにおいて、コ
レクタ取り出し領域と、フォトダイオードのカソード取
り出し領域となるn+ 型拡散層11を形成する。
Next, a method of manufacturing the light receiving semiconductor device of this embodiment shown in FIG. 2 will be described with reference to the flow chart of FIG. An n + type buried layer (not shown) is selectively formed on the p type substrate 8 if necessary, and then an n type epitaxial layer 9 is grown. Next, element isolation PR
At this time, boron is ion-implanted at a high concentration to form the element isolation region 10, and in the collector / phosphorus diffusion PR, the collector lead-out region and the n + type diffusion layer 11 to be the cathode lead-out region of the photodiode are formed.

【0013】次に、ボロン拡散PRにおいて、トランジ
スタのベース領域およびフォトダイオードのアノード領
域となるp型拡散層12を形成し、続くエミッタ・リン
拡散PRにおいて、エミッタ領域を形成する。ここで、
ウェハ上に下層が酸化膜、上層が窒化膜となる絶縁膜を
形成し、コンタクト孔PRにおいて、窒化膜にコンタク
ト孔を開設する。そしてこの状態で中間在庫品として保
管しておく。
Next, in the boron diffusion PR, the p-type diffusion layer 12 to be the base region of the transistor and the anode region of the photodiode is formed, and in the subsequent emitter / phosphorus diffusion PR, the emitter region is formed. here,
An insulating film whose lower layer is an oxide film and whose upper layer is a nitride film is formed on the wafer, and a contact hole is formed in the nitride film in the contact hole PR. Then, it is stored as an intermediate stock item in this state.

【0014】この受光半導体装置では、フォトダイオー
ドの並列接続個数を変化させることにより、感度を、従
って、光結合装置に応用した場合にはそのCTRをほぼ
直線的に変化させることができる。従って、この受光半
導体装置が使用される光結合装置のCTRが決定される
と、それに応じてフォトダイオード並列接続個数が決定
され、形成すべきAl配線のパターンが決まる。Al配
線PRに先立って、コンタクト孔内の酸化膜をエッチン
グ除去し、蒸着法により全面にAlを被着する。Al配
線PRでは、決定されたパターンのAl配線7a、7b
およびボンディングパッド(端子3〜6)を形成する。
Al配線上を絶縁膜で被覆した後、ボンディングパッド
PRでボンディングパッド上の絶縁膜を除去する。
In this light receiving semiconductor device, by changing the number of photodiodes connected in parallel, it is possible to change the sensitivity, and thus the CTR, when applied to an optical coupling device, in a substantially linear manner. Therefore, when the CTR of the optical coupling device in which this light receiving semiconductor device is used is determined, the number of photodiodes connected in parallel is determined, and the pattern of Al wiring to be formed is determined. Prior to the Al wiring PR, the oxide film in the contact hole is removed by etching, and Al is deposited on the entire surface by vapor deposition. In the Al wiring PR, the Al wirings 7a and 7b having the determined pattern
And bonding pads (terminals 3 to 6) are formed.
After covering the Al wiring with the insulating film, the insulating film on the bonding pad is removed by the bonding pad PR.

【0015】図4の(a)は、本実施例の配線例を示す
平面図であり(但し、フォトダイオード部の配線は省
略、以下同様)、図4の(b)はその等価回路図であ
る。この回路は、図7の(b)に示した従来の受光回路
と回路形式は同様である。但し、従来例でのフォトダイ
オードが本実施例では、フォトダイオードアレイになっ
ている。
FIG. 4A is a plan view showing a wiring example of the present embodiment (however, the wiring of the photodiode portion is omitted, the same applies hereinafter), and FIG. 4B is an equivalent circuit diagram thereof. is there. This circuit has the same circuit form as the conventional light receiving circuit shown in FIG. However, the photodiode in the conventional example is a photodiode array in this embodiment.

【0016】図5の(a)は、他の配線例を示す平面図
であり、図5の(b)は、その等価回路図である。本実
施例では、電源端子を2つ設け、それぞれの電源端子に
接続されるフォトダイオードの数を異ならせておく。こ
のように構成すれば、受光半導体装置が完成した後に、
電源端子4を使用する、予備端子5を電源端子とし
て用いる、端子4と端子5とを接続して使用する、の
中から用途に応じて適切な回路を選択することができ
る。
FIG. 5A is a plan view showing another wiring example, and FIG. 5B is an equivalent circuit diagram thereof. In this embodiment, two power supply terminals are provided and the number of photodiodes connected to each power supply terminal is made different. According to this structure, after the light receiving semiconductor device is completed,
An appropriate circuit can be selected from among using the power supply terminal 4, using the spare terminal 5 as a power supply terminal, and connecting and using the terminal 4 and the terminal 5 according to the application.

【0017】図6の(a)は、さらにもう一つの配線例
を示す平面図であり、図6の(b)はその等価回路図で
ある。この回路例では、2つのトランジスタに、それぞ
れフォトダイオードの並列回路と出力端子が接続され、
2個の受光回路が構成されている。受光半導体装置をこ
のように構成すれば、端子3、端子5のうちいずれか
の端子を使用する、一つの光結合装置から2出力を得
る、端子3、5を並列に接続して大電流容量の回路を
構成する、等の利用が可能となる。
FIG. 6A is a plan view showing another wiring example, and FIG. 6B is an equivalent circuit diagram thereof. In this circuit example, two parallel transistors and output terminals are connected to the two transistors,
Two light receiving circuits are configured. According to this structure of the light-receiving semiconductor device, one of the terminals 3 and 5 is used, two outputs are obtained from one optical coupling device, and the terminals 3 and 5 are connected in parallel to have a large current capacity. It is possible to use such as configuring the circuit of.

【0018】[0018]

【発明の効果】以上説明したように、本発明の受光半導
体装置は、マトリックス状に配置された複数のフォトダ
イオードを備え、Al配線によってその接続個数を変え
ることができるようにしたものであるので、本発明によ
れば、Al配線PRでのパターンを変更するのみで、要
求される感度の受光半導体装置を製造することが可能と
なる。従って、本発明によれば、エミッタ拡散終了後の
ウェハを中間在庫品として保有しておき、光結合装置の
CTR等の用途別の感度要求がなされた後に、2つのP
R工程を実行するのみで製品を提供することが可能とな
り、従来例の場合よりもTAT(turn around time)を
短縮することができる。
As described above, the light-receiving semiconductor device of the present invention is provided with a plurality of photodiodes arranged in a matrix, and the number of the connected photodiodes can be changed by the Al wiring. According to the present invention, it is possible to manufacture a light-receiving semiconductor device having a required sensitivity simply by changing the pattern of the Al wiring PR. Therefore, according to the present invention, the wafer after the completion of the emitter diffusion is held as an intermediate stock product, and after the sensitivity request for each application such as CTR of the optical coupling device is made, the two P
The product can be provided only by executing the R process, and the TAT (turn around time) can be shortened as compared with the case of the conventional example.

【0019】また、エミッタ拡散時間を調整して所望の
感度の受光半導体装置を製造する従来例と比較して、よ
り高い精度で感度調整を行うことができる。さらに、同
一チップ上に複数のトランジスタを設けたので、本発明
によれば、一つの受光半導体装置に複数の受光回路を内
蔵させることができるようになり、多様な用途に対応す
ることが可能となる。
Further, the sensitivity can be adjusted with higher precision as compared with the conventional example in which the emitter diffusion time is adjusted to manufacture a light receiving semiconductor device having a desired sensitivity. Further, since a plurality of transistors are provided on the same chip, according to the present invention, a plurality of light receiving circuits can be built in one light receiving semiconductor device, and it is possible to cope with various applications. Become.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の一実施例の平面図。FIG. 1 is a plan view of an embodiment of the present invention.

【図2】 図1のフォトダイオード部分の拡大図とその
断面図。
FIG. 2 is an enlarged view of a photodiode portion of FIG. 1 and a sectional view thereof.

【図3】 製造工程中のPR工程を主とした流れ図。FIG. 3 is a flowchart mainly showing a PR process in a manufacturing process.

【図4】 図1の実施例に対するAl配線例を示す平面
図とその等価回路図。
FIG. 4 is a plan view showing an Al wiring example for the embodiment of FIG. 1 and its equivalent circuit diagram.

【図5】 図1の実施例に対するAl配線例を示す平面
図とその等価回路図。
5A and 5B are a plan view and an equivalent circuit diagram showing an Al wiring example for the embodiment of FIG.

【図6】 図1の実施例に対するAl配線例を示す平面
図とその等価回路図。
6 is a plan view showing an example of Al wiring for the embodiment of FIG. 1 and its equivalent circuit diagram. FIG.

【図7】 従来例の平面図とその等価回路図。FIG. 7 is a plan view of a conventional example and its equivalent circuit diagram.

【図8】 エミッタ拡散時間とCTRとの関係を示すグ
ラフ。
FIG. 8 is a graph showing the relationship between emitter diffusion time and CTR.

【符号の説明】[Explanation of symbols]

1、1a フォトダイオード 2、2a トランジスタ 3 出力端子 4 電源端子 5 予備端子 6 GND端子 7 Al配線 7a アノードAl配線 7b 電源Al配線 8 p型サブストレート 9 n型エピタキシャル層 10 素子分離領域 11 n+ 型拡散層 12 p型拡散層1, 1a Photodiode 2, 2a Transistor 3 Output terminal 4 Power supply terminal 5 Spare terminal 6 GND terminal 7 Al wiring 7a Anode Al wiring 7b Power supply Al wiring 8 p-type substrate 9 n-type epitaxial layer 10 Element isolation region 11 n + type Diffusion layer 12 p-type diffusion layer

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板の表面領域内に複数の受光素
子が規則的に配置され、その中の選択された受光素子が
金属配線を介してトランジスタと接続されている受光半
導体装置。
1. A light receiving semiconductor device in which a plurality of light receiving elements are regularly arranged in a surface region of a semiconductor substrate, and a selected light receiving element among them is connected to a transistor through a metal wiring.
【請求項2】 半導体基板の表面領域内に規則的配列で
配置された複数の受光素子と、前記半導体基板の表面領
域内に配置されたトランジスタと、前記半導体基板上に
配置されたボンディングパッドと、を備え、 金属配線により、前記受光素子のうち選択された受光素
子が並列接続の態様で前記トランジスタと前記ボンディ
ングパッドとに接続されている受光半導体装置。
2. A plurality of light-receiving elements arranged in a surface region of the semiconductor substrate in a regular array, transistors arranged in the surface region of the semiconductor substrate, and bonding pads arranged on the semiconductor substrate. And a light-receiving semiconductor device in which a light-receiving element selected from the light-receiving elements is connected to the transistor and the bonding pad in parallel by a metal wiring.
【請求項3】 半導体基板の表面領域内に規則的配列で
配置された複数の受光素子と、前記半導体基板の表面領
域内配置された少なくとも2個のトランジスタと、前記
半導体基板上に配置された複数のボンディングパッド
と、を備え、 前記受光素子のうちの第1群の受光素子が、金属配線に
より、並列接続の態様で第1のトランジスタと第1のボ
ンディングパッドとに接続され、 前記受光素子のうちの第2群の受光素子が、金属配線に
より、並列接続の態様で前記第1のトランジスタとは異
なる第2のトランジスタと前記第1のボンディングパッ
ドとに接続されている受光半導体装置。
3. A plurality of light receiving elements arranged in a regular array in a surface region of a semiconductor substrate, at least two transistors arranged in a surface region of the semiconductor substrate, and a plurality of light receiving elements arranged on the semiconductor substrate. A plurality of bonding pads, wherein the first group of light receiving elements of the light receiving elements are connected to the first transistor and the first bonding pad in a parallel connection mode by metal wiring, The light receiving semiconductor device in which the second group of light receiving elements is connected to a second transistor different from the first transistor and the first bonding pad in a parallel connection mode by metal wiring.
【請求項4】 半導体基板の表面領域内に規則的配列で
配置された複数の受光素子と、前記半導体基板の表面領
域内に配置されたトランジスタと、前記半導体基板上に
配置された複数のボンディングパッドと、を備え、 前記受光素子のうちの第1群の受光素子が、金属配線に
より、並列接続の態様で前記トランジスタと第1のボン
ディングパッドとに接続され、 前記受光素子のうちの第2群の受光素子が、金属配線に
より、並列接続の態様で前記トランジスタと前記第1ボ
ンディングパッドとは異なる第2のボンディングパッド
とに接続されている受光半導体装置。
4. A plurality of light-receiving elements arranged in a surface region of the semiconductor substrate in a regular array, transistors arranged in the surface region of the semiconductor substrate, and a plurality of bondings arranged on the semiconductor substrate. A pad, the first group of light receiving elements of the light receiving elements are connected to the transistor and the first bonding pad in a parallel connection by metal wiring, and the second group of the light receiving elements A light-receiving semiconductor device in which a group of light-receiving elements is connected to the transistor and a second bonding pad different from the first bonding pad in a parallel connection mode by metal wiring.
【請求項5】 各チップ内にトランジスタと規則的配列
状態にある複数のフォトダイオードとを形成し、基板表
面を絶縁膜で被覆し、コンタクト孔開設のためのフォト
リソグラフィ工程を施した後、上記各工程の施されたウ
ェハを中間在庫品として保管しておく第1の段階と、 求められる製品の特性に応じて前記複数のフォトダイオ
ードの中から配線を施すべきフォトダイオードを決定
し、その決定に基づいてAl配線を形成する第2の段階
と、 を含む受光半導体装置の製造方法。
5. A transistor and a plurality of photodiodes in a regular array are formed in each chip, a substrate surface is covered with an insulating film, and a photolithography process for opening a contact hole is performed. The first step is to store the wafer that has undergone each process as an intermediate inventory product, and the photodiode to be wired is determined from the plurality of photodiodes according to the required product characteristics, and the determination is made. A second step of forming an Al wiring based on the above, and a method for manufacturing a light receiving semiconductor device, comprising:
【請求項6】 発光素子と、 半導体基板の表面領域内に規則的配列で配置された複数
の受光素子と、前記半導体基板の表面領域内に配置され
たトランジスタと、前記半導体基板上に配置されたボン
ディングパッドと、を備え、金属配線により、前記受光
素子のうち選択された受光素子が並列接続の態様で前記
トランジスタと前記ボンディングパッドとに接続されて
いる受光半導体装置と、 が同一容器内に光学的に結合されて配置されている光結
合装置。
6. A light emitting device, a plurality of light receiving devices arranged in a surface region of the semiconductor substrate in a regular array, transistors arranged in the surface region of the semiconductor substrate, and a transistor arranged on the semiconductor substrate. And a light-receiving semiconductor device in which the light-receiving element selected from the light-receiving elements is connected in parallel to the transistor and the bonding pad by metal wiring in the same container. An optical coupling device that is optically coupled and arranged.
JP35068292A 1992-12-04 1992-12-04 Light receiving semiconductor device, method of manufacturing the same, and optical coupling device using the same Expired - Lifetime JP2687831B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35068292A JP2687831B2 (en) 1992-12-04 1992-12-04 Light receiving semiconductor device, method of manufacturing the same, and optical coupling device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35068292A JP2687831B2 (en) 1992-12-04 1992-12-04 Light receiving semiconductor device, method of manufacturing the same, and optical coupling device using the same

Publications (2)

Publication Number Publication Date
JPH06204548A true JPH06204548A (en) 1994-07-22
JP2687831B2 JP2687831B2 (en) 1997-12-08

Family

ID=18412135

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2687831B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2726691A1 (en) * 1994-11-08 1996-05-10 Thomson Csf LARGE-DIMENSIONAL PHOTODETECTOR AND METHOD FOR PRODUCING SUCH A PHOTODETECTOR
JP2006245180A (en) * 2005-03-02 2006-09-14 Texas Instr Japan Ltd Semiconductor device and inspection method thereof
EP2249388A3 (en) * 1999-05-11 2012-08-22 Yokogawa Electric Corporation Photo diode array

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5986257A (en) * 1982-11-10 1984-05-18 Hitachi Ltd Photosensor array device
JPS60167477A (en) * 1984-02-10 1985-08-30 Hitachi Ltd Photosensor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5986257A (en) * 1982-11-10 1984-05-18 Hitachi Ltd Photosensor array device
JPS60167477A (en) * 1984-02-10 1985-08-30 Hitachi Ltd Photosensor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2726691A1 (en) * 1994-11-08 1996-05-10 Thomson Csf LARGE-DIMENSIONAL PHOTODETECTOR AND METHOD FOR PRODUCING SUCH A PHOTODETECTOR
EP0712166A1 (en) * 1994-11-08 1996-05-15 Thomson-Csf Large size photodetector and method of manufacturing the same
EP2249388A3 (en) * 1999-05-11 2012-08-22 Yokogawa Electric Corporation Photo diode array
JP2006245180A (en) * 2005-03-02 2006-09-14 Texas Instr Japan Ltd Semiconductor device and inspection method thereof

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