JPH0620311A - Multi-probe head - Google Patents

Abstract

PURPOSE:To obtain a multi-probe head used for a recoding and reproducing device using the principle of a scanning type electron microscope, forming a read/write circuit on the same substrate as a probe electrode and reading a signal from the probe electrode with a high S/N. CONSTITUTION:The probe electrode Pi,j is connected to the base of a transistor TRi,j, and an analog switch SBi.j for applying bias voltage to the probe electrode Pi,j is provided. Further, the analog switch SAi,j is provided on the emitter side of the transistor TRi,j. By detecting the flowing out of charge stored in the base capacitance of the transistor TRi,j as tunnel current by an emitter follower circuit consisting of the transistor TRi,j, the signal is read from the probe electrode Pi,j.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-probe head used in a device for recording and / or reproducing data by physical interaction between a plurality of probe electrodes and a recording medium, and more particularly to a scanning tunnel electron. The present invention relates to a multi-probe head used in a high-density and large-capacity recording / reproducing device that utilizes the principle of a microscope.

[0002]

2. Description of the Related Art Memory material technology is at the core of the electronics industry such as computers and their peripherals, video discs, digital audio discs, etc., and memory material development has been extremely active in recent years. There is. Conventionally, magnetic memories and semiconductor memories made of magnetic materials or semiconductors have been the mainstream of memory, but with the development of laser technology, optical memories using organic thin films such as organic dyes and photopolymers have appeared. There is. The optical memory is an inexpensive recording medium having a high recording density.

On the other hand, a scanning tunneling electron microscope (Scanning Tunneli Microscope) capable of directly observing the electronic structure of surface atoms of a conductor.
ng Microscope, hereinafter abbreviated as STM. ) Was developed [G. Binnig et al., Phys. Rev. Lett., 4
9 , 57 (1982)], whether single crystal or amorphous,
It became possible to measure real space images with high resolution. Further, the STM has the advantage that it can be observed at low power without damaging the sample with an electric current and operates in the atmosphere, and is expected to have a wide range of applications.

In the STM, a voltage is applied between a metallic probe (probe electrode) and a conductive substance which is a sample, so that both are set to 1
The fact that a tunnel current flows between the two is used when they are brought close to a distance of about nm. Since this current responds exponentially to changes in the distance between the two, the STM is very sensitive to surface conditions. Further, by scanning the probe so as to keep the tunnel current constant, various information regarding all electron clouds in the real space can also be read.
At this time, the resolution in the in-plane direction is about 0.1 nm. Therefore, if the principle of STM is applied, it is possible to sufficiently perform high-density recording and reproduction on the atomic order (sub-nanometer). For example, Japanese Patent Application Laid-Open No. 61-80563 discloses a recording / reproducing apparatus in which atomic particles adsorbed on the surface of a recording medium are removed by an electron beam or the like to write data and the data is read by STM.

As a recording layer, a method has been proposed in which a material having a memory effect on voltage-current switching characteristics, for example, a thin film layer of a conjugated π-electron organic compound or a chalcogen compound is used, and recording and reproduction are performed by using STM. (Japanese Patent Laid-Open Nos. 63-161552 and 63-161553). That is, by applying a voltage exceeding the threshold value, these recording layers can transit between two different states depending on the polarity at the time of application, and these states remain stable when no voltage is applied. . Then, it is possible to detect in which state the difference is in the tunnel current value when the distance between the surface of the recording layer and the probe is constant. Since a voltage exceeding the threshold value can be applied to the recording layer by using the probe for detecting the tunnel current, binary recording and reproduction of information can be performed at a recording density corresponding to the in-plane resolution of the STM. . According to this method, if the recording bit size is 10 nm, a large capacity recording and reproducing of 10 ¹² bits / cm ² are possible. Further, for the purpose of downsizing, an apparatus has been proposed in which a plurality of probe electrodes are formed on a semiconductor substrate and a recording medium facing the probe electrodes is displaced to perform recording (Japanese Patent Laid-Open No. 62-281138, Japanese Laid-Open Patent Publication No. 196751 publications). For example, by combining the multi-probe head in which 2500 probes are arranged in a matrix of 50 × 50 on a 1 cm square silicon chip and the above-mentioned recording material having a memory effect, it is possible to obtain 40 probes per probe electrode.
It is possible to record / reproduce digital data having 0 M bits and a total recording capacity of 1 T (tera) bits.

[0006]

However, when recording / reproducing information by combining a multi-probe head having a plurality of probe electrodes with the above-mentioned recording material having a memory effect, the following problems occur. Was occurring. In the multi-probe head, it is necessary to control the distance between each probe electrode and the distance between each probe electrode and the recording medium with high accuracy, and therefore the effect of thermal expansion must be eliminated, so it is necessary to suppress the amount of heat generation as much as possible. There is. Therefore, the read / write circuit formed on the multi-probe head must have a circuit configuration with less heat generation. Conventionally, as a readout circuit, a current detection type which uses a low input bias current and a high-speed operation OP amplifier has been used, but this circuit is monolithically the same substrate as the probe electrode due to a thermal problem. It is difficult to form on. Therefore, it is necessary to provide these circuits separately from the multi-probe head, and even if the multi-probe head itself can be made small, the external components become large, and as a result, small size and large capacity utilizing the characteristics of the STM. Is difficult to realize. In order to control the distance between each of the plurality of probe electrodes and the recording medium, it is necessary to read out signals from all the probe electrodes with a high S / N ratio. However, when a plurality of probe electrodes are simply arranged in a matrix and each probe electrode is selected and controlled by a switch element, signal voltage leakage due to switching, variation in gate capacitance of each switch element, etc. The N ratio decreases. An object of the present invention is to provide a multi-probe head in which a read / write circuit can be formed on the same substrate as a probe electrode and a signal from the probe electrode can be read at a high S / N ratio.

[0007]

The multi-probe head of the first invention is a multi-probe head having a plurality of probe electrodes for reproducing at least data on a recording medium, and is provided for each probe electrode. And a switch element for selecting an arbitrary probe electrode among the probe electrodes, and the probe electrode, the active element, and the switch element are formed on the same substrate. .

The multi-probe head of the second invention is a multi-probe head having a plurality of probe electrodes for reproducing at least data on a recording medium,
A first capacitance provided for each probe electrode and having one end connected to the probe electrode; a second capacitance provided for each probe electrode and not connected to the probe electrode; A switch element for selecting an arbitrary probe electrode among the probe electrodes, and the first and second corresponding to the selected probe electrode.
Read circuit for reading out the potential of the electrostatic capacitance, and the probe electrode, each of the electrostatic capacitances, the switch element, and the read circuit are formed on the same substrate.

[0009]

In the multi-probe head of the first invention, since the probe electrode, the active element provided for each probe electrode, and the switch element for selecting the probe electrode are formed on the same substrate, read / write The circuit is formed on the same substrate as the probe electrode. In this case, it is advisable to detect a minute change in tunnel current by applying a voltage to the parasitic capacitance of the active element via the switch element and reading the charge change of this parasitic capacitance to the load side of the active element. For example, a transistor can be used as the active element, and an emitter follower circuit that is an impedance conversion circuit can be used as the circuit configuration.

In the multi-probe head of the second invention,
Since the first capacitance connected to the probe electrode and the second capacitance that is a dummy for the first capacitance are provided, the change in the voltage of the first capacitance due to the tunnel current. Can be detected as the voltage difference between both capacitances, and the S / N ratio is high without being affected by the leakage current of the capacitance.
The signal can be read out as a ratio. In this case, it is desirable that the capacitance values of the first and second capacitances be substantially equal.

[0011]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a block diagram showing the configuration of a multi-probe head according to a first embodiment of the present invention. In this multi-probe head, probe electrodes are arranged in a matrix of m × n.

First, the overall circuit configuration will be described with reference to FIG. Clock CLK _x is input and n + 1 output lines c ₀
And x- shift register 7 having a to c _n, clock CL
Y− having K _y input and m + 1 output lines q _{1 to} q _{m + 1}
A shift register 8 is provided. Corresponding to each of the output lines q _{1 to} q _m , m signal reading lines 3 _{1 to} 3 _m and m voltage supply lines 4 ₁ to 4 _m are provided. One end of each signal readout line 3 ₁ to 3 _m are respectively connected to the signal line 5 provided in common through the analog switch ST ₁ ~ST _m, the bias voltage V through the analog switch SR ₁ to SR _{m bb} is applied. The bias potential _Vbb is a bias potential for keeping a MOSFET (MOS field effect transistor) 9 described later in an active state. Further, _one ends of the respective voltage supply lines 4 ₁ to 4 _m are connected to the commonly provided bias line 6 via the analog switches SX _{1 to} SX _m , respectively. Analog switch _{ST 1 ~ST m, SX 1 ~SX} m , the gate control is performed by the output line q ₁ to q _m of the corresponding analog switches SR ₁ to SR _m each output line q ₂ ~q _{m + 1}
Gate control is done in. That is, the analog switches ST _i and SX _i are gate-controlled by the i-th (1 ≦ i ≦ m) output line q _i , and the analog switch SR _i is gate-controlled by the i + 1-th output line q _{i + 1.} . Further, load capacities CR _{1 to} CR _m are equivalently connected to the signal read lines 3 _{1 to} 3 _m , respectively. The values of the load capacitors CR _{1 to} CR _m are, for example, about several pF.

One end of the signal line 5 is connected to the gate of the MOSFET 9, the power source voltage V _cc is supplied to the source of the MOSFET 9, and the drain is connected to the output terminal V _out . Bias line 6 has three analog switches S
_A write bias voltage V _w , an erase bias voltage V _d , and a read bias voltage V _r are applied via _w , S _d , and S _r , respectively. The analog switches S _w , S _d , and S _r have write clock signal φ _w and erase clock signal φ, respectively.
Gate control is performed by _d and the read clock signal φ _r .

(M · n) probe electrodes P_1,1~ P_{m, n}
Are provided, and these probe electrodes P _1,1~ P_{m, n}Corresponding to
Analog switch SA_1,1~ SA_{m, n}, SB_1,1~ S
B_{m, n}And bipolar transistor TR_1,1~ TR_{m, n}
Is provided. Each probe electrode P_1,1~ P_{m, n}Around
Since all the circuits are the same, here, (i
1 ≦ i ≦ m, 1 ≦ j ≦ n) probe electrode P_{i, j}Nitsu
And explain. Transistor TR_{i, j}The collector of
Source voltage V_ccIs applied to the probe electrode on the base_{i , j}But
It is connected. Furthermore, this bass is an analog switch
Chi SB_{i, j}Via the i-th voltage supply line 4_iConnected to
There is.

The analog switch SB _{i, j} is gate-controlled by the j-th output line c _j from the x-shift register 7. Transistor TR _i, emitter of _j, the analog switches SA _i, is connected to the i-th signal read lines 4 _i through _j, the analog switches SA _{i, j}
Is the j-1th output line c from the x-shift register
Gate controlled by _j-1 .

Since the multi-probe head is configured as described above, an equivalent circuit diagram in the case of paying attention to the probe electrode P _{i, j} in the _i- th row and the j-th column among the plurality of probe electrodes is shown in FIG. It becomes like a thing. That is, the tip of the probe electrode P _{i, j faces} the recording medium layer 2 provided on the grounded substrate 1. A recording medium 10 is composed of the substrate 1 and the recording medium layer 2. As the recording medium layer 2, for example, the above-mentioned recording material having a memory effect or a metal thin film capable of forming minute unevenness can be used.

The probe electrode P _{i, j} is a transistor TR _{i, j}
The base capacitance CS _{i, j of the} transistor _{i, j} is equivalently inserted between the base and the ground. Further, this base is connected to the bias line 6 via the analog switch SB _{i, j} and the voltage supply line 4 _i . The bias line 6 has an analog switch S _r ,
The read bias voltage V _r , the write bias voltage V _w , and the erase bias voltage V _d are applied via S _w and S _d , respectively.

The power supply voltage V _cc is supplied to the collector of the transistor TR _{i, j} and the emitter thereof is the analog switch SA.
It is connected to the signal readout line 3 _i via _{i, j} . The load capacitance CR _i is equivalently connected to the signal read line 3 _i as described above, and the bias potential V _bb is applied via the analog switch SR _i .
The signal readout line 3 _i is connected to the MOSFET 9 via the signal line 5.
Is connected to the gate. The power supply voltage V _cc is applied to the source of the MOSFET 9 and the load resistance RL is applied to the drain.
And the output terminal V _out are connected.

Next, the operation of this multi-probe head will be described. The principle of signal reading in this multi-probe head is that the electric charge accumulated in the base capacitance CS _{i, j} of the transistor TR _{i, j} flows out to the recording medium layer 2 via the probe electrode P _{i, j} and the base potential of The change is transferred to the load capacitance CR _i of the signal read line 3 _i via the emitter follower circuit composed of the transistor TR _{i, j} and the analog switch SA _{i, j,} and the potential of the load capacitance CR _i is transferred to the analog switch ST _i. Through MOSF
It is to be taken out by the source follower circuit composed of ET9. The base capacitance CS _{i, j} must be charged to a predetermined voltage before reading, but this voltage is
The voltage is supplied from the bias line 6 through the voltage supply line 4 _i and the analog switch SB _{i, j} . Further, the voltage required for writing and erasing data is also supplied from the bias line 6 to the probe electrode P _{i, j} .

Hereinafter, using the timing chart of FIG.
The operation for the probe electrode P _{i, j} will be described in more detail. The probe electrode P _{i, j} is assumed to face a predetermined position where the data of the recording medium layer 2 should be read.

First, the analog switch S _r is turned on to apply the read bias voltage V _r to the voltage supply line 4 _i . In this state, when the output line c _j is turned on and the analog switch SB _{i, j} is turned on, the transistor TR
The base potential of _{i, j} becomes the read bias voltage V _r ,
The base capacitance CS _{i, j} is charged to this potential. After that, the analog switch SB _{i, j} is turned off. The charges accumulated in the base capacitance CS _{i, j} flow out from the probe electrode P _{i, j} to the recording medium layer 2, and the potential of the probe electrode P _{i, j} , that is _, the base potential of the transistor TR _{i, j} gradually decreases. Since the current flowing out from the probe electrode P _{i , j,} that is, the tunnel current varies depending on the recording state of the recording medium layer 2 _, the base potential of the transistor TR _{i, j} after a certain period of time should vary depending on the recording state.

After a lapse of a predetermined time, the output line q _{i + 1} is turned on and the analog switch SR _{i, j} is turned on,
The potential of the signal read line 3 _i is set to the bias potential V _bb .
As a result, the load capacitance CR _i of the signal read line 3i is also charged to this potential. Then, the analog switch SR _{i, j} is turned off, and immediately thereafter, the output line c _j-1 is turned on and the analog switch SA _{i, j} is turned on. As a result, the base potential of the transistor TR _{i, j} at this time is
The data is transferred to the load capacitance CR _i of the signal read line 3 _i by the emitter follower circuit formed by the transistor TR _{i, j} . The potential of the load capacitance CR _i changed as a result of the transfer is shown in FIG.
Is indicated by an arrow. By setting h _fe of the transistor TR _{i, j} to be sufficiently large (for example, several hundreds or more), its base potential is transferred to the load capacitance CR _i without decreasing. The potential of the load capacitance CR _i at this time is output to the terminal V _out by the source follower circuit including the MOSFET 9 via the analog switch ST _i .

In FIG. 3, after the state of the analog switch SB _{i, j} changes from OFF → ON → OFF until the analog switch SA _{i, j} turns ON, the analog switch SR _{i, j} is turned on a plurality of times. The state is changing from off → on → off. Of these, those other than immediately before the analog switch SA _{i, j} is turned on are used to charge the load capacitance for reading data from the probe electrodes other than the probe electrode P _{i, j} . The time interval from the turning on of the analog switch SB _{i, j} to the turning on of the analog switch SA _{i, j} is controlled to be always constant.

By repeating the above operation sequentially for each probe electrode, a change in tunnel current due to a surface irregularity in the recording medium layer 2 or a change in electronic state is read out as a change in base potential of the transistor TR _{i, j.} It was possible to read out the data from the recording medium layer 2 satisfactorily.

Next, the recording operation will be described. Here, the binary recording, that is, the recording of "0" and "1" is referred to as an erase operation and a write operation, respectively. When performing a write operation, the analog switch S _w is turned on, applying a write bias voltage V _w to the voltage supply line 4 _i. The probe electrode P _{i, j} is opposed to a predetermined recording position on the recording medium layer 2, the analog switch SB _{i, j} is turned on, the write bias voltage V _w is applied to the probe electrode P _{i, j} , and the probe electrode P _{i, j} is turned on again. The analog switch SB _{i, j} is turned off. The potential of the probe electrode P _{i, j} gradually decreases as in the reading. The write bias voltage V _w is set to a voltage exceeding the threshold when the recording medium layer 2 uses a π-electron compound that is modulated by a voltage exceeding a certain threshold. Also,
When recording is performed by partially melting or evaporating the surface of the metal thin film, a value given by the following equation is used from the energy E required for forming the bit.

V _w ≧ [2E / C _cs ] ^1/2 (where C _cs is the capacitance value of the base capacitance CS _{i, j} ). This voltage forms a write bit in the recording medium layer 2. When performing the erase operation,
The erase bias voltage V _d is applied to the voltage supply line 4 _i , the analog switch SB _{i, j} is turned on, and the probe electrode P _{i, j.}
The voltage necessary for erasing the recorded bits may be applied to.

In the present embodiment, the data read operation from the recording medium layer is performed by discharging the electrostatic capacity in which electric charges are accumulated in advance by the tunnel current and reading the electric potential of the electrostatic capacity after the discharging by the active element. I am doing it. Of course, the electrostatic capacitance may be charged with a tunnel current, and the potential of the electrostatic capacitance after charging may be read by the active element. In this way, by reading the change in the potential of the electrostatic capacitance due to the tunnel current with the active element, it was possible to perform signal reading with a high S / N ratio and little variation between bits.
Further, in the write / erase operation, the amount of injected charge and the amount of energy required for writing or erasing in the recording medium layer can be defined by the value of the electrostatic capacitance and the charging voltage, so that the amount of charge between the probe and the recording medium layer is reduced. Even if the tunnel gap changed, abnormal current did not flow, and writing and erasing could be performed stably and with good reproducibility.

Here, the operation of selecting a specific probe electrode P _{i, j} from a plurality of probe electrodes will be supplementarily described.

One output line c of the X-shift register 7
_j-1 is selected, the analog switch SA _{i, j} for signal transfer in the corresponding column is turned on, and the transistor TR _{i, j}
Is transferred to the signal read line 3 _i of the row.
When this column is selected, the analog switch SB _{i, j-1} for charging the immediately preceding column is also turned on, and the base potential of the transistor TR _{i, j-1} is charged from the voltage supply line 4 _i . The signal transferred from the signal read line 3 _{i of} each row to the load capacitance CR _i is multiplexed (multiplexed) by the analog switch ST _i driven by the Y-shift register 8 and output to the signal line 5, and the signal is transferred by the MOSFET 9. It is output after impedance conversion. At this time, at the same time when the analog switch ST _i is turned on, the analog switch SR _i-1 of the signal readout line 3 _{i-1 in} the immediately preceding row is also turned on,
The load capacitance CR _{i-1 of the} signal read line 3 _i-1 is reset to the bias potential V _bb . That is, each load capacity CR
_When the potential of _i is read out, it is reset to the bias potential V _bb at the next clock timing to prepare for the next signal transfer cycle.

By repeating the above operation each time the column selection by the X-shift register 7 is sequentially advanced, signals can be read out from all the probe electrodes arranged in a matrix and output in time series. Further, instead of the read bias voltage V _r , the write bias voltage V _w
Alternatively, by applying the erase bias voltage V _d ,
It was possible to write or erase at the same timing as reading.

In the present embodiment, since the output of each probe electrode is amplified in the vicinity of each probe electrode on the head, crosstalk between the probe electrodes due to the matrix wiring, switching noise of the switch element, and the like are hardly affected. It can be eliminated, and reading with a high S / N ratio becomes possible. In this embodiment, a transistor is used as an active element, but in addition to this, an F element is used as an active element.
A source follower circuit configuration may be used using ET.

Next, a multi-probe head according to a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing the structure of this multi-probe head, and FIG. 5 is its timing chart.

[0033] The multi-probe head has a k number of probe electrodes P ₁ to P _k, in common to the respective probe electrodes P ₁ to P _k, shift register 102 k output clock line C
L, a bias line BL, a signal read line SL, and a dummy read line NL are provided. Shift register 102
Is for starting the shift operation by the selection signal S _in input to the selection terminal D, and turns on any one of the outputs Q _{1 to} Q _k in synchronization with the clock CLK supplied from the outside. And Gates G _{1 to} G _k are provided corresponding to the respective outputs Q _{1 to} Q _k of the shift register 102. The gates G _{1 to} G _k are respectively provided in the shift register 10
Two corresponding outputs Q _{1 to} Q _k are used as one input, the other input is connected to the clock line CL, and a logical product of the logical negation value of the other input and one input is obtained and output. . One end of the bias line BL is connected to the bias power supply V _B. Signal read line SL, dummy read line N
The read bias voltage V _r is supplied to one end of L via the analog switches S _s and S _n , respectively. These analog switches S _s and S _n are gate-controlled by a transfer clock φ supplied from the outside to the clock line CL. Signal reading line SL, and the dummy read line NL, respectively the load capacitance C _SL, C _NL is equivalently connected, these load capacitance C _SL, C _NL are mutually capacitance value is equal. A differential amplifier 108 for amplifying the potential difference between the signal read line SL and the dummy read line NL is provided, and the output V _out of the differential amplifier 108 is the signal output of the entire multi-probe head. Become.

Next, the circuit configuration around each of the probe electrodes P _{1 to} P _k will be described by taking the i-th probe electrode P _i as a representative. The other probe electrodes have the same circuit configuration.

Probe electrode P_iCorresponding to the probe voltage
Pole P_iCapacitance for charge storage inserted in parallel with
CS_iAnd dummy capacitance CN_iAnd 4 analog switches
Chi SA _i, SB_i, NA_i, NB_iAnd are provided. Anna
Log switch SA_iIs the probe electrode P_iThe signal readout line
Analog switch NA connected to SL_iIs a dummy electrostatic
Capacity CN_iFor connecting to the dummy read line NL
It is a thing. These analog switches SA_i, NA_iIs
i-th gate G_iIs gated with the output of
There is. On the other hand, analog switch SB_i, NB_iIs that
Probe electrode P_iAnd dummy capacitance CN_iBias
It is for connecting to the line BL, and is the i + 1th game
G_{i + 1}The output is gate controlled. here
So, the capacitance CS for charge storage_iAnd dummy capacitance C
N_iAnd have substantially the same capacitance value, and
Touch SA_iAnd NA_iAnd have the same characteristics, and analog switch
SB_iAnd NB_iAnd are designed to have the same characteristics.

Next, the operation of this embodiment will be described with reference to FIG. It is assumed that the clock CLK has a duty ratio of 50%, the transfer clock φ is synchronized with the clock CLK, and the duty ratio is less than 50%.

The probe electrode P _i is opposed to a predetermined recording position on the recording medium layer. When the selection signal S _in is input here, the shift register 102 starts the shift operation, and the outputs Q _{1 to} Q _k are sequentially turned on. Probe electrode P _i
, The charge storage capacitance CS _i and the dummy capacitance CN _i are the analog switch SB _i , when the output Q _{i + 1} is turned on in the previous transfer cycle. It is charged to the bias voltage V _B by NB _i . Since the probe electrode P _i is connected to the charge storage capacitance CS _i , the tunnel current flowing from the probe electrode P _i to the recording medium layer causes the voltage V _{Si at} both ends thereof to gradually drop. On the other hand, since a current source is not connected to the dummy capacitance CN _i , the voltage V _Ni across it does not change. The magnitude of the tunnel current is
Since it changes depending on the recording state in the recording medium layer, the voltage difference between the electrostatic capacitances CS _i and CN _i after a certain period of time depends on this recording state.

[0038] synchronization with the transfer clock phi, analog switches S _s, by S _n, respectively and the load capacitance C _NL of the load capacitance C _SL and the dummy read line NL in the signal readout line SL to the read bias voltage V _r Is charged up. It is assumed that the shift operation of the shift register 102 progresses and the output Q _i is turned on. The output of the gate G _i is in the off state while the transfer clock φ is in the on state, but is in the on state (the period A in the figure) at the timing when the transfer clock φ falls. As a result, the analog switch SA _i ,
Due to SA _i , the voltages V _Si and V _Ni of the electrostatic charge storage capacitance CS _i and the dummy capacitance CN _i are changed to the signal read line SL.
To the dummy read line NL, and the voltages of the load capacitors C _SL and C _NL change according to the voltages of the electrostatic capacitors CS _i and CN _i , respectively. Both read lines SL,
The potential difference between NL is read out by the differential amplifier 108, amplified, and output as a signal V _out . This signal changes according to the potential difference between the electrostatic capacitances CS _i and CN _i , that is, the data read by the probe electrode P _i .

When the output Q _{i + 1} of the shift register 102 is turned on, the output of the (i + 1) th gate G _{i + 1} is turned on at the timing when the transfer clock φ falls (illustrated period B). . At this time, the analog switch S
B _i and NB _{i charge} the respective capacitances CS _i and CN _i to the bias voltage V _B , and prepare for the next read cycle.

The read operation has been described above by focusing on the i-th probe electrode P _i , but in reality, as the shift operation of the shift register 102 progresses, data is read from each probe electrode in synchronization with the clock CLK. Are sequentially read and output as a signal V _out . That is, in the present embodiment, a series of read operations are sequentially repeated for each probe electrode using the clock CLK or the transfer clock φ synchronized with the clock CLK, resulting in unevenness modulation in the recording medium layer or a change in electronic state. The change in the tunnel current could be read as the change in the potential of the electrostatic capacitance CS _i . Further, when performing a write operation or an erase operation, the write bias voltage V _w or the erase bias voltage V _d is applied to the bias line BL instead of the read bias voltage V _r to write or erase the recording bit. The voltage required for the capacitance CS
_i just add.

In this embodiment, since the operation of reading data from the recording medium layer uses charging or discharging of electrostatic capacity by tunneling current, the influence of thermal noise is obtained even though the circuit has low current and high impedance. Less susceptible to S /
It was possible to perform signal reading with a high N ratio and little variation between bits. Furthermore, since the signal is extracted as the potential difference between the capacitance connected to the probe electrode and the dummy capacitance, the influence of capacitance variation at the probe electrode, crosstalk due to matrix wiring, and switching noise due to switch elements are eliminated. I was able to.

Next, an example of the structure of the multi-probe head of this embodiment on the substrate will be described with reference to FIGS. 6 and 7. FIG. 6 is a perspective view of this multi-probe head, and FIG. 7 is an enlarged view of the vicinity of the probe electrode.

Substrate 101 of multi-probe head 100
For example, a silicon substrate is used. Board 10
A large number of comb-shaped piezoelectric cantilevers 107 are provided outwardly on one side of each of the cantilevers 107.
A probe electrode 106 is formed on each of the upper surfaces. On the substrate 101, a capacitance 104 for charge storage and a dummy capacitance 103 corresponding to each probe electrode 106 are provided in the vicinity of each probe electrode 106. In order to reduce the influence of noise from the outside, as shown in FIG. 7, the wiring 130 extending from the probe electrode 106 to the charge storage capacitance 104 is a guard ring-shaped wiring connected to the dummy capacitance 103. Surrounded by 131.

A plurality of bonding pads 109 for connecting signal lines are arranged in a line on the side of the substrate 101 opposite to the side on which the piezoelectric cantilevers 107 are formed. As a result, the bonding pad 1
Recording and reproduction can be performed by moving a recording medium (not shown) in a direction parallel to the direction in which 09 are arranged. This bonding pad may be provided on each of two opposing sides of the substrate 101. Bonding pad 10
9 is provided with a shift register 102, and a control circuit unit 105 is formed in the center of the substrate 101. The control circuit unit 105 is integrally formed with analog switches connected to the dummy capacitances 103 and the charge storage capacitances 104, a circuit for applying a bias to the probe electrode 106, and the like. Has been done. Further, a differential amplifier 108 for outputting data is provided on the substrate 101. These circuits can be manufactured by applying a silicon IC manufacturing process.
In this case, by forming these circuits mainly with low power consumption elements centering on the CMOS circuit, there was almost no heat generation due to the circuit current, and the position control of the probe electrode was not adversely affected.

Here, the drive element for reading and writing data is integrally formed using the silicon substrate, but the present invention is not limited to the silicon substrate, and a silicon thin film is epitaxially grown on the sapphire substrate. What is called a so-called SOS substrate may be used, and further, a semiconductor layer and a substrate of any form such as a polysilicon thin film or a solid phase epitaxial film grown on a quartz substrate can be used.

FIG. 8 is a block diagram showing an example of the structure of a recording / reproducing apparatus using the multi-probe head of the present invention.

The multi-probe head 100 is mounted on the inner upper portion of the frame-shaped structure 110 via an actuator 112.
Is attached, and the substrate 1 of the recording medium 10 is attached to the inside lower part of the structure 110 via the actuator 113 so as to face this. The actuator 112 is driven by the scanning circuit 111. The recording medium layer 2 is provided on the substrate 1 of the recording medium 10, and the recording medium layer 2 and the tip of the probe electrode 106 on the multi-probe head 100 side are close to each other until a tunnel current can flow. The multi-probe head 100 is connected to a probe head control circuit 114 so that necessary data and control information can be exchanged between them. The output of this probe head control circuit 114 is
It is connected to both the cantilever drive circuit 116 and the tilt correction circuit 117 via the inter-recording medium distance control circuit 115. The output of the cantilever drive circuit 116 is connected to the multi-probe head 100 and used to drive each cantilever 107 (FIG. 6). On the other hand, the output of the tilt correction circuit 117 is connected to the actuator 113,
It is used to correct the inclination of the recording medium 10. Further, the probe head control circuit 114 is connected to an encoder 118 and a decoder 119 that input / output data. Here, the X direction and the Y direction are taken in the in-plane direction of the recording medium layer 2,
The direction perpendicular to the recording medium layer 2 is the Z direction.

Next, the operation of this recording / reproducing apparatus will be described. The probe head control circuit 114 provides information on the tunnel current flowing between each probe electrode 106 of the multi-probe head 100 and the recording medium layer 2 to the probe head 10.
Read every six. The tunnel current includes information recorded on the recording medium layer 2 as well as information on the distance between the probe electrode 106 and the recording medium layer 2. The probe / recording medium distance control circuit 115 detects a deviation of the probe electrode 106 from the reference position. Then, based on the detected displacement, the cantilever drive circuit 116 drives the individual cantilevers 107 (FIG. 6) in the Z direction, and controls so that the distance between the probe electrode 106 and the recording medium layer 2 is kept constant. To do. The tilt correction circuit 117
When it is necessary to correct the relative postures of the multi-probe head 100 and the recording medium 10, the actuator 113
Is driven to adjust the inclination of the recording medium 10 to correct the posture.

When recording data on the recording medium layer 2, the write data is encoded by the encoder 118, transferred to the probe head control circuit 114, and recorded on the recording medium layer 2 by the multi-probe head 100. When reading data, an address to be read is generated by a processor (not shown), and this address is transferred to the probe head control circuit 114. The probe head control circuit 114 reads the signal of each probe electrode 106 from the multi-probe head 100 according to this address and transfers it to the decoder 119. Decoder 119
Performs error detection or error correction from this signal and outputs it as read data to the outside.

[0050]

As described above, according to the first aspect of the present invention, the probe electrode, the active element provided for each probe electrode, and the switch element for selecting the probe electrode are formed on the same substrate. By this, the read / write circuit can be formed on the same substrate as the probe electrode, and high S /
There is an effect that a signal can be read well with an N ratio. Further, in the second aspect of the present invention, the change in the tunnel is provided by providing the first capacitance connected to the probe electrode and the second capacitance that is a dummy for the first capacitance. Can be formed on the same substrate as the probe electrode, and a high S / N ratio can be obtained without being affected by capacitance leakage current. There is an effect that the signal can be read by.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a multi-probe head according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an i row j in the multi-probe head of FIG.
It is an equivalent circuit diagram when paying attention to the probe electrode P _{i, j} of a row.

FIG. 3 is a timing chart of the multi-probe head of FIG.

FIG. 4 is a block diagram showing a configuration of a multi-probe head according to a second embodiment of the present invention.

5 is a timing chart of the multi-probe head of FIG.

6 is a perspective view of the multi-probe head of FIG.

FIG. 7 is an enlarged view of the vicinity of probe electrodes of the multi-probe head of FIG.

FIG. 8 is a block diagram showing an example of a configuration of a recording / reproducing apparatus using the multi-probe head of the present invention.

[Explanation of symbols]

1 substrate 2 recording medium layer 3 ₁ to 3 _m signal read lines 4 ₁ to 4 _m voltage supply line 5 signal lines 6 bias line 7 X- shift register 8 Y- shift register 9 MOSFET 10 recording medium 100 multi-probe head 101 substrate 102 Shift register 103 Dummy capacitance 104 Capacitance for charge storage 105 Control circuit unit 106 Probe electrode 107 Cantilever 108 Differential amplifier 109 Bonding pad 110 Structure 111 Scanning circuit 112,113 Actuator 114 Probe head control circuit 115 Probe probe Recording medium distance control circuit 116 cantilever drive circuit 117 tilt correction circuit 118 encoder 119 decoder

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiko Yamano 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Shunichi Shito 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Within the corporation

Claims (6)

[Claims] 1. A multi-probe head having a plurality of probe electrodes for reproducing at least data from a recording medium, wherein an active element provided for each probe electrode and an arbitrary probe of the probe electrodes. A multi-probe head having a switch element for selecting an electrode, wherein the probe electrode, the active element, and the switch element are formed on the same substrate. 2. The multi-probe head according to claim 1, wherein a transistor is used as an active element, a switch element is provided at an emitter of the transistor, and a signal from a probe electrode is read by an emitter follower circuit by the transistor. 3. A capacitance is effectively connected in parallel to each probe electrode, and a switch element for providing a predetermined charge to the capacitance is provided, and the static current is generated by a tunnel current flowing through the probe electrode. The multi-probe head according to claim 2, wherein the data is reproduced by changing the voltage across the capacitance and detecting the changed voltage. 4. A multi-probe head having a plurality of probe electrodes for reproducing at least data from a recording medium, the first capacitance being provided for each probe electrode and having one end connected to the probe electrode. A second capacitance provided for each probe electrode and not connected to the probe electrode, a switch element for selecting an arbitrary probe electrode of the probe electrodes, and the selected The first and second corresponding to probe electrodes
And a readout circuit for reading out the potential of the electrostatic capacitance, wherein the probe electrode, each of the electrostatic capacitances, the switch element, and the readout circuit are formed on the same substrate. 5. A switch element is provided for each of the first capacitance and the second capacitance.
The multi-probe head described in. 6. The multi-probe head according to claim 4, wherein the read circuit calculates the difference between the potential of the first capacitance and the potential of the second capacitance.