JPH06201791A - Generating device for inspection data of combinatorial logic circuit - Google Patents

Abstract

PURPOSE:To provide a combinatorial logic circuit inspection data generating device being simple in operation process. CONSTITUTION:An operation section 2 defines circuit formation and fixed logical expression, and an input vector extracting section 1 selects such a first test vector that the failure state of a detectable node becomes maximum. After the failure state of the node detected by the test vector is removed, a second test vector is further extracted so that number of the failure states of detectable nodes becomes maximum and until the whole failure states of the all nodes are detected, after the failure states of the nodes detected by the test vectors from the first to the (n-1)th are removed, a process for extracting the (n)th test vector where the number of the failure states of the detectable nodes becomes maximum is further repeated to generate test data where the failure states of the whole nodes are detected, and the test data are supplied to an inspecting device 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention inputs a proper combination of data to a combinational combination logic circuit and an integrated circuit composed of the combinational logic circuit so that the structure of the logic circuit is as desired. The present invention relates to a data generator for supplying data to an inspection device for inspecting whether or not the data is generated.

[0002]

2. Description of the Related Art Various failures may occur in circuits and integrated circuits composed of combinational logic circuits due to miswiring, unwiring, element failure, noise margin change due to power supply voltage fluctuation, and the like. Faults in these logic circuits are classified as follows.

Single stuck-at fault (stack at high / low)
・ One input / output terminal of the logic element in the logic circuit is "H"
Alternatively, it is fixed to "L" and a failure occurs. Multiple failures ... Multiple single failures occur simultaneously. Short-circuit failure between lines: All logic elements are normal and are caused by incorrect wiring, bridges, etc. The function itself of the logic circuit may change. Intermittent failure: This occurs when the noise margin becomes small.
Poor reproducibility.

Although there are such failures as described above, the number of multiple failures and short-circuit failures increases exponentially with respect to the circuit scale. Therefore, the number of circuits is unrealistic except for the sufficiently small circuits. Even if multiple failures occur in the circuit, most of them can be detected by the same detection method as the single stuck-at failure. The intermittent failure mainly results from the transistor level inside the integrated circuit and the state of the board on which the integrated circuit is mounted. For the above reasons, it is assumed that all logic circuit failures are single stuck-at failures, and various failure detection methods have been proposed.

In the combinational logic circuit, when one input sequence is determined, the output sequence is uniquely determined. Therefore, it is possible to detect a failure by comparing the input / output relationship between the circuit in which no failure has occurred and the circuit in which the failure has occurred. The conditions for detecting a circuit failure from the circuit input / output relationship are as follows. 1) The input pattern should be the opposite of the fault condition at the fault location. 2) Propagation of the fault condition at the fault location to the output of the circuit.

FIG. 5 shows a node d in a combinational logic circuit.
FIG. 6 is a diagram schematically showing a case where an “L” stuck-at fault occurs in FIG. In order to detect the above failure, since d is “H” from the above condition 1) (A,
B) = We need an input pattern that is (H, H). Further, from the condition 2), the node e needs to be “L”, that is, C = “H”. Therefore, stack at low of node d
In order to detect, try the following vector test. (A, B, C, Y) = (H, H, H, H) When the trial with the above vector is unsuccessful, there is a possibility that a stack at low fault has occurred at the node d in the circuit.

In order to detect these failures, it is sufficient to try all combinations of inputs and monitor the output results. However, when there are many inspection targets and the trial targets have many input terminals, a huge number of trials is required. And Therefore, it is desirable that the combinational logic circuit and the integrated circuit to be inspected can be inspected with a small number of trials.

Therefore, focusing only on the single stuck-at fault,
In the above test, the stack at low of the node d and the stack at high of the nodes b, c, f can be detected. Therefore, it is not necessary to limit the failure location and it is not necessary to test all combinations of inputs when only the quality of the combinational logic circuit is detected.

Stack at hig of all nodes of combinational logic circuit
There are two methods for detecting h / low at least once and minimizing the number of tests.

The first method is stack for a node.
Each test in which at high and stack at low are detected is a column vector. The following calculation is performed among all of these fault vectors to calculate a polynomial and form a sum of products. Of these, the product term having the smallest degree becomes the required minimum test vector. A specific example will be described below.

FIG. 6 is a diagram showing all combinations of inputs of the logic circuit of FIG. ABC is the input terminal of the logic circuit, ac ()
Represents the state of each node, st () represents the detectable fault state of the node, “0” is the “L” stuck-at fault (stack at low), and “1” is the “H” of the node. ”
Stuck-at fault (stack at high), “•” indicates that the stuck-at node failure cannot be detected.

From this result st (), column vectors ah to fl in FIG. 7 having nodes and test vectors capable of fault detection in the fault state as elements are created. Vector ah
Is a set of tests in which a stuck-at "H" fault at node a can be detected. The elements in these vectors are sum-combined terms and multiplied among all vectors. However, the multiplication performed here does not change even if the multiplication is performed between the same elements or the addition is performed between the same terms.

As a result of the above operation, each of the combinations of test vectors combined by multiplication can detect a single stuck-at fault in all nodes, and the combination with the smallest degree of this term is
This is a combination that can detect single stuck-at faults on all nodes with the minimum number of vectors.

Tmin = ah * bh * ch * dh * eh * fh * a
l * bl * cl * dl * el * fl = t3 * t7 * t5 * t7 * (t0 + t2 + t4) * (t1 + t3 +
t5) * (t1 + t3 + t5) ** t7 * (t0 + t2 + t4) * (t1 +
t3 + t5) * (t0 + t2 + t4 + t6 + t7) * (t1 + t3 + t
Five)

Hereinafter, t, the mark * of the product operation, will be omitted. = 357 (0 + 2 + 4) (1 + 3 + 5) {(0 + 2 + 4) + (6 +
7)} = 357 {(0 + 2 + 4) (1 + 3 + 5) + (0 + 2 + 4) (1 +
3 + 5) (6 + 7)}

Hereinafter, the + sign between the integration terms will be omitted. = 357 {(01 03 05 12 23 25 14 34 45) + (01 03 05 12
23 25 14 34 45) (6 + 7)} = 357 {(01 03 05 12 23 25 14 34 45) + (016 036 056
126 236 256 146 345 456 017 037 057 127 237 257 1
47 347 457)} = 01357 0357 0357 12357 2357 2357 13457 3457 3457
013567 03567 03567 123567 23567 23567 134567 34567
34567 01357 0357 0357 12357 2357 2357 13457 13457
3457

Except for the same one of the above product terms, = 01357 0357 12357 2357 13457 3457 013567 03567 12
3567 23567 134567 34567 13457 Each of the trial combinations summarized in the above product term detects a single stuck-at fault on all nodes at least once. Among them, the one with the smallest order is (t0, t3, t5, t7) (t2, t3, t5, t7) (t3, t4, t5, t7), and the minimum test vector number is 4.

Stack at hig of all nodes of combinational logic circuit
A second method for detecting h / low at least once and reducing the number of tests is to first number the output nodes of the logic elements that make up the logic circuit. Each output node is connected to the output terminal of the circuit or the input terminal of another logic circuit, and the output obtained at this output node is defined as a function of the output node of the previous stage determined by the logic element. To be done. The input node is defined as an input terminal, and the above operation is repeated until the subsequent node becomes a node connected to the output terminal of the logic circuit.

Node j is node k, l, m, n, ..., Z
Numbering is done so that the following conditions are observed when defined by ac (j) = f (ac (k), ac (l), ac (m), ac (n), ..., Ac (z)) ac (j) represents the state of the node j. At this time, j <k, l, m, n,
…, Z

Under the above conditions, when an input vector is given to a node defined as an input and a logical operation f is executed in the order of node numbers, the state vector of each node of the logic circuit uniquely determined by the input vector is obtained. As a result, 1) of the fault detection conditions described above, a detectable fault state at each node becomes clear for one input vector.

Further, it is necessary to satisfy the condition 2) of the failure detection condition, that is, the condition for the failure state to propagate to the output. This condition is expressed as follows. Node j and i, h, g,
…, When a is the input of a logic element and node k is its output, st (j) = st (k) & fac (ac (i), ac (h), ac (g), ..., ac (a)) st (j) represents whether or not the state of the node j can be propagated to the output. However, k> j, i, h, g,…, a

Among the output nodes of the logic element, the node connected to the output of the circuit can always observe itself, so st (k) is always true (set to "H"). Further, in order for the state of the input node j to the logic element whose output is the node k to propagate to the output k, the inputs i, h, g, ... Need to meet.

I, h, g, ..., A = 0 (when the logic elements are OR and NOR) i, h, g, ..., a = 1 (the logic elements are AND, N
AND) i, h = X (when the logic element is X-OR, X-NOR) i = X (when the logic element is INV) (X represents an arbitrary value)

Fac () represents the above condition. By performing the above calculation in the reverse order of the node numbers, the nodes capable of fault propagation are determined for a certain input vector. By the above operation, a node in which a failure can be detected for a certain input vector and its failure state are determined. This is first executed for all combinations of inputs, and the input vector that maximizes the number of detected faults is extracted. Further, the input vector having the maximum number of detected faults in the fault state space excluding the fault states detectable by the input vector is extracted from the other vectors excluding the input vector. An input vector having the maximum number of detected faults is extracted from the fault state space excluding the fault states detectable by the input vector group extracted by the above operation. The above operation is repeated until no new node in which a failure can be detected appears. Thus, when there is no redundant part in the combinational logic circuit, a single stuck-at fault at all nodes can be detected in the extracted vector group.

[0025]

However, the above-mentioned first method of the conventional example has the following drawbacks. As an example, in a combinational logic circuit in which the total number of nodes in the circuit is m and the number of input terminals is n, when a test vector that minimizes the number of trials is obtained by the above method, the stack
igh or stack at low The number of elements of a column vector that represents a test that can be detected is 1-2 n, and the number of column vectors is 2m.
become. Therefore, the above product-sum term operation is performed by n of 1-2.
This is a multiplication of 2m sum terms having the number of elements in the power, and there is a drawback that a very large-scale logical sum operation is required to obtain the minimum test vector.

In addition, in the second method, it is necessary to define, for each node, a condition for propagating a failure point to an output, in addition to a logical function between nodes representing the configuration of a logic circuit.

Further, in the second method, each output node is connected to the output terminal of the circuit or the input terminal of another logic circuit, and the output obtained at this output node is the logic element. It is defined as a function of the output node of the previous stage determined by. The input node is defined as an input terminal, and the above operation is repeated until the subsequent node becomes a node connected to the output terminal of the logic circuit. When the node j is defined by the nodes k, l, mn, ..., Z as follows, the numbering had to be performed so that the following conditions were observed. ac (j) = f (ac (k), ac (l), ac (m), ac (n), ..., Ac (z)) ac (j) represents the state of the node j. At this time, j <k, l, m, n,
…, Z

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a data generator having simple arithmetic processing.

[0029]

According to a first aspect of the present invention, a combination of all inputs to a combinational logic circuit composed of a plurality of logic elements is tried, and a first input vector that maximizes the number of detected faults is extracted. Furthermore, an attempt is made to extract a second input vector that maximizes the number of detected faults in the fault state space excluding the fault states that can be detected by the first input vector. , ..., 2, The data obtained by extracting the n-th input vector that maximizes the number of detected faults in the fault state space excluding the fault states that can be detected by the combinatorial logic In a combinational logic circuit test data generator that supplies an inspection device for inspecting whether or not the circuit configuration of a circuit is as desired, the definition of the circuit configuration is performed for the input / output relation of each of the logic elements When the input / output points of each logic element are a, ..., H, i in the case of, the ac (j) = fac (ac (i), ac (h), ..., ac (a)) , J> a,…,
It is characterized in that arithmetic means for generating data is provided by using a logical expression defined so as to have a relationship of h, i.

A second aspect of the present invention attempts a combination of all inputs to a combinational logic circuit composed of a plurality of logic elements, extracts a first input vector that maximizes the number of detected faults, and further extracts the first input vector. An attempt is made to extract the second input vector that maximizes the number of detected faults in the fault state space excluding the fault states that can be detected by the input vector.
Data obtained by extracting the n-th input vector that maximizes the number of detected faults in the fault state space excluding the fault states that can be detected by the input vectors of 1, n-2, ..., 2, 1. In a combinational logic circuit inspection data generator for supplying an inspection device for inspecting whether or not the circuit configuration of the combinational logic circuit is as desired, in the combinational logic circuit inspection data generator, the definition of the circuit configuration is defined by the input / output relation of each of the logic elements. And the ordering at that time is
, H, i, ac (j) = fac (ac (i), ac (h), ..., ac (a)) where j> a, ...,
Data is generated using a logical expression defined to have a relationship of h, i, and st (j) = st (k) & fst (ac (i), ac (h), ..., ac ( a))
It is characterized in that an arithmetic means for evaluating the condition is provided by using a logical expression defined so as to have a relationship of k> j, i, h, ..., a.

In a third aspect of the present invention, a combination of all inputs to a combinational logic circuit composed of a plurality of logic elements is tried, a first input vector that maximizes the number of detected faults is extracted, and further, the above-mentioned first aspect. An attempt is made to extract the second input vector that maximizes the number of detected faults in the fault state space excluding the fault states that can be detected by the input vector.
Data obtained by extracting the n-th input vector that maximizes the number of detected faults in the fault state space excluding the fault states that can be detected by the input vectors of 1, n-2, ..., 2, 1. In a combinational logic circuit inspection data generator for supplying an inspection device for inspecting whether or not the circuit configuration of the combinational logic circuit is as desired, in the combinational logic circuit inspection data generator, the definition of the circuit configuration is defined by the input / output relation of each of the logic elements. About the nodes a, b, ...
A group of nodes having storage areas for node information in h and i, and initializing the nodes connected to the input terminals, and then connecting to the above-mentioned nodes via logic elements as the execution order of defined logical operations When all the node information of is fixed,
The value obtained by monotonically increasing the maximum node information in the node information of the above node group is stored as the node information of that node, and after the above node information is confirmed in all nodes, ac (j) = fac (ac (i ), ac (h), ..., ac (a)) The logical expressions defined so as to have the relationship of), ac (h), ..., ac (a)) are executed in ascending order of node information, and st (j) = st (k) & fst (ac ( i), ac (h), ..., ac (a))
k> j, i, h, ..., a The logical expressions defined to have the relation of k> j, i, h, ..., a are executed in descending order of node information, and an arithmetic means for evaluating the failure detection condition is provided. To do.

[0032]

According to the first aspect of the present invention, it is possible to generate a pattern for detecting a single stuck-at fault in all nodes in a circuit at least once by performing a trial in which the maximum number is all combinations of inputs. it can.

According to the second aspect of the present invention, the number of cases in the maximum case is the total number of combinations of inputs, so that the pattern for detecting the single stuck-at fault of all the nodes in the circuit at least once is generated. , Automatically generate circuit failure detection conditions.

According to the third invention, when the pattern for detecting the single stuck-at fault of all the nodes in the circuit is generated at least once, the definition of the circuit can be described randomly in the input / output relation of the logic elements. To facilitate circuit definition.

[0035]

Embodiments of the first to third inventions will be described below with reference to the drawings.

In the first to third inventions, the configuration of the logic circuit is defined as follows. First, the output nodes of the logic elements forming the logic circuit are numbered. Each output node is connected to the output terminal of the circuit or the input terminal of another logic circuit, and the output obtained at this output node is defined as a function of the output node of the preceding stage. The input node is defined as an input terminal, and the above operation is repeated until the subsequent node becomes a node connected to the output terminal of the logic circuit.

Node j is node k, l, m, n, ..., Z
The numbering is such that the following condition a) is observed when defined by ac (j) = f (ac (k), ac (l), ac (m), ac (n), ..., Ac (z)) ac (j) represents the state of the node j. At this time, j <k, l, m, n,
…, Z

Under the above conditions, when an input vector is given to a node defined as an input and a logical operation f is executed in the order of the node numbers, the state vector of each node of the logic circuit uniquely determined by the input vector is obtained. As a result, the failure detection conditions 1), 1) shown in the above-mentioned conventional example
For one input vector, the detectable fault conditions at each node are revealed.

Further, it is necessary to satisfy the condition 2) of the fault detection condition, that is, the condition for the fault state to propagate to the output. This condition is expressed as follows. Node j and i, h, g,
…, When a is the input of a logic element and node k is its output, st (j) = st (k) & fac (ac (i), ac (h), ac (g), ..., ac (a)) st (j) represents whether or not the state of the node j can be propagated to the output. However, k> j (condition b))

Among the output nodes of the logic element, the node connected to the output of the circuit can always observe itself, so st (k) is always true (set to "H"). In order for the state of the input node j to the logic element whose output is the node k to propagate to the output k, the inputs i, h, g, ... It is necessary to satisfy c).

I, h, g, ..., A = 0 (when the logic elements are OR and NOR) i, h, g, ..., a = 1 (the logic elements are AND, N
AND) i, h = X (when the logic element is X-OR, X-NOR) i = X (when the logic element is INV) (X represents an arbitrary value)

Fac represents the above condition. By performing the above calculation in the reverse order of the node numbers, the nodes capable of fault propagation are determined for a certain input vector. By the above operation, a node in which a failure can be detected for a certain input vector and its failure state are determined. This is first executed for all combinations of inputs to find the input vector that maximizes the number of detected faults. Further, the input vector having the maximum number of detected faults in the fault state space excluding the fault states detectable by the input vector is obtained from the other vectors excluding the input vector. The above operation is repeated until no new node in which a failure can be detected appears. By this, when there is no redundant part in the combinational logic circuit, the single stuck-at fault of all nodes can be detected.

Hereinafter, the first invention will be described in detail with reference to examples.

FIG. 3 defines the logical input / output relationship between the nodes of FIG. Nodes a, b, c, d, e,
f corresponds to ac (0), ac (1), ac (2), ac (3), ac (4), ac (5) respectively, and b (n) is the node directly connected to the input terminal. Each digit of the power of 0 to 2 that is input to is input, and the logical operation defined below is executed in the ascending order of node numbers. As a result, when a certain input vector is obtained, the states of all the nodes are determined, and the condition 1) for performing the fault detection is determined, and which fault state can be detected at each node.

St () in FIG. 4 is the same as that in each node in FIG.
It is a figure showing the said failure detection condition 2) and the conditions for a state of a failure location to propagate to an output. Since the node directly connected to the output terminal of the logic circuit can always be monitored, the condition 2) of this node is always "1". The st () and the following parts of this equation correspond to fac () in the previous equation. The conditions of other nodes are defined as shown in FIG. 4 by other input node states and output nodes that are input to the same logic element as the node of interest. By evaluating this conditional expression in ascending order of node numbers, when a certain input vector is given, the nodes for which failure can be detected become clear.

Therefore, at the node j, if st (j) = 1 and ac (j) = 0, stack at high detection st (j) = 1 and ac (j) = 1, stack at low detection st (j If) = 0 and ac (j) = x, the failure cannot be detected.

The above processing is performed for all input vectors in FIG. 6, where "0" is an "L" stuck-at fault (stack at low) at that node, and "1" is an "H" stuck-at fault (at that node). stack at high), “•” indicates that the stuck-at fault of the node is not detected. Test 3 has the largest number of detected faults among these test results, and the input vector having the maximum number of detected faults in the fault state space excluding the fault states detectable by the input vector is the above-mentioned. A test 7 is obtained by obtaining the vector from among the other vectors except the input vector. Further, the extraction of the test vector is repeated until no fault-detectable node appears, and tests 0 and 5 are obtained. Since there is no redundant part in the combinational logic circuit, the single stuck-at fault of all nodes can be detected by the test extracted in the above operation.

FIG. 1 shows the principle described above and the second and
It is a block diagram which shows the data generator by 3rd invention roughly, In FIG. 1, 1 is an input vector extraction part which extracts 1st, 2nd input vector, 2 is beforehand based on the extraction result of an input vector. An arithmetic unit that generates data using a defined logical expression, 3 is an inspection device to which data is supplied, and 4 is a combinational logic circuit to be inspected.

Next, a schematic operation will be described with reference to the flowchart of FIG. First, in step S1, the arithmetic unit 2 defines the circuit configuration, and further, ac (j) = f (ac (i), ac
(h), ..., ac (a)) is defined as a logical expression. Next, in step S2, the input vector extraction unit 1 selects the first test (input) vector that maximizes the fault state of the detectable node, and in step S3, the fault of the node detected by the test vector is selected. After removing the states, a second test vector that maximizes the number of detectable fault states of the node is extracted, and the first to n-1 th until all fault states of all nodes are detected. After removing the fault state of the node detected by the test vector, the process of step S3 is repeated until the nth test vector that maximizes the number of fault states of the detectable node is extracted in step S4. Step S5
Generate test data that detects the failure status of all nodes.

8 to 11 are flowcharts showing the details of the processing.

Next, the second invention will be described in detail with reference to examples.

FIG. 12 defines the logical input / output relationship between the nodes of FIG. 5, and FIG. 3 shows the input / output relationship of each logic element of the logic circuit shown in FIG. The logical function represented in the above format is evaluated as to which of the above logical operations is secured in advance as a function in the processing flow of the present invention, and the processing flow such as the start address of the corresponding logical operation is determined. The information to be stored is stored in the array fun [] as the function execution order, and the function that evaluates the condition for propagating the input node with this logic element to the output is extracted from the above condition c), and is evaluated, for example. Reserve the processing flow start address, such as the function processing routine start address, in the array funst [] as the function execution order.

Further, in order to confirm the input / output relation, the node input to the logic element connected to a certain output node j is associated with the output node, secured in the array intm [], and the state of each node is obtained. , An output node to which a certain input node j is connected via a logic element is secured in the array ottm [] in association with the input node, and is used for evaluation of propagation of a fault state.

The node state is determined as follows. When the logic function is executed so as to satisfy the above condition a), first, the input pattern in the node directly connected to the input terminal is substituted, and the state of the node connected to this is determined. Therefore, the logical operations executed in the order satisfying the condition a) are always called with the input node fixed. Therefore, when the node to be determined is j, the logical function fun (j) that obtains j and its input node intm [j] are called,
The state of j is determined.

The node condition propagation condition is determined as follows. After a certain input pattern is given to the combinational logic circuit and the states of all the nodes in the circuit are determined, the condition b) is evaluated in descending order of node number. Thereby, first, the output propagation condition of the node directly connected to the output terminal is evaluated. Since the output terminal can always be monitored, the output propagation condition st () of this node is "true", and the stuck-at fault in the state opposite to the node state at this time can be detected.

If the node to be evaluated is not directly connected to the output terminal, it is possible to refer to ottm [j] to see if the output node of the logic element whose input is node j can propagate to the output terminal. Evaluate (ottm [j]). st (ottm
[j]) is evaluated from the layer closer to the output according to the condition b), and is always called when the output node has been evaluated for propagation or not.

Furthermore, funs with intm [ottm [j]] as an argument
Execute t (j) to evaluate whether the state of the node j can propagate through the logic element whose input terminal is the node j. the above
When the logical product of st (ottm [j]) and funst (j) is true, the fault state of node j can be propagated.
A stuck-at fault in the opposite state of can be detected.

Further, as described above with reference to FIGS. 3 and 6, when the input vector is obtained, the states of all the nodes are determined, and the condition 1) for performing the fault detection, which fault state can be detected in each node. Is required. further,
As described above with reference to FIGS. 4 and 5, since there is no redundant portion in the combinational logic circuit, single stuck-at faults at all nodes can be detected by the test extracted in the above operation.

13 to 16 are flowcharts showing the details of the processing.

Next, the third invention will be described in detail with reference to Examples.

Hierarchization of the above logical operations relating to the above-mentioned FIG. 12, FIG. 5, FIG. 3, etc. is performed as follows. The node j defined as an input terminal is extracted from all the nodes, and the layer "0" is stored in the array lay [j] that stores the layer of each node. Next, the layered information la of a node which supplies an input to a node j via a logic element.
By referring to y [tm [j]], it is determined whether or not all the hierarchization of these input nodes is completed. If all input nodes have been layered, the largest node among them is incremented by "1" to make the layer of that node, and the layering end information is input to layf [j]. . If the hierarchy of all the input nodes is not completed, the same operation is performed on the next node without doing anything. The above operation is repeated until all nodes are hierarchized. With the above processing, the layering of nodes is completed. As a result, by executing the logical operations in the ascending order of the layer number lay [j], each node state and output that are uniquely determined for a certain input pattern can be obtained regardless of the order in which the circuit is defined. .

FIG. 18 is a flow chart showing the details of the processing. Only steps S181 to S186 are different from FIG. 13, and steps S131 to S134 are shown in FIG.
Is the same as. In addition, steps S135 to S160
Since it is the same as FIGS. 14 to 16, it is omitted.

The above-mentioned processes in the first to third inventions are carried out with respect to the input vector given in advance, and when the trial of all input vectors is completed, the process is terminated so that the input vector with the given input vector is obtained. It is also possible to know to what extent a fault condition in the circuit can be detected.

Even if there are elements that perform sequential operations in the circuit and the integrated circuit, if the internal state of the circuit is uniquely determined by the input vector, the test vector from which the time difference between the output vector and the input vector is removed is removed. By performing the above processing in step 1, the internal combinational logic element can be inspected. In this case, if the sequential operation element is composed of a flip-flop or the like and is used as a means for transferring the data of the combinational logic element by the clock supplied from the outside of the logic element, the vector generated by the above process is tried. Even if the operation is diagnosed by doing so, there is no practical problem.

[0065]

As described above, according to the first aspect of the invention, in a combinational logic circuit composed of a plurality of logic elements, all combinations of inputs are simulated, and an input vector that maximizes the number of detected faults is obtained. . Furthermore, by performing a trial to find the input vector that maximizes the number of detected faults in the fault state space excluding the fault states that can be detected by the input vector from other vectors excluding the input vector, the maximum case It is possible to generate a pattern that detects a single stuck-at fault on all nodes in the circuit at least once by making a trial in which the number of is all combinations of inputs.

According to the second aspect of the invention, in the combinational logic circuit, all the input combinations are simulated, and the input vector that maximizes the number of detected faults is obtained. Further, the input vector having the maximum number of detected faults in the fault state space excluding the fault states detectable by the input vector is obtained from the other vectors excluding the input vector. An input vector that maximizes the number of detected faults is extracted from the fault state space excluding the fault states that can be detected by the input vector group extracted by the above operation. By repeating the above operation until a new detectable fault condition does not occur, the maximum number of inputs is all combinations of inputs, so that at least one single stuck-at fault in all nodes in the circuit is detected. There is an advantage that a circuit failure detection condition is automatically generated when a detection pattern is generated.

According to the third invention, in the combinational logic circuit, all the input combinations are simulated, and the input vector that maximizes the number of detected faults is obtained. Further, the input vector having the maximum number of detected faults in the fault state space excluding the fault states detectable by the input vector is obtained from the other vectors excluding the input vector. An input vector that maximizes the number of detected faults is extracted from the fault state space excluding the fault states that can be detected by the input vector group extracted by the above operation. By repeating the above operation until a new detectable fault condition does not occur, the maximum number of inputs is all combinations of inputs, so that at least one single stuck-at fault in all nodes in the circuit is detected. When generating a pattern to be detected, it is possible to describe the definition of the circuit at random in the input / output relationship of the logic elements, which is effective in facilitating the definition of the circuit.

[Brief description of drawings]

FIG. 1 is a block diagram schematically illustrating a data generator according to an exemplary embodiment of the present invention.

FIG. 2 is a flowchart schematically showing an operation.

FIG. 3 is an explanatory diagram showing a relationship between nodes of a combinational logic circuit.

FIG. 4 is an explanatory diagram showing a failure detection condition of each node of a combinational logic circuit.

FIG. 5 is a configuration diagram showing an example of a combinational logic circuit for explaining a processing method of the present invention and a conventional example.

FIG. 6 is an explanatory diagram showing all combinations of inputs of a combinational logic circuit.

FIG. 7 is an explanatory diagram showing a column vector whose elements are test vectors capable of detecting a failure at each node of the combinational logic circuit.

FIG. 8 is a flowchart showing a process according to the embodiment of the first invention.

FIG. 9 is a flowchart showing a continuation of the above flowchart.

FIG. 10 is a flowchart showing a continuation of the above flowchart.

FIG. 11 is a flowchart showing a continuation of the above flowchart.

FIG. 12 is an explanatory diagram showing an example of the definition of the input / output relationship of each node of the combinational logic circuit.

FIG. 13 is a flowchart showing a process according to an embodiment of the second invention.

FIG. 14 is a flowchart showing a continuation of the above flowchart.

FIG. 15 is a flowchart showing a continuation of the above flowchart.

FIG. 16 is a flowchart showing a continuation of the above flowchart.

FIG. 17 is an explanatory diagram showing the contents of an array that is determined, assigned, and evaluated in the processing flows of FIGS.

FIG. 18 is a flowchart showing a process according to an embodiment of the third invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input vector extraction part 2 Operation part 3 Inspection device 4 Combinational logic circuit

Claims (3)

[Claims] 1. A combination of all inputs to a combinational logic circuit composed of a plurality of logic elements is tried, a first input vector that maximizes the number of detected faults is extracted, and further detected by the first input vector. An attempt is made to extract the second input vector that maximizes the number of detected faults in the fault state space excluding the possible fault states, and the n-1, n-2, ...,
The data obtained by extracting the n-th input vector that maximizes the number of detected faults in the fault state space excluding the fault states that can be detected by the input vectors 2 and 1 is the circuit of the combinational logic circuit. In a combinational logic circuit test data generator that supplies an inspection device that inspects whether or not the configuration is as desired, the circuit configuration is defined for the input / output relation of each of the logic elements, and the ordering at that time is performed. , When the input / output points of each logic element are a, ..., H, i, ac (j) = fac (ac (i), ac (h), ..., ac (a)) where j> a, …,
A combinational logic circuit test data generation device characterized by comprising arithmetic means for generating data using a logical expression defined to have a relationship of h, i. 2. A combination of all inputs to a combinational logic circuit composed of a plurality of logic elements is tried, a first input vector that maximizes the number of detected faults is extracted, and further detected by the first input vector. An attempt is made to extract the second input vector that maximizes the number of detected faults in the fault state space excluding the possible fault states, and the n-1, n-2, ...,
The data obtained by extracting the n-th input vector that maximizes the number of detected faults in the fault state space excluding the fault states that can be detected by the input vectors 2 and 1 is the circuit of the combinational logic circuit. In a combinational logic circuit test data generator that supplies an inspection device that inspects whether or not the configuration is as desired, the above circuit configuration is defined for the input / output relation of each of the logic elements, and the ordering at that time is performed. , When the input / output points of each logic element are a, ..., H, i, ac (j) = fac (ac (i), ac (h), ..., ac (a)) where j> a, …,
Data is generated using a logical expression defined to have a relationship of h, i, and st (j) = st (k) & fst (ac (i), ac (h), ..., ac ( a))
A combinational logic circuit test data generator characterized in that arithmetic means is provided for evaluating a condition using a logical expression defined to have a relationship of k> j, i, h, ..., a. 3. A combination of all inputs to a combinational logic circuit composed of a plurality of logic elements is tried, a first input vector that maximizes the number of detected failures is extracted, and further detected by the first input vector. An attempt is made to extract the second input vector that maximizes the number of detected faults in the fault state space excluding the possible fault states, and the n-1, n-2, ...,
The data obtained by extracting the n-th input vector that maximizes the number of detected faults in the fault state space excluding the fault states that can be detected by the input vectors 2 and 1 is the circuit of the combinational logic circuit. In a combinational logic circuit inspection data generator that supplies an inspection device that inspects whether or not the configuration is as desired, the above circuit configuration is defined for the input / output relation of each of the logic elements, and the input / output of each logic element is performed. Node a as an output point,
b, ..., H, and i have node information storage areas, and after initializing the nodes connected to the input terminals, the nodes are connected to the above nodes via logic elements as the execution order of the defined logical operation. When all the node information of the existing node group is confirmed, the value obtained by monotonically increasing the maximum node information among the node information of the above node group is stored as the node information of that node, and the above node information is stored in all nodes. Then, the logical expressions defined to have a relation of ac (j) = fac (ac (i), ac (h), ..., ac (a)) are executed in ascending order of node information. , St (j) = st (k) & fst (ac (i), ac (h),…, ac (a)) where
k> j, i, h, ..., a The logical expressions defined to have the relation of k> j, i, h, ..., a are executed in descending order of node information, and an arithmetic means for evaluating the failure detection condition is provided. Combined logic circuit test data generation device.