JPH0620143B2 - Tunnel injection static induction transistor - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a tunnel injection static induction transistor.

[Prior art and its problems]

An electrostatic induction transistor (hereinafter abbreviated as SIT) is a transistor that controls the current between a source and a drain by changing the height of a potential barrier generated by connecting a depletion layer between gates. .

At this time, since the potential is controlled through the capacitance of the depletion layer, it corresponds to a bipolar transistor having no storage capacitance in the base layer, and operates at very high speed and low noise as compared with an FET. It has excellent characteristics.

However, the conventional SIT has a structure in which the size between the source and the drain, particularly between the source and the gate is relatively large, so that there is a problem that carriers are scattered by the crystal lattice and the upper limit frequency is limited.

In order to eliminate the above-mentioned drawbacks, a thermionic emission type SIT in which carriers can move at a thermoelectron velocity without being scattered by a crystal lattice was previously proposed by the present inventors.

The electrothermal density J at this time is given by the following equation (1).

Here, q is unit charge, k is Boltzmann constant, T is absolute temperature, m ^* is effective carrier mass, ns is source impurity density, Φgs is diffusion potential of gate region and source region, V
g is the voltage applied to the gate.

S when the carrier injection state becomes the thermionic emission state
When the width of the potential barrier is set to Wg, the IT interruption frequency fc is given by the following equation (2) when the SIT is connected in cascade and the second stage input capacitance is considered.

Therefore, when GaAs is used and the width Wg of the potential barrier is 0.1 μm, the cutoff frequency fc is about 78.
It will be about 0 GHz.

From the above, the fc of the thermionic emission type SIT is at most 80.
It was 0 GHz, and a higher cutoff frequency fc was not obtained.

[Object of the Invention]

The present invention uses a tunnel injection SIT that uses quantum effect tunnel injection that exceeds the limit of the thermionic emission SIT described above.
The purpose is to provide.

[Outline of Invention]

Therefore, in the tunnel injection type SIT of the present invention, at least a part of the first conductivity type drain region of high impurity density and the second conductivity type semiconductor region formed on the drain region and opposite to the first conductivity type are formed. A channel region having
The first conductivity type tunnel injection region formed on the channel region, the second conductivity type high impurity density source region formed on the tunnel injection region, and the second conductivity type of the channel region. Contacting the semiconductor region, and
The gate region is provided with a gate region made of a semiconductor having a forbidden band width larger than that of the channel region formed at a position where the distance between the true gate region and the source region in the channel region is equal to or less than the mean free path of carriers. The feature is that the interval between regions is formed within 2λ _{D with} respect to the Debye length λ _D determined by the impurity density of the channel region.

Example of Invention

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a tunnel injection type SIT according to an embodiment of the present invention.
2 is a sectional view of FIG. In the figure, 1 is a region of the n ⁺ GaAs substrate that serves as a drain, 10 is a region of the p layer channel, and 3 and 4 are n ⁺ and p ⁺ layer tunnel injection layers provided in contact with the channel region 10. 4 of them
Is a source region, and 5 is a gate region made of Ga _1-x Al _x As. Reference numeral 9 is an insulator provided to reduce the capacitance Cgd between the gate region and the drain region. As the insulator, SiO ₂ , Si ₃ N ₄ film,
Alternatively, a polyimide resin or the like is preferable. Dielectric constant of GaAs 11
On the other hand, since Si ₃ N ₄ is 5.5, SiO ₂ is 3.8, and polyimide is 3.2, Cgd is less than half that in the case where GaAs is present. Reference numeral 6 is a drain electrode, 7 is a source electrode, and 8 is a gate electrode formed on the exposed portion of the gate region.

As can be seen from this configuration, in a compound semiconductor such as GaAs in which a good insulating film cannot be obtained, the gate region has a larger forbidden band width than GaAs, for example, Ga _1-x Al _x A
By forming a mixed crystal such as s, the gate region can resemble an insulated gate.

Further, in the configuration shown in the figure, a channel region 10 formed between the source region 4 and the drain region 1 passing between the gate regions 5 is formed.
There is a potential barrier peak inside, which is called the true gate region. When the channel length (dimension between the source region and the drain region in the channel region) is short, the position where the true gate region is generated is hardly affected by the drain voltage, and the source in the channel region 10 of the p layer is Can be closer to the area. Therefore, substantially the source region 4
The distance between the gate region 5 and the gate region 5, that is, the thickness of the n ⁺ tunnel injection region 3 is equal to or less than the mean free path, so that the dimension between the true gate region and the source region 4 is equal to or less than the mean free path of carriers. This makes it possible to obtain a high-speed tunnel injection type SIT.

In operation, when a voltage is applied to the gate region, the p layer of the gate region and the channel region are inverted, and when the region of the p layer in contact with the gate region 5 becomes the n layer, More electrons are tunnel-injected into the drain region to operate. In this case, normally-on and normally-off operations can be performed by changing the distance and thickness of the gate region and the impurity density of the channel region. The value of x of Ga _1-x Al _x As that becomes the gate region is, for example, x = 0.3. The impurity density may be undoped.

In the tunnel injection type SIT configured as described above, the cutoff frequency fc is given by the following equation (3).

From equations (3) and (4) Becomes Here, the tunnel transition time ft is the reciprocal of τ.

The tunnel transition time is given by the following equation (6).

here, Is the Planck constant divided by 2π (1.0546 × 1
^0-34 J · sec), E is the electric field strength of the tunnel junction, and a is the lattice constant. Considering the case of GaAs, the lattice constant a is set to 5.6533Å and the electric field strength E is 10 ⁶ V / cm, 5
The fc at the time of × 10 ⁶ V / cm, 7 × 10 ⁶ V / cm, and 10 ⁷ V / cm is 1.37 × from the equations (5) and (6), respectively.
10 ¹³ Hz, 6.83 × 10 ¹³ Hz, 9.56 × 10 ¹³
Hz, 1.37 × 10 ¹⁴ Hz, cutoff frequency is 1
It becomes about 00 THz. This value is about 100 times that of the thermistor emission type SIT previously proposed by the applicant, and the cutoff frequency fc of the SIT can be made extremely high by using tunnel injection based on the quantum effect rather than thermionic injection. I understand.

The length from the source region to the drain region, that is, the channel region length can be controlled to a value such as 100Å, but the gate region interval, that is, the channel region width, is
It is necessary to decide based on the Debye length. The Debye length is given by the following equation (7).

Here, n is the impurity density of the channel region, and ε is the inductivity.

In the above formula (7), when n is 10 ¹² cm ^-3 , λ _D is 3.95μ
m is 10 ¹⁴ cm ^-3 , 0.4 μm, and 10 ¹⁶ cm ^-3 is 0.04 μm.

In order to effectively control the electrons traveling from the source region to the drain region by the voltage applied to the gate region, it is necessary to roughly set the channel region width to 2λ _D or less. However, as compared with the dimension control of the channel region length, the dimension control of the channel region width is determined by the accuracy of photolithography, and therefore the dimension of the channel region width needs to be determined in consideration of the manufacturing technique. Since the current electron beam lithography can process up to 0.07 μm, the channel region width of the impurity density n = 10 ¹⁶ cm ⁻³ is 0.
It is needless to say that 08 μm can be sufficiently manufactured, and the progress of the lithography technique enables the manufacture of a thin channel region having a higher impurity density.

FIG. 2 shows an embodiment in which a buried region 11 having a high impurity density is formed in the p-channel region of the embodiment of FIG. 1 in order to more efficiently limit the electrons from the source region to the gate region. . Since the buried region 11 has a high potential barrier with respect to the electrons on the source region side, the electrons pass through both sides of the buried region in the channel region. The p-channel region in which the actually operating portion forms the gate region and the source electrode 7 may be, for example, 0.5 μm to 1 μm, which facilitates manufacturing.

FIG. 3 shows still another embodiment of the present invention in which only the channel region 10 of the p layer is brought into contact with the gate region 5 and the portion adjacent to the source region 4 is the n ⁺ region 3 and the drain region. In this structure, the portion adjacent to 1 is the n ⁻ region 2.

In addition, FIG. 4 shows the channel region 2 of the n ⁻ layer on both sides of the channel region 10 of the p layer which is in contact with the gate region 5.
Further, there is shown an example in which the tunnel injection region 3 of the n ⁺ layer is formed in contact with the upper channel region 2 and the source region 4, and Cgs can be made small and the gate region can be made small. . In this embodiment, the distance between the source region 4 and the gate region 5, that is, the dimensions of the upper channel region 2 and the tunnel injection region 3 are, of course, equal to or smaller than the mean free path of carriers.

As described above, in the embodiments of FIGS. 1 to 4 described above, by setting the distance from the source region to the true gate region to be equal to or less than the mean free path of carriers, a high-speed tunnel injection type SIT can be obtained. You will get it.

By the way, the impurity densities of the n ⁺ and p ⁺ layers in the tunnel injection region can be determined by the following equation. That is, p ⁺ , n ⁺
When the impurity density of the layer is uniform, the thickness W of the depletion layer determined by the diffusion potential Vb of 0 bias is given by the following equation.

Here, NA is the acceptor density of the p ⁺ source region 4, N _D
Is the donor density of the n ⁺ tunnel injection region 3.

The N _A when the 10 ²¹ cm ^-3, N _D 10 ¹⁹ In cm ^-3 W
Is 130Å, E is 2.16 × 10 ⁶ V / cm, N _D is 10 ²⁰
At cm ^-3 , W is 41Å and E is about 6.8 × 10 ⁶ V / cm, and fc at that time is 40 THz and 72 TH, respectively.
Be in z position.

In addition, in the above embodiments, the Ga _{1 -x} A in the gate region is
It is necessary to reduce the surface level between l _x As and GaAs as much as possible, and a small amount of P (phosphorus) such as Ga _1-x Al _x As _1-y is used so that the lattice constant matches with GaAs. ) Is preferably added to form a mixed crystal. The composition at that time is x
When y = 0.3, y = 0.01 is preferable.

The impurity density of the channel region may be set to 10 ¹⁹ cm ⁻³ from the i layer, and the tunnel injection region may be set to about 10 ¹⁸ to 10 ²¹ cm ⁻ . The source and drain electrode materials are Au-G for the n ⁺ layer.
e, Au-Ge-Ni, Au-Zn, Ag-for the p ⁺ layer
An alloy such as Zn or Cr-Au can be used.

As the electrode material of Ga _1-x Al _x As in the gate region,
In addition to the source and drain electrode materials, Ti, P
It is also possible to use a refractory metal material such as t, W, Cr, Hf, or Ni that does not form a resistive contact with Ga _1-x Al _x As.

In the fabrication of the device, the channel region and the source region are formed by a molecular layer epitaxial growth method capable of growing one molecular layer of GaAs according to the invention of the present inventors, an optical molecular layer epitaxial growth method, a vapor phase growth method, a MOCVD method,
The MBE method, the ion implantation method, etc. can be used. The source, gate, and drain electrodes can be formed by a combination of vacuum vapor deposition (resistance heating, electron beam heating, sputtering method), plasma etching, photoetching, photolithography, and the like.

Further, the semiconductor material is not limited to GaAs but InP and InA
Needless to say, the semiconductor may be a semiconductor such as a mixed crystal of s, II-VI group semiconductors, or In _1-x Ga _x P or In _1-x Ga _x As for the gate region.

〔The invention's effect〕

As described above, according to the present invention, it is possible to obtain a tunnel injection static induction transistor of high speed and low noise, which operates in three terminals such as amplification and oscillation in a high frequency range which cannot be obtained by a conventional transistor.

[Brief description of drawings]

1 to 4 are cross-sectional views of a tunnel injection type static induction transistor according to each embodiment of the present invention. 1 ... n ⁺ substrate to be a drain, 2, 10 ... Channel region, 3, 4 ... Tunnel injection region, 4 ... Source region, 5 ... Made of a semiconductor having a wider band gap than GaAs Gate region, 6 ... Drain electrode, 7 ... Source electrode, 8 ... Gate electrode, 9 ... Insulator.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kaoru Motoya 2-9-9 Yonegabukuro, Sendai-shi, Miyagi 406 (56) Reference JP-A-57-186374 (JP, A) Proceedings of the Federation Conference, pp. 537-540

Claims (5)

[Claims] 1. A drain region of the first conductivity type having a high impurity density, and a channel region having at least a portion of a second conductivity type semiconductor region formed on the drain region and opposite to the first conductivity type. The first conductivity type tunnel injection region formed on the channel region, the second conductivity type high impurity density source region formed on the tunnel injection region, and the second conductivity type of the channel region. It is made of a semiconductor that is in contact with the semiconductor region and has a larger forbidden band width than the channel region formed at a position where the distance between the true gate region and the source region in the channel region is equal to or less than the mean free path of carriers. provided with a gate region, that the distance between the gate region with respect to the Debye length lambda _D determined from the impurity concentration of the channel region, is formed within 2 [lambda] _D Tunnel injection type static induction transistor, characterized. 2. The device according to claim 1, wherein the channel region is GaAs and the gate region is Ga _1-x Al _x As.
Tunnel injection type static induction transistor formed by. 3. A tunnel injection static induction transistor according to claim 1, wherein the gate region is corrected in lattice constant with the semiconductor of the channel region. 4. A tunnel injection static induction transistor according to claim 1 or 3, wherein the gate region is Ga _1-x Al _x As _1-y P _y . 5. The gate electrode provided in contact with the gate region according to any one of claims 1 to 4, wherein the gate electrode is formed of a metal material that does not make a resistive contact with the gate region. Tunnel injection type static induction transistor.