JPH0620057A - Graphic generator - Google Patents

Graphic generator

Info

Publication number
JPH0620057A
JPH0620057A JP5337693A JP5337693A JPH0620057A JP H0620057 A JPH0620057 A JP H0620057A JP 5337693 A JP5337693 A JP 5337693A JP 5337693 A JP5337693 A JP 5337693A JP H0620057 A JPH0620057 A JP H0620057A
Authority
JP
Japan
Prior art keywords
basic
frame memory
graphic
locus
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5337693A
Other languages
Japanese (ja)
Inventor
Sanae Aoyanagi
早苗 青柳
Yoshiyuki Miyabe
義幸 宮部
Jun Yoshida
純 吉田
Yutaka Morii
豊 森井
Makoto Yoshida
良 吉田
Mikito Ishikawa
幹人 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Mobile Communications Co Ltd
Japan Broadcasting Corp
Panasonic Holdings Corp
Original Assignee
Nippon Hoso Kyokai NHK
Matsushita Communication Industrial Co Ltd
Japan Broadcasting Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Hoso Kyokai NHK, Matsushita Communication Industrial Co Ltd, Japan Broadcasting Corp, Matsushita Electric Industrial Co Ltd filed Critical Nippon Hoso Kyokai NHK
Priority to JP5337693A priority Critical patent/JPH0620057A/en
Publication of JPH0620057A publication Critical patent/JPH0620057A/en
Pending legal-status Critical Current

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  • Image Generation (AREA)

Abstract

PURPOSE:To realize the graphic generator which is capable of anti-aliasing processing simultaneous with plotting and does not generate any unnatural graphics even at the time of overlap of loca. CONSTITUTION:This graphic generator is provided with a transformation and conversion circuit part which converts input graphic data to graphic information by geometrical transformation, a gradation setting circuit 3 which gives such gradation that the luminance is different between the center picture element and peripheral picture elements, a transform operation input circuit 4 which designates the classification and the extent of geometrical transformation and the gradation, a locus generator 11 which generates a locus signal to continuously give coordinates of positions of fundamental graphics stored in a fundamental graphic memory 5, a frame memory write circuit 9 which writes fundamental graphics in a frame memory 7 where fundamental graphic on the locus are held, and an address generating circuit 10 which calculates the address of a frame memory 7 determined by the locus signal and sends the read address and the write address to the fundamental graphic memory 5 and the frame memory 7 respectively.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、複数のデジタル化され
た基本図形を用意し、それらを軌跡に沿ってフレームメ
モリに繰り返し順次描画することにより任意の図形を発
生する図形発生装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a figure generating device for generating a desired figure by preparing a plurality of digitized basic figures and repeatedly drawing them in a frame memory along a trajectory. is there.

【0002】[0002]

【従来の技術】以下、図面を参照しながら従来の図形発
生装置において、幅広い曲線を描く例を取り上げて説明
する。図4は、従来の図形発生装置の要部ブロック図を
示す。
2. Description of the Related Art An example of drawing a wide curve in a conventional graphic generator will be described below with reference to the drawings. FIG. 4 shows a block diagram of a main part of a conventional graphic generator.

【0003】図4において、1は図形入力装置で、例え
ばタブレット、マウス等がその用途に供され、使用者が
輪郭線上の点列と内部の1点の座標を入力する。入力さ
れた輪郭情報は輪郭メモリ2に記憶され、制御回路3を
通じてフレームメモリ4の対応する位置に書き込まれ
る。制御回路3は、その後、塗りつぶし装置5に塗りつ
ぶし動作の指令と輪郭メモリ2に格納された内部の1点
の座標を与える。塗りつぶし装置5は、受け取った座標
からフレームメモリ4の内容を見ながら塗りつぶしを開
始する。内部のテクスチャーは塗りつぶしパターンを保
持するパターンメモリ6の内容に従って塗りつぶす。フ
レームメモリを参照して塗りつぶす代わりに、輪郭線の
形状の幾何学的な構造とみなして塗りつぶす方式があ
る。その場合、塗りつぶし装置の構成は前記塗りつぶし
装置5と異なる構成となる。
In FIG. 4, reference numeral 1 is a figure input device, for example, a tablet, a mouse or the like is used for its purpose, and a user inputs a sequence of points on a contour line and coordinates of one point inside. The input contour information is stored in the contour memory 2 and written into the corresponding position of the frame memory 4 through the control circuit 3. After that, the control circuit 3 gives the filling device 5 a command of the filling operation and the coordinates of one internal point stored in the contour memory 2. The filling device 5 starts filling while watching the contents of the frame memory 4 from the received coordinates. The internal texture is filled according to the contents of the pattern memory 6 holding the fill pattern. Instead of referring to the frame memory for filling, there is a method of filling by considering it as a geometrical structure of the contour line shape. In that case, the structure of the filling device is different from that of the filling device 5.

【0004】他の従来例として、図6にその要部ブロッ
ク図を示す。図6において、図形入力装置1から中心線
の座標を入力し、その出力を輪郭発生装置2に接続して
輪郭線を自動的に求める。中心線と輪郭線間の垂直距離
と端点の形状を指定する輪郭操作回路3が輪郭発生装置
2の入力に接続され、輪郭線を発生する時に輪郭線の形
状を決定する。発生された輪郭線は輪郭メモリ4に保存
され、制御回路5は、塗りつぶし装置7を起動し、パタ
ーンメモリ8を参照してフレームメモリ6への塗りつぶ
しが開始される。
As another conventional example, FIG. 6 shows a block diagram of a main part thereof. In FIG. 6, the coordinates of the center line are input from the figure input device 1, and the output is connected to the contour generating device 2 to automatically obtain the contour line. A contour manipulating circuit 3 for specifying the vertical distance between the center line and the contour line and the shape of the end point is connected to the input of the contour generating device 2 and determines the shape of the contour line when generating the contour line. The generated contour line is stored in the contour memory 4, and the control circuit 5 activates the filling device 7 and refers to the pattern memory 8 to start filling the frame memory 6.

【0005】さらに、他の従来例として、図8と図9に
原理を示す。図8は中心線に並行に幅に相当する本数の
線を描く方法であり、図9は中心線と垂直方向の幅に相
当する線分を中心線の軌跡に沿いドラッギングする方法
である。
Further, as another conventional example, the principle is shown in FIGS. 8 and 9. FIG. 8 shows a method of drawing a number of lines corresponding to the width parallel to the center line, and FIG. 9 shows a method of dragging a line segment corresponding to the width in the direction perpendicular to the center line along the locus of the center line.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、図4の
構成では、使用者が輪郭線を入力する過程で多大な時間
と労力が費やされ、それは図5に示すように中心線を入
力する場合の倍以上となる。また、図6の構成とした
時、輪郭発生装置2で、例えば図7に示すような中心線
が複雑に折れ曲がっている曲線の輪郭線を発生する場合
等、非常に時間の要する複雑な処理となる。また、端点
の形状に変化を持たせたい場合、特別な処理を施さねば
ならない。図8、図9に示す方法では、平行線を描く間
隔を細かくしないと空白ができるという欠点がある。ま
た、端点の形状は特別に処理して作成する必要がある。
上記の方法では、描画速度を調節したり、実線を点線に
変えたりするために、きめ細かな配慮が必要で、処理方
法に統一性を失って装置が複雑となる。さらに、ジャギ
ーの問題については、別個の処理を施さねばならない。
However, in the configuration of FIG. 4, a great deal of time and labor is spent in the process of the user inputting the contour line, which is caused when the center line is input as shown in FIG. Is more than double. Further, when the configuration of FIG. 6 is adopted, in the contour generating device 2, for example, when a contour line of a curved line in which the center line is complicatedly bent as shown in FIG. Become. Further, if it is desired to change the shape of the end points, special processing must be performed. The method shown in FIGS. 8 and 9 has a drawback in that a blank can be formed unless the interval for drawing parallel lines is made fine. Further, the shape of the end point needs to be specially processed and created.
In the above method, since the drawing speed is adjusted and the solid line is changed to the dotted line, careful consideration is required, and the processing method loses uniformity and the apparatus becomes complicated. In addition, the jaggies issue must be treated separately.

【0007】また、基本図形が中心画素と周辺画素の輝
度の異なる階調をもつ図形の場合でも軌跡上の基本図形
をおく位置の間隔が小さい時や交差した時等、基本図形
の全ての部分を書くと意図した軌跡が現れず、アンタイ
エリアジングの効果も大きく現れない。
Even when the basic figure has a gradation in which the brightness of the central pixel is different from that of the peripheral pixels, all the parts of the basic figure such as when the distance between the positions where the basic figure is placed on the locus is small or when they intersect. When you write, the intended trajectory does not appear, and the effect of antialiasing does not appear significantly.

【0008】本発明はかかる点に鑑み、描画と同時にア
ンタイエリアジング処理が可能で、軌跡が重なった時も
不自然な図形を発生しない図形発生装置を提供すること
を目的とする。
In view of the above point, an object of the present invention is to provide a graphic generator capable of performing anti-aliasing processing at the same time as drawing and not generating an unnatural graphic even when loci overlap.

【0009】[0009]

【課題を解決するための手段】本発明は上記目的を達す
るため、デジタル化された入力図形データに幾何学変形
を施し図形情報に変換する変形変換回路部と、中心画素
と周辺画素の輝度が異なる階調を与える階調設定回路部
と、前記入力図形データの幾何学変形の種類及び量、及
び前記入力図形データの階調を指定する変形操作入力回
路とを有し、前記入力図形データに幾何学的変形変換と
階調設定を加える図形変形装置と、前記図形変形装置か
ら出力され、周辺画素と中心画素で輝度が異なる階調を
もつ基本図形を記憶する基本図形メモリと、前記基本図
形の位置の座標を連続的に与える軌跡信号を発生する軌
跡発生装置と、軌跡上の前記基本図形を保持するフレー
ムメモリと、前記フレームメモリに前記基本図形を書き
込むフレームメモリ書き込み回路と、前記軌跡信号から
決定される前記フレームメモリのアドレスを演算し、前
記基本図形メモリに読出アドレス信号を、前記フレーム
メモリに書込みアドレス信号を送出するアドレス発生回
路とを具備した構成である。
In order to achieve the above object, the present invention has a transformation conversion circuit section for subjecting digitized input figure data to a geometric transformation to transform it into figure information, and a luminance of a central pixel and peripheral pixels. The input graphic data has a gradation setting circuit section for giving different gradations, a transformation operation input circuit for designating the type and amount of geometric deformation of the input graphic data, and the gradation of the input graphic data. A graphic deforming device for performing geometrical transformation and gradation setting, a basic graphic memory for storing a basic graphic output from the graphic deforming device and having different gradations in brightness between peripheral pixels and central pixel, and the basic graphic A locus generator that generates a locus signal that continuously gives the coordinates of the position, a frame memory that holds the basic figure on the locus, and a frame memo that writes the basic figure in the frame memory. A write circuit and an address generation circuit for calculating an address of the frame memory determined from the trajectory signal and sending a read address signal to the basic graphic memory and a write address signal to the frame memory. .

【0010】[0010]

【作用】本発明は上記した構成により、基本図形の中心
画素からの距離に従って、周辺画素の輝度が、基本図形
の中心画素の輝度から背景となるフレームメモリの画素
の輝度へと変化するように周辺画素と中心画素で輝度が
異なる階調をもつ基本図形を用いることにより、基本図
形を軌跡上に配置すると同時にジャギーの取れた図形を
表示したり、さらに、軌跡に従って複数の前記基本図形
を前記フレームメモリに書き込む時に、前記基本図形が
互いに部分的な重なりをもつ場合は、フレームメモリ書
込み制御回路により、前記基本図形の中の書き込もうと
する画素の輝度が、書き込む位置にある前記フレームメ
モリ上の画素の輝度よりも前記基本図形の中心の画素の
輝度に近ければ、前記基本図形を前記フレームメモリに
書き込むよう制御して、ジャギーの取れた図形を発生す
ることが可能となる。
According to the present invention, the brightness of the peripheral pixels changes from the brightness of the central pixel of the basic graphic to the brightness of the pixel of the background frame memory according to the distance from the central pixel of the basic graphic. By using a basic figure having gradations with different brightness in the peripheral pixels and the central pixel, the basic figure is arranged on the locus and at the same time a jagged figure is displayed, and further, a plurality of the basic figures are displayed according to the locus. When writing to the frame memory, if the basic figures partially overlap each other, the frame memory write control circuit causes the brightness of the pixel to be written in the basic figure to be on the frame memory at the writing position. If the brightness of the pixel at the center of the basic graphic is closer than the brightness of the pixel, the basic graphic is written to the frame memory. Te, it is possible to generate a jaggy of balanced figure.

【0011】[0011]

【実施例】以下、本発明の実施例について、図面を参照
しながら説明する。図1は本発明の一実施例に係る図形
発生装置の要部ブロック図を示すものである。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main part of a graphic generation device according to an embodiment of the present invention.

【0012】図1において、1は、図形変形装置で、例
えば、ディジタル化されたベクトル型の入力図形に幾何
学変形を施しドット型の図形情報に変換する変形変換回
路部2と、中心画素と周辺画素の輝度が異なる階調を与
える階調設定回路部3と、変形操作入力回路4からな
る。なお、変形変換回路部2は、加算器及び乗算器等に
より作成し、階調設定回路部3はフィルターが挿入され
ており、さらにランダムに各点での濃度に変化5をつけ
る演算部が付加されている場合もある。図形変形装置1
の変形変換回路部2と階調設定回路部3に必要な設定値
は変形操作入力回路4を通じて入力される。
In FIG. 1, reference numeral 1 is a graphic transformation device, which is, for example, a transformation conversion circuit section 2 for geometrically transforming a digitized vector type input figure to convert it into dot type graphic information, and a central pixel. A gradation setting circuit section 3 that gives gradations with different brightness of peripheral pixels, and a modification operation input circuit 4. The transformation conversion circuit unit 2 is created by an adder, a multiplier, etc., the gradation setting circuit unit 3 has a filter inserted, and an arithmetic unit for randomly adding a change 5 to the density at each point is added. It may have been done. Graphic transformation device 1
The setting values required for the transformation conversion circuit section 2 and the gradation setting circuit section 3 are input through the transformation operation input circuit 4.

【0013】5は図形変形装置1の出力である基本図形
を複数個格納する基本図形メモリ、6は基本図形メモリ
5内の基本図形の中の1つを選択する基本図形指示回
路、8はフレームメモリ7に付属のフレームメモリ書込
み回路、9はフレームメモリ書込み回路8を制御するフ
レームメモリ書込み制御回路、10は軌跡発生装置11
の出力の軌跡信号を受け取り基本図形メモリ5に読み出
しアドレスを、フレームメモリ書込み回路8に書込みア
ドレスを計算して送出するアドレス発生回路、11は任
意の図形の軌跡上の各点の位置を演算する軌跡発生装
置、12は軌跡発生装置11に含まれ、指示信号を与え
ることにより軌跡の種類を選択したり、任意の時間間隔
或いは距離を置いて位置の軌跡信号をアドレス発生回路
10に発生させる軌跡制御入力回路である。
Reference numeral 5 is a basic figure memory for storing a plurality of basic figures output from the figure deforming apparatus 1, 6 is a basic figure instruction circuit for selecting one of the basic figures in the basic figure memory 5, and 8 is a frame. A frame memory writing circuit attached to the memory 7, a frame memory writing control circuit 9 for controlling the frame memory writing circuit 8, and a locus generator 11
An address generating circuit for receiving a locus signal of the output of (1) and calculating a read address to the basic figure memory 5 and a write address to the frame memory writing circuit 8, and 11 for calculating the position of each point on the locus of an arbitrary figure. The locus generating device 12 is included in the locus generating device 11, and selects a type of locus by giving an instruction signal, or generates a locus signal of a position in the address generating circuit 10 at an arbitrary time interval or distance. This is a control input circuit.

【0014】以上のように構成された本実施例の動作に
ついて説明すると、まず、変形操作入力回路4から指示
信号を与えて、入力図形に幾何学変形を施しドット型の
図形情報に変換する変形変換と、中心画素と周辺画素の
輝度が異なる階調設定を行なう。なお、例えば、階調を
もつドット型の図形が入力した場合に、変形量0、階調
変化0とし操作を加えないようにする等、入力図形に応
じて、変形変換回路部2や階調設定回路部3が動作しな
いようにすることもできる。
The operation of the present embodiment configured as described above will be described. First, a transformation is given from the transformation operation input circuit 4 to geometrically transform an input figure to convert it into dot type figure information. The conversion and the gradation setting in which the brightness of the central pixel and the peripheral pixel are different are performed. Note that, for example, when a dot-type graphic having gradation is input, the deformation conversion circuit unit 2 and the gradation are changed according to the input graphic, such as setting the deformation amount to 0 and changing the gradation to 0 so that no operation is performed. It is also possible to prevent the setting circuit unit 3 from operating.

【0015】次に、基本図形メモリ5では、図形変形装
置1の出力である基本図形を複数個記憶する。基本図形
メモリ5内の基本図形指示回路6により、その中の1つ
を選択して、フレームメモリ7に付属のフレームメモリ
書込み回路8に出力する。フレームメモリ書き込み回路
8はフレームメモリ7に基本図形を書き込む。フレーム
メモリ書き込み制御回路9は、フレームメモリ書き込み
回路8がフレームメモリ7に基本図形を書き込むか否か
を画素単位で制御する。フレームメモリ書き込み制御回
路9は、外部より作動させるかどうかを指示できる。
Next, the basic graphic memory 5 stores a plurality of basic graphics output from the graphic transformation device 1. The basic figure designating circuit 6 in the basic figure memory 5 selects one of them and outputs it to the frame memory writing circuit 8 attached to the frame memory 7. The frame memory writing circuit 8 writes a basic figure in the frame memory 7. The frame memory write control circuit 9 controls whether or not the frame memory write circuit 8 writes a basic figure in the frame memory 7 on a pixel-by-pixel basis. The frame memory write control circuit 9 can instruct whether to operate from the outside.

【0016】基本図形指示回路6は、基本図形メモリ5
の1図形の読出しアドレスとその大きさを与えるもの
で、軌跡発生装置11と同期させて軌跡上の各点が決定
される毎に異なる基本図形を選択して視覚的に特徴のあ
る効果をあげる。
The basic figure designating circuit 6 includes a basic figure memory 5
The read address and the size of one figure are given, and a different basic figure is selected every time each point on the path is determined in synchronization with the path generator 11, and a visually distinctive effect is obtained. .

【0017】軌跡発生装置11は、任意の図形の軌跡上
の各点の位置を演算する。軌跡発生装置11の出力の軌
跡信号は、アドレス発生回路10を通じて基本図形メモ
リ5とフレームメモリ書込み回路8に送出される。軌跡
発生装置11に含まれる軌跡制御入力回路12は指示信
号を与えることにより、軌跡の種類を選択したり、任意
の時間間隔或いは距離を置いて位置の軌跡信号をアドレ
ス発生回路10に発生させる。
The locus generator 11 calculates the position of each point on the locus of an arbitrary figure. The locus signal output from the locus generating device 11 is sent to the basic figure memory 5 and the frame memory writing circuit 8 through the address generating circuit 10. The locus control input circuit 12 included in the locus generation device 11 selects the type of locus by giving an instruction signal, and causes the address generation circuit 10 to generate a locus signal of a position at an arbitrary time interval or distance.

【0018】例えば、実線に比べ大きく距離をとれば点
線、あるいは距離を変化させれば一点鎖線等の線種が得
られる。時間間隔を大きくすれば、図形発生の順序がわ
かり易く表示される。
For example, if the distance is larger than that of the solid line, a dotted line can be obtained, or if the distance is changed, a line type such as a one-dot chain line can be obtained. By increasing the time interval, the order of graphic generation is displayed in an easy-to-understand manner.

【0019】アドレス発生回路10は、軌跡発生装置1
1から軌跡信号を受け取リ基本図形指示回路6の示す1
基本図形のアドレス及び大きさから基本図形メモリ5の
読み出しアドレスを計算し、フレームメモリ7の書き込
みアドレスを計算し、同期して各々に送出して制御を行
なう。フレームメモリ7に繰り返し描画された複数の基
本図形は、順次与えられた図形を構築してゆく。その過
程はフレームメモリ7に接続される表示装置によって確
認することができる。このような構成によって、基本図
形の中心の画素の輝度と周辺の画素の輝度と、フレーム
メモリ7の画素の中でその基本図形がおかれる時に周囲
にある背景の画素の輝度で、階調が順に小さく或いは大
きく変化していくよう基本図形の中心画素と周辺画素の
輝度の階調を設定した基本図形を選択することにより、
描画と同時にアンタイエリアジング処理が行なわれる
等、任意の図形を多様な表現で高い品質で発生させるこ
とが可能である。
The address generation circuit 10 is used for the locus generation device 1
1 shown by the basic figure designating circuit 6
The read address of the basic graphic memory 5 is calculated from the address and the size of the basic graphic, the write address of the frame memory 7 is calculated, and the write address is sent to each of them synchronously for control. A plurality of basic figures repeatedly drawn in the frame memory 7 sequentially construct given figures. The process can be confirmed by a display device connected to the frame memory 7. With such a configuration, the brightness of the central pixel of the basic graphic and the brightness of the peripheral pixels, and the brightness of the background pixels surrounding the basic graphic in the pixels of the frame memory 7 are the gradations. By selecting the basic figure in which the brightness gradations of the central pixel and peripheral pixels of the basic figure are set so as to change gradually or gradually,
It is possible to generate an arbitrary figure with various expressions and high quality by performing anti-aliasing processing simultaneously with drawing.

【0020】基本図形にフィルターを施した中心画素と
周辺画素に異なる輝度をもつ図形を用いた場合、例え
ば、直線を考えると、基本図形上の画素の階調度がフレ
ームメモリ上の対応する画素の階調度よりも大きけれ
ば、その画素をフレームメモリ上に書き込むようにすれ
ば、曲線の中心部分より端に向かって階調度が次第に変
化して曲線と背景の境界の部分に目立った不自然さが少
なくなり、滑らかに見えるので、フレームメモリに書き
込む時に既にジャギーが取れることとなる。
In the case of using a graphic having different brightness for the central pixel and the peripheral pixels, which are filtered on the basic graphic, for example, when a straight line is considered, the gradation degree of the pixel on the basic graphic is the same as that of the corresponding pixel on the frame memory. If the pixel is larger than the gradient, the pixel is written in the frame memory, and the gradient gradually changes from the central portion of the curve toward the end, resulting in a noticeable unnaturalness at the boundary between the curve and the background. It's less and looks smooth, so you'll already be able to get rid of jaggies when writing to the frame memory.

【0021】例えば、図2(a)の図形が図2(b)の
ようになる。なお、図2(c)は階調をもつ基本図形を
示している。これは、直線を書く時に基本図形の中心部
の画素の階調度が背景となるフレームメモリの画素の階
調度より大きい場合である。逆の場合は、基本図形の階
調度の変化の与え方も逆となる。また、図3(a)に示
すように、基本図形を軌跡に従って配置する時、基本図
形どうしが重なる場合、全ての基本図形の画素を書き込
んだ場合、図3(b)に示すように、図形を構成する一
連の画素の中で代表的な中心画素の部分が失われ、意図
した図形の表現力が小さくなったり、ジャギーを抑制し
た効果がよく見えなくなる。
For example, the figure of FIG. 2A becomes as shown in FIG. Note that FIG. 2C shows a basic figure having gradation. This is the case where the gradation of the pixel at the center of the basic figure is higher than the gradation of the pixel of the background frame memory when writing a straight line. In the opposite case, the method of changing the gradation of the basic figure is also reversed. Further, as shown in FIG. 3A, when the basic figures are arranged according to the locus, when the basic figures overlap each other, when the pixels of all the basic figures are written, as shown in FIG. A part of a representative central pixel is lost in the series of pixels constituting the, and the expressive power of the intended figure becomes small, or the effect of suppressing the jaggies cannot be seen well.

【0022】このため、基本図形を書き込む時に前の基
本図形と重なる場合には、重なる位置の基本図形の画素
とフレームメモリの画素を比較して、基本図形のその画
素が基本図形の中心画素の輝度に近い場合は書き込み、
逆の場合は書き込まないようにすると、図3(c)のよ
うに中心画素が損なわれない。
For this reason, when writing a basic figure, when it overlaps with the previous basic figure, the pixel of the basic figure at the overlapping position is compared with the pixel of the frame memory, and that pixel of the basic figure is the central pixel of the basic figure. If the brightness is close, write
In the opposite case, if the writing is not performed, the central pixel is not damaged as shown in FIG.

【0023】[0023]

【発明の効果】以上の説明から明らかなように、本発明
は、基本図形メモリの内容を、軌跡発生装置で発生した
軌跡信号に従って、順次繰り返して基本メモリに接続さ
れたフレームメモリに出力してゆくという人間が図形を
描画している動作と同じ過程をシミュレートしているた
め、任意の図形を発生するとともに、描画と同時にアン
タイエリアジング処理が行なわれるという効果がある。
また、軌跡が重なった時も不自然な図形を発生しないと
いう効果がある。
As is apparent from the above description, according to the present invention, the contents of the basic figure memory are sequentially and repeatedly output to the frame memory connected to the basic memory in accordance with the locus signal generated by the locus generator. Since the same process as that of a human being drawing a figure is simulated, there is an effect that an arbitrary figure is generated and an antialiasing process is performed simultaneously with drawing.
Further, there is an effect that an unnatural figure is not generated even when the loci overlap.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係る図形発生装置の要部ブ
ロック図
FIG. 1 is a block diagram of a main part of a graphic generation device according to an embodiment of the present invention.

【図2】基本図形とその軌跡の例を示す図FIG. 2 is a diagram showing an example of a basic figure and its trajectory.

【図3】基本図形とその軌跡の別の例を示す図FIG. 3 is a diagram showing another example of a basic figure and its trajectory.

【図4】従来例の図形発生装置の要部ブロック図FIG. 4 is a block diagram of a main part of a conventional graphic generator.

【図5】図形の入力点列の例を示す図FIG. 5 is a diagram showing an example of an input point sequence of a figure.

【図6】他の従来例の図形発生装置の要部ブロック図FIG. 6 is a block diagram of a main part of another conventional graphic generator.

【図7】図形の中心線と輪郭線の例を示す図FIG. 7 is a diagram showing an example of a center line and a contour line of a figure.

【図8】別の従来例の図形発生方法を示す図FIG. 8 is a diagram showing another conventional graphic generation method.

【図9】さらに別の従来例の図形発生方法を示す図FIG. 9 is a diagram showing another conventional graphic generation method.

【符号の説明】[Explanation of symbols]

1 図形変形装置 2 変形変換回路部 3 階調設定回路部 4 変形操作入力回路 5 基本図形メモリ 6 基本図形指示回路 7 フレームメモリ 8 フレームメモリ書込み回路 9 フレームメモリ書込み制御回路 10 アドレス発生装置 11 軌跡発生装置 12 軌跡制御入力回路 1 Figure Deformation Device 2 Deformation Conversion Circuit Section 3 Gradation Setting Circuit Section 4 Deformation Operation Input Circuit 5 Basic Figure Memory 6 Basic Figure Indication Circuit 7 Frame Memory 8 Frame Memory Write Circuit 9 Frame Memory Write Control Circuit 10 Address Generator 11 Trajectory Generation Device 12 Trajectory control input circuit

フロントページの続き (72)発明者 青柳 早苗 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 宮部 義幸 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 吉田 純 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 森井 豊 東京都渋谷区神南二丁目2番1号 日本放 送協会放送センター内 (72)発明者 吉田 良 東京都渋谷区神南二丁目2番1号 日本放 送協会放送センター内 (72)発明者 石川 幹人 神奈川県横浜市港北区綱島東四丁目3番1 号 松下通信工業株式会社内Front page continued (72) Inventor Sanae Aoyagi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Yoshiyuki Miyabe 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. Person Yoshida Jun 1006, Kadoma, Kadoma-shi, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Yutaka Morii 2-2-1, Jinnan, Shibuya-ku, Tokyo Broadcasting Center of Japan Broadcasting Corporation (72) Inventor Ryo Yoshida Tokyo 2-2-1 Jinnan, Shibuya-ku, Tokyo Broadcasting Association of Japan Broadcasting Center (72) Inventor Mikito Ishikawa 4-3-1, Tsunashima-higashi, Kohoku-ku, Yokohama-shi, Kanagawa Matsushita Communication Industrial Co., Ltd.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】デジタル化された入力図形データに幾何学
変形を施し図形情報に変換する変形変換回路部と、中心
画素と周辺画素の輝度が異なる階調を与える階調設定回
路部と、前記入力図形データの幾何学変形の種類及び
量、及び前記入力図形データの階調を指定する変形操作
入力回路とを有し、前記入力図形データに幾何学的変形
変換と階調設定を加える図形変形装置と、前記図形変形
装置から出力され、周辺画素と中心画素で輝度が異なる
階調をもつ基本図形を記憶する基本図形メモリと、前記
基本図形の位置の座標を連続的に与える軌跡信号を発生
する軌跡発生装置と、軌跡上の前記基本図形を保持する
フレームメモリと、前記フレームメモリに前記基本図形
を書き込むフレームメモリ書き込み回路と、前記軌跡信
号から決定される前記フレームメモリのアドレスを演算
し、前記基本図形メモリに読出アドレス信号を、前記フ
レームメモリに書込みアドレス信号を送出するアドレス
発生回路とを具備し、前記フレームメモリに前記基本図
形の描画を繰り返して蓄積することによって、任意の図
形を発生することを特徴とする図形発生装置。
1. A transformation conversion circuit section for geometrically transforming digitized input figure data to convert it into figure information, a gradation setting circuit section for giving gradations in which the brightness of a central pixel and peripheral pixels are different, A graphic transformation having a transformation operation input circuit for designating the type and amount of geometric transformation of input graphic data and a gradation of the input graphic data, and performing geometric transformation conversion and gradation setting on the input graphic data. Device, a basic figure memory for storing a basic figure output from the figure deforming apparatus and having gradations with different brightness in peripheral pixels and central pixels, and a trajectory signal for continuously giving coordinates of the position of the basic figure A locus generating device, a frame memory for holding the basic figure on the locus, a frame memory writing circuit for writing the basic figure in the frame memory, and before being determined from the locus signal. An address generating circuit for calculating an address of the frame memory and sending a read address signal to the basic figure memory and a write address signal to the frame memory is repeatedly stored in the frame memory by repeatedly drawing the basic figure. A figure generation device characterized by generating an arbitrary figure by doing so.
【請求項2】フレームメモリ書込み回路は、軌跡に従っ
て複数の前記基本図形を前記フレームメモリに書き込む
時に、前記基本図形が互いに部分的な重なりをもつ場合
は、前記基本図形の中の書き込もうとする画素の輝度
が、書き込む位置にある前記フレームメモリ上の画素の
輝度より前記基本図形の中心の画素の輝度に近ければ、
前記基本図形を前記フレームメモリに書き込むことによ
り、ジャギーの取れた図形を発生することを特徴とする
請求項1記載の図形発生装置。
2. A frame memory writing circuit, when writing a plurality of the basic figures in the frame memory according to a locus, if the basic figures have a partial overlap with each other, a pixel to be written in the basic figure. If the brightness of is closer to the brightness of the pixel at the center of the basic figure than the brightness of the pixel on the frame memory at the writing position,
The graphic generating apparatus according to claim 1, wherein a jagged graphic is generated by writing the basic graphic in the frame memory.
JP5337693A 1993-03-15 1993-03-15 Graphic generator Pending JPH0620057A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5337693A JPH0620057A (en) 1993-03-15 1993-03-15 Graphic generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5337693A JPH0620057A (en) 1993-03-15 1993-03-15 Graphic generator

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP8926085A Division JPS61248175A (en) 1985-04-25 1985-04-25 Graphic generating device

Publications (1)

Publication Number Publication Date
JPH0620057A true JPH0620057A (en) 1994-01-28

Family

ID=12941108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5337693A Pending JPH0620057A (en) 1993-03-15 1993-03-15 Graphic generator

Country Status (1)

Country Link
JP (1) JPH0620057A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2671861A1 (en) * 1991-01-22 1992-07-24 Carlier Paul Atmospheric solar water heater

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5990161A (en) * 1982-11-16 1984-05-24 Dainippon Ink & Chem Inc Method and device for forming composite picture
GB2140257A (en) * 1980-12-04 1984-11-21 Quantel Ltd Video image creation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2140257A (en) * 1980-12-04 1984-11-21 Quantel Ltd Video image creation
JPS5990161A (en) * 1982-11-16 1984-05-24 Dainippon Ink & Chem Inc Method and device for forming composite picture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2671861A1 (en) * 1991-01-22 1992-07-24 Carlier Paul Atmospheric solar water heater

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